MC74VHC1G09DFT2G-L22038 [ONSEMI]
Single 2-Input AND Gate, Open Drain;
| 型号： | MC74VHC1G09DFT2G-L22038 |
| 厂家： | 
ONSEMI |
| 描述： | Single 2-Input AND Gate, Open Drain 栅 |
| 文件： | 总6页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1G09
2-Input AND Gate with
Open Drain Output
The MC74VHC1G09 is an advanced high speed CMOS 2−input AND
gate with open drain output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
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The internal circuit is composed of three stages, including an open
drain output which provides the capability to set output switching level.
This allows the MC74VHC1G09 to be used to interface 5 V circuits to
MARKING
DIAGRAMS
circuits of any voltage between V and 7 V using an external resistor
and power supply.
CC
5
VX M G
The MC74VHC1G09 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
G
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
1
Features
• High Speed: t = 4.3 ns (Typ) at V = 5 V
PD
CC
• Low Internal Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
• Power Down Protection Provided on Inputs
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 16
VX M G
G
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
VX = Device Code
M
G
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
V
1
2
5
CC
IN B
IN A
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OVT
OUT Y
V
CC
GND
3
4
OUT Y
FUNCTION TABLE
Inputs
Output
Y
Figure 1. Pinout (Top View)
A
B
L
L
L
H
L
L
L
L
Z
IN A
IN B
&
OUT Y
H
H
H
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
October, 2013 − Rev. 18
MC74VHC1G09/D
MC74VHC1G09
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
−0.5 to +7.0
V
IN
−0.5 to +7.0
V
V
DC Output Voltage
Input Diode Current
Output Diode Current
DC Output Current, per Pin
−0.5 to 7.0
V
OUT
I
−20
mA
mA
mA
mA
mW
°C/W
°C
IK
I
+20
OK
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
P
Power dissipation in still air
Thermal resistance
SC−88A, TSOP−5
200
333
D
q
SC−88A, TSOP−5
JA
T
Lead temperature, 1 mm from case for 10 s
Junction temperature under bias
Storage temperature
260
L
T
J
+150
°C
T
−65 to +150
Level 1
°C
stg
MSL
Moisture Sensitivity
F
R
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 2000
> 200
N/A
V
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
500
mA
Latchup
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0.0
0.0
−55
Max
5.5
Unit
V
V
CC
DC Supply Voltage
V
IN
DC Input Voltage
5.5
V
V
OUT
DC Output Voltage
7.0
V
T
A
Operating Temperature Range
Input Rise and Fall Time
+125
°C
ns/V
t , t
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
r
f
CC
CC
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
9.4
1
37,000
4.2
1
10
100
1000
17,800
2.0
TIME, YEARS
8,900
1.0
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
MC74VHC1G09
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
0.5
0.9
1.35
1.65
V
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OL
Maximum Low−Level
IN
IH
IL
Output Voltage
I
= 50 mA
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
IL
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
40
5
mA
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
1.0
20
CC
CC
I
Power Off−Output
Leakage Current
V
V
= 5.5 V
= 5.5 V
0
0.25
2.5
OFF
OUT
IN
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
load
r
f
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
= 3.3 0.3 V C = 15 pF
6.2
8.7
8.8
10.5
14.0
12.5
16.5
t
Maximum Output
Enable Time,
Input A or B to Y
ns
CC
L
PZL
12.3
R = R = 500 W C = 50 pF
L
I
L
V
CC
= 5.0 0.5 V C = 15 pF
4.3
5.8
5.9
7.9
7.0
9.0
9.0
11.0
L
R = R = 500 W C = 50 pF
L
I
L
V
= 3.3 0.3 V C = 50 pF
8.7
5.8
6.0
12.3
7.9
10
14.0
9.0
10
16.5
11.0
10
t
Maximum Output
Disable Time
ns
pF
pF
CC
L
PLZ
R = R = 500 W
L
I
V
CC
= 5.0 0.5 V C = 50 pF
L
R = R = 500 W
L
I
C
Maximum Input Ca-
pacitance
IN
Typical @ 25°C, V = 5.0 V
CC
18
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G09
V
CC
− 7 V
V
CC
V
CC
A or B
R
OVT
L
A
B
50%
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
Y
50% V
CC
V
OL
+0.3 V
Figure 4. Output Voltage Mismatch Application
Figure 5. Switching Waveforms
V
CC
V
CC
x 2
R
1
PULSE
GENERATOR
DUT
R
T
C
R
L
L
C = 50 pF equivalent (Includes jig and probe capacitance)
L
R = R = 500 W or equivalent
L
1
R = Z
of pulse generator (typically 50 W)
T
OUT
Figure 6. Test Circuit
V
CC
V
CC
V
CC
MC74VHC1G09
MC74VHC1G03
A
B
1
2
3
5
4
MC74VHC1G09
3.3 V
B
A
2.2 kW
1.5 V
R
LED
220 W
C
D
A
B
GTL
E = (A • B) + (C+D)
Figure 7. Complex Boolean Functions
Figure 8. LED Driver
Figure 9. GTL Driver
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC1G09DFT1G
NLVVHC1G09DFT1G*
MC74VHC1G09DFT2G
NLVVHC1G09DFT2G*
MC74VHC1G09DTT1G
NLV74VHC1G09DTT1G*
SC70−5 / SC−88A / SOT−353
(Pb−Free)
3000/Tape & Reel
SOT23−5 / TSOP−5 / SC59−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MC74VHC1G09
PACKAGE DIMENSIONS
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE L
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
G
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1G09
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
EXCEED 0.15 PER SIDE. DIMENSION A.
5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
0.20 C A B
2X
0.10
T
M
5
4
3
2X
0.20
T
B
S
1
2
K
B
A
DETAIL Z
G
A
MILLIMETERS
TOP VIEW
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
C
D
0.90
0.25
1.10
0.50
J
G
H
J
K
M
0.95 BSC
C
0.01
0.10
0.20
0
0.10
0.26
0.60
10
3.00
0.05
H
SEATING
PLANE
END VIEW
C
_
_
SIDE VIEW
S
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
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MC74VHC1G09/D
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