MC74VHC1G132 [ONSEMI]
2-Input NAND Schmitt-Trigger; 2输入与非施密特触发器型号: | MC74VHC1G132 |
厂家: | ONSEMI |
描述: | 2-Input NAND Schmitt-Trigger |
文件: | 总6页 (文件大小:73K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74VHC1G132
2−Input NAND
Schmitt−Trigger
The MC74VHC1G132 is a single gate CMOS Schmitt NAND
trigger fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The MC74VHC1G132 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G132 to be used to interface 5.0 V circuits to
3.0 V circuits.
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MARKING
DIAGRAMS
5
5
1
VD M G
SC−88A/SOT−353/SC−70
DF SUFFIX
G
The MC74VHC1G132 can be used to enhance noise immunity or to
square up slowly changing waveforms.
1
5
CASE 419A
Features
• High Speed: t = 3.6 ns (Typ) at V = 5.0 V
PD
CC
5
VD AYW G
G
• Low Power Dissipation: I = 1.0 mA (Max) at T = 25°C
CC
A
1
TSOP−5/SOT−23/SC−59
DT SUFFIX
1
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 68; Equivalent Gates = 16
• Pb−Free Packages are Available
CASE 483
VD
M
A
= Device Code
= Date Code*
= Assembly Location
= Year
Y
W
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
5
V
IN B
IN A
GND
1
2
3
CC
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
4
OUT Y
OUT Y
V
CC
Figure 1. Pinout (Top View)
FUNCTION TABLE
Inputs
Output
Y
A
B
L
L
L
H
L
H
H
H
L
IN A
IN B
&
OUT Y
H
H
H
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 17
MC74VHC1G132/D
MC74VHC1G132
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
DC Supply Voltage
*0.5 to )7.0
V
V
CC
V
DC Input Voltage
−0.5 to +7.0
IN
V
DC Output Voltage
*0.5 to V )0.5
V
OUT
CC
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
−20
$20
mA
mA
mA
mA
°C
IK
I
OK
I
$12.5
$25
OUT
I
CC
T
*65 to )150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
°C
L
T
)150
°C
J
q
SC70−5/SC−88A (Note 1)
TSOP−5
350
230
°C/W
JA
P
Power Dissipation in Still Air at 85°C
SC70−5/SC−88A
TSOP−5
150
200
mW
D
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
R
V
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
ESD
I
Latchup Performance
Above V and Below GND at 125°C (Note 5)
$500
mA
LATCHUP
CC
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
5.5
Unit
V
V
DC Supply Voltage
CC
V
DC Input Voltage
0.0
5.5
V
IN
V
DC Output Voltage
0.0
V
V
OUT
CC
T
Operating Temperature Range
Input Rise and Fall Time
*55
)125
°C
ns/V
A
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
−
−
No Limit
No Limit
f
CC
CC
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
1
100
110
120
130
140
20.4
1
10
100
9.4
1000
TIME, YEARS
37,000
4.2
Figure 3. Failure Rate vs. Time Junction Temperature
17,800
2.0
8,900
1.0
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2
MC74VHC1G132
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
≤ 85°C
−55 ≤ T ≤ 125°C
A
A
V
(V)
CC
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
Positive Threshold
Voltage
3.0
4.5
5.5
1.50
2.35
2.80
1.88
2.66
3.21
2.25
3.10
3.70
1.50
2.35
2.80
2.25
3.10
3.70
1.50
2.35
2.80
2.25
3.10
3.70
V
T+
V
Negative Threshold
Voltage
3.0
4.5
5.5
0.65
1.10
1.45
1.03
1.62
2.02
1.40
2.10
2.60
0.65
1.10
1.45
1.40
2.10
2.60
0.65
1.10
1.45
1.40
2.10
2.60
V
V
V
T−
V
Hysteresis Voltage
3.0
4.5
5.5
0.30
0.40
0.50
0.85
1.05
1.20
1.60
2.00
2.25
0.30
0.40
0.50
1.60
2.00
2.25
0.30
0.40
0.50
1.60
2.00
2.25
H
V
= V or GND
2.0
1.9
2.0
1.9
1.9
V
Minimum High−Level
Output Voltage
IN
IN
CC
OH
V
I
= V or V
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.5
IH
IL
I
= −50mA
OH
= −50 mA
OH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
V
OH
OH
V
I
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Maximum Low−Level
Output Voltage
IN
IH
IL
OL
= 50 mA
OL
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
OL
OL
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
V
= V or GND
5.5
1.0
20
40
CC
IN
CC
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t /t = 3.0 ns
r f
load
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Maximum
Propagation Delay,
A or B to Y
Test Conditions
Unit
t
,
V
V
= 3.3 0.3 V
C = 15 pF
L
4.6
6.1
11.9
15.4
1.0
1.0
14.0
17.5
1.0
1.0
16.1
19.6
ns
PLH
CC
CC
t
C = 50 pF
L
PHL
= 5.0 0.5 V
C = 15 pF
L
3.6
4.3
7.7
9.7
1.0
1.0
9.0
11.0
1.0
1.0
10.3
12.3
C = 50 pF
L
C
Maximum Input
Capacitance
5.5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
11
C
PD
Power Dissipation Capacitance (Note 6)
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1G132
TEST POINT
OUTPUT
V
CC
A or B
50%
DEVICE
UNDER
TEST
GND
t
t
PLH
C *
L
PHL
Y
50% V
CC
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
†
Device Order Number
Package Type
Tape and Reel Size
MC74VHC1G132DFT1
SC70−5/SC−88A/SOT−353
178 mm (7 in)
3000 Units / Tape & Reel
M74VHC1G132DFT1G
MC74VHC1G132DFT2
M74VHC1G132DFT2G
MC74VHC1G132DTT1
M74VHC1G132DTT1G
SC70−5/SC−88A/SOT−353
(Pb−Free)
178 mm (7 in)
3000 Units / Tape & Reel
SC70−5/SC−88A/SOT−353
178 mm (7 in)
3000 Units / Tape & Reel
SC70−5/SC−88A/SOT−353
(Pb−Free)
178 mm (7 in)
3000 Units / Tape & Reel
SOT23−5/TSOP−5SC59−5
178 mm (7 in)
3000 Units / Tape & Reel
SOT23−5/TSOP−5SC59−5
(Pb−Free)
178 mm (7 in)
3000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1G132
PACKAGE DIMENSIONS
SC−88A / SOT−353 / SC70
CASE 419A−02
ISSUE H
NOTES:
A
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
B
D 5 PL
0.2 (0.008)
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
N
K
N
S
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
mm
inches
ǒ
Ǔ
1.9
0.0748
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1G132
PACKAGE DIMENSIONS
TSOP−5 / SOT23−5 / SC59−5
DT SUFFIX
CASE 483−02
ISSUE D
NOTES:
D
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. A AND B DIMENSIONS DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
B
C
S
1
2
L
G
A
MILLIMETERS
INCHES
MIN MAX
0.1142 0.1220
DIM
A
B
C
D
G
H
J
K
L
MIN
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
MAX
3.10
J
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
0.05 (0.002)
H
M
K
M
S
10
0
10
_
_
_
_
2.50
3.00 0.0985 0.1181
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1G132/D
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