MC74VHC1GT00DTT3 [ONSEMI]
AHC/VHC SERIES, 2-INPUT NAND GATE, PDSO5, SC-59, SOT-23, TSOP-5;
| 型号： | MC74VHC1GT00DTT3 |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, 2-INPUT NAND GATE, PDSO5, SC-59, SOT-23, TSOP-5 栅 输入元件 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1GT00
2-Input NAND Gate /
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
The MC74VHC1GT00 is a single gate 2–input NAND fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
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The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and
the output has a full 5V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the
input, allowing the device to be used as a logic–level translator from
3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to
3.0V CMOS Logic while operating at the high–voltage power supply.
The MC74VHC1GT00 input structure provides protection when
voltages up to 7V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT00 to be used to interface 5V circuits to 3V
MARKING
DIAGRAMS
SC–88A / SOT–353/SC–70
DF SUFFIX
d
VH
CASE 419A
Pin 1
d = Date Code
TSOP–5/SOT–23/SC–59
DT SUFFIX
circuits. The output structures also provide protection when V = 0V.
d
CC
VH
These input and output structures help prevent device destruction
caused by supply voltage – input/output voltage mismatch, battery
backup, hot insertion, etc.
CASE 483
Pin 1
d = Date Code
• High Speed: t = 3.1ns (Typ) at V = 5V
PD
CC
• Low Power Dissipation: I = 2µA (Max) at T = 25°C
CC
A
PIN ASSIGNMENT
• TTL–Compatible Inputs: V = 0.8V; V = 2.0V
IL
IH
1
2
3
4
5
IN B
IN A
GND
• CMOS–Compatible Outputs: V > 0.8V ; V < 0.1V @Load
OH
CC
OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
OUT Y
VCC
• ESD Performance: HBM > 2000V
ORDERING INFORMATION
IN B
IN A
GND
1
2
3
5
4
VCC
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
OUT Y
FUNCTION TABLE
Figure 1. 5–Lead SOT–353 Pinout (Top View)
Inputs
Output
Y
A
B
L
L
L
H
L
H
H
H
L
IN A
IN B
&
OUT Y
H
H
H
Figure 2. Logic Symbol
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 5
MC74VHC1GT00/D
MC74VHC1GT00
MAXIMUM RATINGS*
Characteristics
Symbol
Value
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
–0.5 to +7.0
–0.5 to +7.0
–0.5 to 7.0
V
IN
V
V
= 0
V
OUT
V
CC
High or Low State
–0.5 to V + 0.5
CC
Input Diode Current
I
–20
+20
mA
mA
mA
mA
mW
°C
IK
Output Diode Current
DC Output Current, per Pin
(V
< GND; V
> V
)
I
OK
OUT
OUT
CC
I
+25
OUT
DC Supply Current, V and GND
I
+50
CC
CC
Power dissipation in still air, SC–88A †
Lead temperature, 1 mm from case for 10 s
Storage temperature
P
200
D
T
260
L
T
stg
–65 to +150
°C
* Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
†Derating — SC–88A Package: –5 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Characteristics
Symbol
Min
3.0
0.0
Max
5.5
5.5
5.5
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
V
IN
V
V
= 0
V
OUT
0.0
0.0
V
CC
High or Low State
Operating Temperature Range
Input Rise and Fall Time
V
CC
T
A
–55
+125
°C
V
V
= 3.3V ± 0.3V
= 5.0V ± 0.5V
t , t
r f
0
0
100
20
ns/V
CC
CC
The q of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
JA
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time
Junction Temperature
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2
MC74VHC1GT00
DC ELECTRICAL CHARACTERISTICS
V
CC
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Symbol
Parameter
Test Conditions
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
IH
Minimum High–Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
V
IL
Maximum Low–Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
I
= V or V
= –50µA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
V
OH
Minimum High–Level
Output Voltage
IN
IH
IL
OH
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
IL
I
I
= –4mA
= –8mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
I
= V or V
= 50µA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
OL
Maximum Low–Level
Output Voltage
IN
IH
IL
OL
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
IL
I
I
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
I
I
I
Maximum Input
Leakage Current
V
= 5.5V or GND
0 to
5.5
±0.1
±1.0
±1.0
µA
µA
mA
µA
IN
IN
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
5.5
0.0
2.0
20
40
CC
CC
Quiescent Supply
Current
Input: V = 3.4V
1.35
0.5
1.50
5.0
1.65
10
CCT
OPD
IN
Output Leakage
Current
V
OUT
= 5.5V
AC ELECTRICAL CHARACTERISTICS (C
= 50 pF, Input t = t = 3.0ns)
r f
load
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Maximum
Propogation Delay,
Input A or B to Y
Test Conditions
Unit
t
t
,
V
V
= 3.0 ± 0.3V
C = 15 pF
L
4.1
5.5
10.0
13.5
11.0
15.0
13.0
17.5
ns
PLH
PHL
CC
C = 50 pF
L
= 5.0 ± 0.5V
C = 15 pF
L
3.1
3.6
6.9
7.9
8.0
9.0
9.5
10.5
CC
C = 50 pF
L
C
Maximum Input
Capacitance
5.5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0V
CC
11
C
Power Dissipation Capacitance (Note 1.)
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no–load dynamic
PD CC in CC PD
CC(OPR
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1GT00
TEST POINT
OUTPUT
3.0V
GND
A or B
50%
DEVICE
UNDER
TEST
t
t
PHL
PLH
C *
L
V
V
OH
Y
50% V
CC
OL
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
DEVICE ORDERING INFORMATION
Figure 5. Test Circuit
Device Nomenclature
Temp
Range
Identifier
Tape &
Reel
Suffix
Package Type
(Name/SOT#/
Common Name)
Circuit
Indicator
Device
Function
Package
Suffix
Device
Order Number
Tape and
Reel Size
Technology
VHC1G
SC–88A / SOT–353
/ SC–70
178 mm (7”)
3000 Unit
MC74VHC1GT00DFT2
MC74VHC1GT00DFT4
MC74VHC1GT00DTT1
MC74VHC1GT00DTT3
MC
MC
MC
MC
74
74
74
74
T00
T00
T00
T00
DF
DF
DT
DT
T2
T4
T1
T3
SC–88A / SOT–353 330 mm (13”)
/ SC–70
10000 Unit
VHC1G
TSOPS / SOT–23
/ SC–59
178 mm (7”)
3000 Unit
VHC1G
TSOPS / SOT–23
/ SC–59
330 mm (13”)
10000 Unit
VHC1G
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4
MC74VHC1GT00
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008")
P
0
K
t
P
2
D
TOP
COVER
TAPE
E
A
B
SEE NOTE 2
+
0
F
W
+
+
K
0
B
1
0
SEE
NOTE 2
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004") MAX.
R MIN.
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
BENDING RADIUS
EMBOSSMENT
100 mm
(3.937")
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039") MAX
250 mm
(9.843")
TYPICAL
COMPONENT
CENTER LINE
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 6. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 1 and 2)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
8 mm 4.35 mm 1.5 +0.1/
-0.0 mm
(0.059
1.0 mm
Min
(0.039")
1.75
±0.1 mm
(0.069
3.5
±0.5 mm
(1.38
2.4 mm
(0.094")
4.0
±0.10 mm
(0.157
4.0
±0.1 mm
(0.156
2.0
±0.1 mm
(0.079
25 mm
(0.98")
0.3
±0.05 mm
(0.01
8.0
±0.3 mm
(0.315
(0.171")
+0.004/
-0.0")
±0.004")
±0.002")
±0.004")
±0.004")
±0.002")
+0.0038/
-0.0002")
±0.012")
1. Metric Dimensions Govern–English are in parentheses for reference only.
2. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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5
MC74VHC1GT00
t MAX
13.0 mm ±0.2 mm
(0.512" ±0.008")
1.5 mm MIN
(0.06")
20.2 mm MIN
(0.795")
50 mm MIN
(1.969")
A
FULL RADIUS
G
Figure 7. Reel Dimensions
REEL DIMENSIONS
Tape Size
T&R Suffix
A Max
G
t Max
8 mm
T1, T2
178 mm
(7")
8.4 mm, +1.5 mm, -0.0
(0.33" + 0.059", -0.00)
14.4 mm
(0.56")
8 mm
T3, T4
330 mm
(13")
8.4 mm, +1.5 mm, -0.0
(0.33" + 0.059", -0.00)
14.4 mm
(0.56")
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 8. Reel Winding Direction
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6
MC74VHC1GT00
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 9. Tape Ends for Finished Goods
User Direction of Feed
T2" PIN ONE AWAY FROM
SPROCKET HOLE
Figure 10. DFT2 AND DFT4 (SC88A) Reel Configuration/Orientation
User Direction of Feed
T1" PIN ONE AWAY FROM
SPROCKET HOLE
Figure 11. DTT1 and DTT3 (TSOP5) Reel Configuration/Orientation
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7
MC74VHC1GT00
SC–88A / SOT–353 / SC–70
DF SUFFIX
5–LEAD PACKAGE
CASE 419A–01
ISSUE B
A
G
NOTES:
V
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MM.
INCHES
DIM MIN MAX
MILLIMETERS
5
1
4
3
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
–B–
S
2
0.026 BSC
0.65 BSC
---
0.004
0.004
0.004
0.010
0.012
---
0.10
0.10
0.10
0.25
0.30
K
N
S
V
M
M
0.2 (0.008)
B
D 5 PL
0.008 REF
0.20 REF
0.079
0.012
0.087
0.016
2.00
0.30
2.20
0.40
N
J
C
K
H
0.5 mm (min)
1.9 mm
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8
MC74VHC1GT00
TSOP–5 / SOT–23 / SC–59
DT SUFFIX
5–LEAD PACKAGE
CASE 483–01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
D
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
5
4
3
B
C
S
1
2
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
L
G
A
B
C
D
G
H
J
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
3.10 0.1142 0.1220
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.00 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
A
J
0.05 (0.002)
K
L
H
M
K
M
S
10
0
3.00 0.0985 0.1181
10
_
_
_
_
2.50
0.094
2.4
0.037
0.95
0.074
1.9
0.037
0.95
0.028
0.7
0.039
1.0
inches
mm
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9
MC74VHC1GT00
Notes
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10
MC74VHC1GT00
Notes
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11
MC74VHC1GT00
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are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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MC74VHC1GT00/D
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