MC74VHC1GT02DFT2G [ONSEMI]
AHC/VHC SERIES, 2-INPUT NOR GATE, PDSO5, SC-88A, SC-70, SOT-353, 5 PIN;
| 型号： | MC74VHC1GT02DFT2G |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, 2-INPUT NOR GATE, PDSO5, SC-88A, SC-70, SOT-353, 5 PIN 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC1GT02
Single 2−Input NOR Gate/
CMOS Logic Level Shifter
LSTTL−Compatible Inputs
The MC74VHC1GT02 is a single gate 2−input NOR fabricated with
silicon gate CMOS technology.
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MARKING
DIAGRAMS
The internal circuit is composed of multiple stages, including a
buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3 V
CMOS logic to 5 V CMOS Logic or from 1.8 V CMOS logic to 3 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT02 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT02 to be used to interface 5 V circuits to
3 V circuits. The output structures also provide protection when
5
5
1
VJ M G
SC−88A/SC70−5/SOT−353
DF SUFFIX
G
1
CASE 419A
5
5
VJ M G
G
1
TSOP−5/SOT23−5/SC59−5
DT SUFFIX
1
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage − input/output voltage mismatch,
battery backup, hot insertion, etc.
CASE 483
VJ = Device Code
Features
M
G
= Date Code*
= Pb−Free Package
• High Speed: t = 4.7 ns (Typ) at V = 5 V
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
• TTL−Compatible Inputs: V = 0.8 V; V = 2 V
PD
CC
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
CC
A
IL
IH
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC
OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 65
• Pb−Free Packages are Available
PIN ASSIGNMENT
1
2
3
4
5
IN B
IN A
GND
OUT Y
V
CC
5
IN B
1
2
3
V
CC
FUNCTION TABLE
Inputs
Output
Y
IN A
A
B
L
L
L
H
L
H
L
L
L
GND
4
OUT Y
H
H
Figure 1. Pinout
H
IN A
IN B
≥ 1
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Figure 2. Logic Symbol
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 11
MC74VHC1GT02/D
MC74VHC1GT02
MAXIMUM RATINGS
Symbol
Characteristics
Value
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to 7.0
CC
V
V
IN
V
V
= 0
CC
V
OUT
High or Low State
−0.5 to V + 0.5
CC
I
Input Diode Current
−20
+20
mA
mA
mA
mA
_C
IK
I
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OK
OUT
OUT CC
I
+25
OUT
I
DC Supply Current, V and GND
+50
CC
CC
T
Storage Temperature Range
*65 to )150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
_C
L
T
)150
_C
_C/W
J
q
Thermal Resistance
SC70−5/SC−88A/SOT−353 (Note 1)
SOT23−5/TSOP−5/SC59−5
350
230
JA
P
Power Dissipation in Still Air at 85_C
SC70−5/SC−88A/SOT−353
SOT23−5/TSOP−5/SC59−5
150
200
mW
D
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
R
V
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
ESD
I
Latchup Performance
Above V and Below GND at 125_C (Note 5)
$500
mA
LATCHUP
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
3.0
0.0
Max
5.5
5.5
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
V
IN
V
V
= 0
CC
0.0
0.0
V
OUT
High or Low State
V
CC
T
Operating Temperature Range
Input Rise and Fall Time
−55
+125
°C
A
t , t
r
V
V
= 3.3 V 0.3 V
= 5.0 V 0.5 V
0
0
100
20
ns/V
f
CC
CC
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature °C
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1GT02
DC ELECTRICAL CHARACTERISTICS
V
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
CC
Symbol
Parameter
Test Conditions
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
Minimum High−Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
IH
V
Maximum Low−Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
IL
V
V
= V or V
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
V
Minimum High−Level
Output Voltage
IN
IH
IL
OH
I
= −50 mA
OH
V
= V or V
IN
IH IL
= V or V
IN
IH
IL
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
OH
OH
V
V
= V or V
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
Maximum Low−Level
Output Voltage
IN
IN
IH
IL
OL
I
= 50 mA
OL
V
= V or V
IN
IH IL
= V or V
IH
IL
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OL
OL
I
Maximum Input
Leakage Current
V
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
1.0
mA
mA
IN
IN
IN
I
Maximum Quiescent
Supply Current
= V or GND
5.5
1.0
20
40
CC
CC
I
Quiescent Supply
Current
Per Input: V = 3.4 V
5.5
1.35
1.50
1.65
mA
CCT
IN
Other Input: V or
CC
GND
I
Power Off Output
Leakage Current
V
= 5.5 V
OUT
0.0
0.5
5.0
10
mA
OFF
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T
A
≤ 85°C
−55 ≤ T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
V
V
= 3.3 0.3 V C = 15 pF
4.5
5.8
10.0
13.5
11.0
15.0
13.0
17.5
ns
Maximum Propagation
Delay, Input A or B to Y
PLH
CC
CC
L
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
3.0
3.8
6.7
7.7
7.5
8.5
8.5
9.5
L
C = 50 pF
L
C
Maximum Input
Capacitance
5.5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
11
C
PD
Power Dissipation Capacitance (Note 6)
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHC1GT02
3.0 V
GND
A or B
50%
t
t
PHL
PLH
V
V
OH
OL
Y
50% V
CC
Figure 4. Switching Waveforms
TEST POINT
OUTPUT
INPUT
C *
L
*Includes all probe and jig capacitance
Figure 5. Test Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC1GT02DFT1
M74VHC1GT02DFT1G
SC70−5/SC−88A/SOT−353
SC70−5/SC−88A/SOT−353
(Pb−Free)
MC74VHC1GT02DFT2
M74VHC1GT02DFT2G
SC70−5/SC−88A/SOT−353
3000/Tape & Reel
SC70−5/SC−88A/SOT−353
(Pb−Free)
MC74VHC1GT02DTT1
M74VHC1GT02DTT1G
SOT23−5/TSOP−5/SC59−5
SOT23−5/TSOP−5/SC59−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHC1GT02
PACKAGE DIMENSIONS
SC−88A, SOT−353, SC−70
CASE 419A−02
ISSUE J
A
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
G
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5
4
3
−B−
S
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
1
2
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
0.026 BSC
0.65 BSC
M
M
D 5 PL
0.2 (0.008)
B
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
K
N
S
N
0.008 REF
0.20 REF
0.079
0.087
2.00
2.20
J
C
K
H
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
mm
inches
ǒ
Ǔ
1.9
0.0748
SCALE 20:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
MC74VHC1GT02
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
C
D
G
H
J
K
L
M
S
0.90
0.25
0.95 BSC
1.10
0.50
C
SEATING
PLANE
0.05
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
T
10
3.00
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1GT02/D
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