MC74VHC1GT50DFT1 [ONSEMI]
Noninverting Buffer / CMOS Logic Level Shifter; 非反相缓冲器/ CMOS逻辑电平转换器型号: | MC74VHC1GT50DFT1 |
厂家: | ONSEMI |
描述: | Noninverting Buffer / CMOS Logic Level Shifter |
文件: | 总8页 (文件大小:88K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74VHC1GT50
Noninverting Buffer /
CMOS Logic Level Shifter
with TTL-Compatible Inputs
The MC74VHC1GT50 is a single gate noninverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
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MARKING
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL- type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic- level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high- voltage power supply.
The MC74VHC1GT50 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT50 to be used to interface high voltage to low
voltage circuits. The output structures also provide protection when
DIAGRAMS
SC-88A / SOT-353/SC-70
DF SUFFIX
VLd
CASE 419A
Pin 1
d = Date Code
TSOP-5/SOT-23/SC-59
DT SUFFIX
VLd
CASE 483
V
CC
= 0 V. These input and output structures help prevent device
destruction caused by supply voltage - input/output voltage mismatch,
battery backup, hot insertion, etc.
Pin 1
d = Date Code
• Designed for 1.65 V to 5.5 V Operation
CC
• High Speed: t = 3.5 ns (Typ) at V = 5 V
PD
CC
• Low Power Dissipation: I = 1 mA (Max) at T = 25°C
CC
A
PIN ASSIGNMENT
• TTL-Compatible Inputs: V = 0.8 V; V = 2.0 V, V = 5 V
IL
IH
CC
1
2
3
4
5
NC
IN A
• CMOS- Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC
OL
CC
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 104; Equivalent Gates = 26
GND
OUT Y
V
CC
FUNCTION TABLE
A Input
Y Output
L
L
NC
5
V
CC
1
2
3
H
H
IN A
GND
4
OUT Y
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Pinout (Top View)
1
IN A
OUT Y
Figure 2. Logic Symbol
Semiconductor Components Industries, LLC, 2003
1
Publication Order Number:
March, 2003 - Rev. 11
MC74VHC1GT50/D
MC74VHC1GT50
MAXIMUM RATINGS (Note 1)
Symbol
Characteristics
Value
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
-0.5 to +7.0
-0.5 to +7.0
-0.5 to 7.0
CC
IN
V
V
= 0
CC
V
OUT
High or Low State
-0.5 to V + 0.5
CC
I
I
I
I
Input Diode Current
-20
+20
mA
mA
mA
mA
mW
°C/W
°C
IK
Output Diode Current
DC Output Current, per Pin
V
< GND; V
> V
OUT CC
OK
OUT
+25
OUT
CC
DC Supply Current, V and GND
+50
CC
P
Power dissipation in still air
Thermal resistance
SC-88A, TSOP-5
SC- 88A, TSOP- 5
200
D
q
333
JA
T
T
Lead temperature, 1 mm from case for 10 s
Junction temperature under bias
Storage temperature
260
L
J
+150
-65 to +150
°C
T
°C
stg
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
> 2000
> 200
N/A
V
I
Latch-Up Performance
Above V and Below GND at 125°C (Note 5)
±500
mA
Latch- Up
CC
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22-A114-A
3. Tested to EIA/JESD22-A115-A
4. Tested to JESD22-C101-A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
1.65
0.0
Max
5.5
5.5
5.5
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
V
V
= 0
CC
0.0
0.0
V
OUT
V
CC
High or Low State
T
Operating Temperature Range
Input Rise and Fall Time
-55
+125
°C
A
t , t
r
V
CC
V
CC
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
f
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Temperature °C
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 3. Failure Rate vs. Time Junction Temperature
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2
MC74VHC1GT50
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
T
A
= 25°C
T
≤ 85°C
-55 ≤ T ≤ 125°C
A
CC
A
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
V
V
Minimum
High-Level
Input Voltage
1.65 to 2.29 0.50 V
0.50 V
0.45 V
0.50 V
0.45 V
V
IH
CC
CC
CC
CC
CC
2.3 to 2.99
0.45 V
CC
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
Maximum
Low-Level
Input Voltage
1.65 to 2.29
2.3 to 2.99
0.10 V
0.15 V
0.10 V
0.15 V
0.10 V
0.15 V
V
V
IL
CC
CC
CC
CC
CC
CC
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
I
= V
1.65 to 2.99
V
CC
- 0.1
V
CC
- 0.1
V
CC
- 0.1
Minimum
High-Level
Output
IN
IH
OH
= -50 mA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
OH
Voltage
V
I
I
= V
= -4 mA
= -8 mA
V
V
IN
OH
OH
IH
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
I
= V
IL
1.65 to 2.99
0.0
0.0
0.1
0.1
0.1
V
OL
Maximum
Low-Level
Output
IN
= 50 mA
3.0
4.5
0.1
0.1
0.1
0.1
0.1
0.1
OL
Voltage
V
I
I
= V
= 4 mA
= 8 mA
V
IN
OL
OL
IL
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
I
Maximum
Input
Leakage
V
= 5.5 V or GND
0 to
5.5
$0.1
$1.0
$1.0
mA
IN
IN
Current
Maximum
Quiescent
Supply
V
IN
= V or GND
5.5
1.0
20
40
mA
CC
CC
Current
I
I
Quiescent
Supply
Current
Input: V = 3.4 V
5.5
0.0
1.35
0.5
1.50
5.0
1.65
10
mA
CCT
OPD
IN
Output
Leakage
Current
V
OUT
= 5.5 V
mA
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3
MC74VHC1GT50
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
load
r
f
-55 ≤ T
≤
A
125°C
T
A
= 25°C
T
≤ 85°C
Max
A
Min
Typ
Max
Min
Min
Max
Symbol
Parameter
Test Conditions
= 1.8 ± 0.15 V C = 15 pF
Unit
ns
t
t
,
Maximum Propagation
Delay, Input A to Y
V
V
16.6
18.0
22.0
PLH
PHL
CC
L
= 2.5 ± 0.2 V C = 15 pF
13.3
19.5
14.5
22.0
17.5
25.5
ns
CC
L
C = 50 pF
L
V
V
= 3.3 ± 0.3 V C = 15 pF
4.5
6.3
10.0
13.5
11.0
15.0
13.0
17.5
ns
CC
L
C = 50 pF
L
= 5.0 ± 0.5 V C = 15 pF
3.5
4.3
6.7
7.7
7.5
8.5
8.5
9.5
CC
L
C = 50 pF
L
C
Maximum Input
Capacitance
5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
12
C
Power Dissipation Capacitance (Note 6)
PD
6. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no-load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
TEST POINT
OUTPUT
V
CC
A
Y
50%
DEVICE
UNDER
TEST
GND
t
t
C *
L
PLH
PHL
V
V
OH
50% V
CC
OL
*Includes all probe and jig capacitance
Figure 4. Switching Waveforms
Figure 5. Test Circuit
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4
MC74VHC1GT50
DEVICE ORDERING INFORMATION
Device Nomenclature
Temp
Range
Identifier
Tape &
Reel
Suffix
Package Type
(Name/SOT#/
Common Name)
Circuit
Indicator
Device
Function
Package
Suffix
Device
Order Number
Tape and
Reel Size
Technology
VHC1G
SC-88A / SOT-353
/ SC-70
178 mm (7”)
3000 Unit
MC74VHC1GT50DFT1
MC74VHC1GT50DFT2
MC74VHC1GT50DTT1
MC
MC
MC
74
74
74
T50
T50
T50
DF
DF
DT
T1
T2
T1
SC-88A / SOT-353
/ SC-70
178 mm (7”)
3000 Unit
VHC1G
TSOP-5 / SOT-23
/ SC-59
178 mm (7”)
3000 Unit
VHC1G
TAPE TRAILER
TAPE LEADER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
NO COMPONENTS
400 mm MIN
COMPONENTS
DIRECTION OF FEED
CAVITY TOP TAPE
TAPE
Figure 6. Tape Ends for Finished Goods
“T1” Pin One Toward Sprocket Hole (3k Reel)
“T2” Pin One Opposing Sprocket Hole (3k Reel)
Figure 7. SC-88A/SOT-353/SC-70-5 DFT1 and DFT2
Reel Configuration/Orientation
“T1” Pin One Opposing Sprocket Hole (3k Reel)
Figure 8. TSOP-5/SC59-5/SOT23-5 DTT1
Reel Configuration/Orientation
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5
MC74VHC1GT50
t MAX
13.0 mm $0.2 mm
(0.512 in $0.008 in)
1.5 mm MIN
(0.06 in)
50 mm MIN
(1.969 in)
20.2 mm MIN
(0.795 in)
A
FULL RADIUS
G
Figure 9. Reel Dimensions
REEL DIMENSIONS
Tape Size
T and R Suffix
A Max
G
t Max
8 mm
T1, T2
178 mm
(7 in)
8.4 mm, + 1.5 mm, -0.0
(0.33 in + 0.059 in, -0.00)
14.4 mm
(0.56 in)
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 10. Reel Winding Direction
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6
MC74VHC1GT50
PACKAGE DIMENSIONS
SC-88A / SOT-353 / SC-70
DF SUFFIX
5-LEAD PACKAGE
CASE 419A-02
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD 419A−02.
G
INCHES
DIM MIN MAX
MILLIMETERS
MIN
1.80
1.15
0.80
0.10
MAX
2.20
1.35
1.10
0.30
5
4
3
A
B
C
D
G
H
J
0.071
0.045
0.031
0.004
0.087
0.053
0.043
0.012
-B-
S
1
2
0.026 BSC
0.65 BSC
−−−
0.004
0.004
0.004
0.010
0.012
−−−
0.10
0.10
0.10
0.25
0.30
K
N
S
0.008 REF
0.20 REF
M
M
0.2 (0.008)
B
D 5 PL
0.079
0.087
2.00
2.20
N
J
C
K
H
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
mm
inches
ǒ
Ǔ
SCALE 20:1
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7
MC74VHC1GT50
PACKAGE DIMENSIONS
TSOP-5 / SOT-23 / SC-59
DT SUFFIX
5-LEAD PACKAGE
CASE 483-01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
D
ISSUE B
5
4
3
B
C
S
1
2
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
L
G
A
B
C
D
G
H
J
2.90
1.30
0.90
0.25
0.85
0.013
0.10
0.20
1.25
0
3.10 0.1142 0.1220
1.70 0.0512 0.0669
1.10 0.0354 0.0433
0.50 0.0098 0.0197
1.05 0.0335 0.0413
0.100 0.0005 0.0040
0.26 0.0040 0.0102
0.60 0.0079 0.0236
1.55 0.0493 0.0610
A
J
0.05 (0.002)
K
L
H
M
K
M
S
10
0
3.00 0.0985 0.1181
10
_
_
_
_
2.50
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
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