MC74VHC240MR2 [ONSEMI]

AHC/VHC SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, SOIC-20;
MC74VHC240MR2
型号: MC74VHC240MR2
厂家: ONSEMI    ONSEMI
描述:

AHC/VHC SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, EIAJ, SOIC-20

驱动 光电二极管 输出元件 逻辑集成电路
文件: 总7页 (文件大小:131K)
中文:  中文翻译
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MC74VHC240  
Octal Bus Buffer/Line Driver  
Inverting with 3-State Outputs  
The MC74VHC240 is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
The MC74VHC240 is an inverting 3state buffer, and has two  
activelow output enables. This device is designed to drive bus lines  
or buffer memory address registers.  
http://onsemi.com  
MARKING  
DIAGRAMS  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
20  
20  
VHC240  
AWLYYWWG  
1
SOIC20  
High Speed: t = 3.6 ns (Typ) at V = 5 V  
DW SUFFIX  
CASE 751D  
PD  
CC  
1
Low Power Dissipation: I = 4 μA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
= V = 28% V  
NIL CC  
NIH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
20  
20  
VHC  
240  
Designed for 2 V to 5.5 V Operating Range  
1
ALYWG  
TSSOP20  
DT SUFFIX  
CASE 948E  
Low Noise: V  
= 0.9 V (Max)  
OLP  
G
1
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 120 FETs or 30 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
VHC240 = Specific Device Code  
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
WW, W  
G or G  
= Work Week  
= PbFree Package  
(Note: Microdot may be in either location)  
OEA  
A1  
1
2
3
4
5
6
7
8
9
20  
V
CC  
19 OEB  
18 YA1  
17 B4  
16 YA2  
15 B3  
14 YA3  
13 B2  
12 YA4  
11 B1  
YB4  
A2  
ORDERING INFORMATION  
Device  
Package  
Shipping  
YB3  
A3  
MC74VHC240DWR2G SOIC20 1000 Units/Reel  
MC74VHC240DTR2G TSSOP20 2500 Units/Reel  
YB2  
A4  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
YB1  
GND 10  
FUNCTION TABLE  
Figure 1. Pin Assignment  
INPUTS  
OEA, OEB  
OUTPUTS  
YA, YB  
A, B  
L
L
H
L
H
X
H
L
Z
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 5  
MC74VHC240/D  
MC74VHC240  
2
4
6
8
18  
16  
14  
12  
A1  
A2  
A3  
A4  
YA1  
YA2  
YA3  
YA4  
DATA  
INVERTING  
OUTPUTS  
INPUTS  
11  
13  
15  
17  
9
7
5
3
B1  
B2  
B3  
B4  
YB1  
YB2  
YB3  
YB4  
1
OEA  
OEB  
OUTPUT  
19  
ENABLES  
Figure 1. LOGIC DIAGRAM  
MAXIMUM RATINGS*  
Symbol  
Parameter  
Value  
Unit  
V
This device contains protection  
circuitry to guard against damage  
due to high static voltages or electric  
fields. However, precautions must  
be taken to avoid applications of any  
voltage higher than maximum rated  
voltages to this highimpedance cir-  
V
DC Supply Voltage  
DC Input Voltage  
– 0.5 to + 7.0  
– 0.5 to + 7.0  
CC  
V
V
in  
V
DC Output Voltage  
Input Diode Current  
Output Diode Current  
– 0.5 to V + 0.5  
V
out  
IK  
CC  
I
20  
20  
mA  
mA  
mA  
mA  
mW  
cuit. For proper operation, V and  
in  
I
OK  
V
out  
should be constrained to the  
I
DC Output Current, per Pin  
DC Supply Current, V and GND Pins  
25  
range GND v (V or V ) v V  
.
out  
CC  
in  
out  
CC  
Unused inputs must always be  
tied to an appropriate logic voltage  
I
75  
CC  
level (e.g., either GND or V ).  
P
D
Power Dissipation in Still Air,  
SOIC Packages†  
TSSOP Package†  
500  
450  
CC  
Unused outputs must be left open.  
T
stg  
Storage Temperature  
– 65 to + 150  
_C  
* Absolute maximum continuous ratings are those values beyond which damage to the device  
may occur. Exposure to these conditions or conditions beyond those indicated may  
adversely affect device reliability. Functional operation under absolutemaximumrated  
conditions is not implied.  
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C  
TSSOP Package: 6.1 mW/_C from 65_ to 125_C  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
Min  
2.0  
0
Max  
5.5  
Unit  
V
V
CC  
DC Supply Voltage  
DC Input Voltage  
DC Output Voltage  
V
in  
5.5  
V
V
out  
0
V
CC  
V
T
Operating Temperature, All Package Types  
40  
+ 85  
_C  
ns/V  
A
t , t  
r
Input Rise and Fall Time  
V
CC  
V
CC  
= 3.3V 0.3V  
=5.0V 0.5V  
0
0
100  
20  
f
http://onsemi.com  
2
MC74VHC240  
DC ELECTRICAL CHARACTERISTICS  
T
A
= 25°C  
T = 40 to 85°C  
A
V
CC  
Min  
Typ  
Max  
Min  
Max  
V
Symbol  
Parameter  
Test Conditions  
Unit  
V
IH  
Minimum HighLevel  
Input Voltage  
2.0  
3.0 to  
5.5  
1.50  
1.50  
V
V
x 0.7  
V
x 0.7  
CC  
CC  
V
Maximum LowLevel  
Input Voltage  
2.0  
3.0 to  
5.5  
0.50  
0.50  
V
V
IL  
V
x 0.3  
V
x 0.3  
CC  
CC  
V
OH  
Minimum HighLevel  
Output Voltage  
V
I
= V or V  
= 50μA  
2.0  
3.0  
4.5  
1.9  
2.9  
4.4  
2.0  
3.0  
4.5  
1.9  
2.9  
4.4  
in  
IH  
IL  
OH  
V
in  
= V or V  
IH  
IL  
I
I
= 4mA  
= 8mA  
3.0  
4.5  
2.58  
3.94  
2.48  
3.80  
OH  
OH  
V
OL  
Maximum LowLevel  
Output Voltage  
V
I
= V or V  
= 50μA  
2.0  
3.0  
4.5  
0.0  
0.0  
0.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
in  
IH  
IL  
OL  
V
in  
= V or V  
IH  
IL  
I
I
= 4mA  
= 8mA  
3.0  
4.5  
0.36  
0.36  
0.44  
0.44  
OL  
OL  
I
Maximum Input  
Leakage Current  
V
V
= 5.5V or GND  
0 to 5.5  
0.1  
1.0  
μA  
μA  
in  
in  
I
Maximum  
= V or V  
IH  
5.5  
0.25  
2.5  
OZ  
in  
IL  
ThreeState Leakage  
Current  
V
= V or GND  
out CC  
I
Maximum Quiescent  
Supply Current  
V
in  
= V or GND  
5.5  
4.0  
40.0  
μA  
CC  
CC  
http://onsemi.com  
3
MC74VHC240  
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)  
r
f
T
A
= 25°C  
T = 40 to 85°C  
A
Min  
Typ  
Max  
Min  
Max  
Symbol  
Parameter  
Test Conditions  
Unit  
t
t
t
,
Maximum Propagation Delay,  
A to YA or B to YB  
V
V
V
= 3.3 0.3V  
= 5.0 0.5V  
= 3.3 0.3V  
C = 15pF  
C = 50pF  
L
5.3  
7.8  
7.5  
11.0  
1.0  
1.0  
9.0  
12.5  
ns  
PLH  
t
CC  
CC  
CC  
L
PHL  
C = 15pF  
3.6  
5.1  
5.5  
7.5  
1.0  
1.0  
6.5  
8.5  
L
C = 50pF  
L
,
Output Enable Time  
OEA to YA or OEB to YB  
C = 15pF  
6.6  
9.1  
10.6  
14.1  
1.0  
1.0  
12.5  
16.0  
ns  
ns  
ns  
PZL  
t
L
R = 1kΩ  
C = 50pF  
L
PZH  
L
V
CC  
= 5.0 0.5V  
C = 15pF  
4.7  
6.2  
7.3  
9.3  
1.0  
1.0  
8.5  
10.5  
L
R = 1kΩ  
C = 50pF  
L
L
,
Output Disable Time  
OEA to YA or OEB to YB  
V
CC  
= 3.3 0.3V  
C = 50pF  
L
10.3  
14.0  
9.2  
1.5  
1.0  
10  
1.0  
16.0  
10.5  
1.5  
PLZ  
t
R = 1kΩ  
PHZ  
L
V
CC  
= 5.0 0.5V  
C = 50pF  
L
6.7  
1.0  
R = 1kΩ  
L
t
,
Output to Output Skew  
V
CC  
= 3.3 0.3V  
C = 50pF  
L
OSLH  
t
(Note 1.)  
OSHL  
V
CC  
= 5.0 0.5V  
C = 50pF  
L
1.0  
(Note 1.)  
C
Maximum Input Capacitance  
4
6
10  
pF  
pF  
in  
C
Maximum ThreeState Output  
Capacitance (Output in  
out  
HighImpedance State)  
Typical @ 25°C, V = 5.0V  
CC  
17  
C
Power Dissipation Capacitance (Note 2.)  
pF  
PD  
1. Parameter guaranteed by design. t = |t t  
|, t  
= |t  
t  
PHLn  
|.  
OSLH  
PLHm  
PLHn OSHL  
PHLm  
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.  
PD  
Average operating current can be obtained by the equation: I  
) = C V f + I /8 (per bit). C is used to determine the noload  
CC(OPR  
CC  
PD CC in CC PD  
2
dynamic power consumption; P = C V  
f + I V  
.
D
PD  
CC  
in  
CC  
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)  
r
f
L
CC  
T
A
= 25°C  
Typ  
Max  
Symbol  
Parameter  
Unit  
V
V
V
Quiet Output Maximum Dynamic V  
0.6  
0.9  
0.9  
3.5  
OLP  
OL  
Quiet Output Minimum Dynamic V  
0.6  
V
OLV  
OL  
V
IHD  
Minimum High Level Dynamic Input Voltage  
Maximum Low Level Dynamic Input Voltage  
V
V
ILD  
1.5  
V
http://onsemi.com  
4
MC74VHC240  
SWITCHING WAVEFORMS  
V
CC  
V
CC  
A or B  
OEA or OEB  
50%  
50%  
GND  
GND  
t
t
PLZ  
PZL  
HIGH  
t
t
PLH  
PHL  
IMPEDANCE  
50% V  
CC  
YA or YB  
YA or YB  
50% V  
CC  
YA or YB  
V
+0.3V  
OL  
t
t
PHZ  
PZH  
V
OH  
-0.3V  
50% V  
CC  
HIGH  
IMPEDANCE  
Figure 2.  
Figure 3.  
TEST CIRCUITS  
TEST POINT  
OUTPUT  
TEST POINT  
1 kΩ  
CONNECT TO V WHEN  
CC  
OUTPUT  
TESTING t AND t  
PLZ  
.
PZL  
DEVICE  
UNDER  
TEST  
DEVICE  
CONNECT TO GND WHEN  
TESTING t AND t  
UNDER  
TEST  
.
PZH  
PHZ  
C *  
L
C *  
L
*Includes all probe and jig capacitance  
*Includes all probe and jig capacitance  
Figure 4. Test Circuit  
Figure 5. Test Circuit  
INPUT  
Figure 6. Input Equivalent Circuit  
http://onsemi.com  
5
MC74VHC240  
PACKAGE DIMENSIONS  
SOIC20  
CASE 751D05  
ISSUE G  
D
A
q
NOTES:  
1. DIMENSIONS ARE IN MILLIMETERS.  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
20  
11  
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD  
PROTRUSION.  
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.  
5. DIMENSION B DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE PROTRUSION  
SHALL BE 0.13 TOTAL IN EXCESS OF B  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
1
10  
MILLIMETERS  
DIM MIN  
MAX  
2.65  
0.25  
0.49  
0.32  
12.95  
7.60  
20X B  
A
A1  
B
C
D
E
2.35  
0.10  
0.35  
0.23  
12.65  
7.40  
M
S
S
B
T
0.25  
A
A
e
1.27 BSC  
H
h
10.05  
0.25  
0.50  
0
10.55  
0.75  
0.90  
7
SEATING  
PLANE  
L
18X e  
q
_
_
A1  
C
T
http://onsemi.com  
6
MC74VHC240  
PACKAGE DIMENSIONS  
TSSOP20  
CASE 948E02  
ISSUE C  
NOTES:  
20X K REF  
1. DIMENSIONING AND TOLERANCING PER  
K
K1  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION:  
MILLIMETER.  
M
S
S
V
0.10 (0.004)  
T
U
S
T U  
0.15 (0.006)  
3. DIMENSION A DOES NOT INCLUDE  
MOLD FLASH, PROTRUSIONS OR GATE  
BURRS. MOLD FLASH OR GATE BURRS  
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION  
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08  
(0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
J J1  
20  
11  
2X L/2  
B
SECTION NN  
L
U−  
PIN 1  
0.25 (0.010)  
IDENT  
N
1
10  
M
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE W.  
S
0.15 (0.006)  
T U  
N
A
V−  
MILLIMETERS  
INCHES  
MIN  
F
DIM MIN  
MAX  
6.60  
4.50  
1.20  
0.15  
0.75  
MAX  
0.260  
0.177  
0.047  
0.006  
0.030  
A
B
6.40  
4.30  
---  
0.252  
0.169  
---  
DETAIL E  
C
D
0.05  
0.50  
0.002  
0.020  
W−  
C
F
G
H
0.65 BSC  
0.026 BSC  
0.27  
0.09  
0.09  
0.19  
0.19  
0.37  
0.20  
0.16  
0.30  
0.25  
0.011  
0.004  
0.004  
0.007  
0.007  
0.015  
0.008  
0.006  
0.012  
0.010  
G
D
J
H
J1  
K
DETAIL E  
0.100 (0.004)  
TSEATING  
K1  
L
6.40 BSC  
0.252 BSC  
0
SOLDERING FOOTPRINT  
PLANE  
M
0
8
8
_
_
_
_
7.06  
1
0.65  
PITCH  
01.36X6  
16X  
1.26  
DIMENSIONS: MILLIMETERS  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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Europe, Middle East and Africa Technical Support:  
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MC74VHC240/D  

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