MC74VHC259_14 [ONSEMI]
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter;
| 型号： | MC74VHC259_14 |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter |
| 文件： | 总8页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74VHC259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology. It achieves high speed operation similar to
equivalent Bipolar Schottky TTL devices while maintaining CMOS low
power dissipation.
The VHC259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in the
mode selection table.. In the addressable latch mode, the data on Data In
is written into the addressed latch. The addressed latch follows the data
input with all non−addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state and are
unaffected by the Data or Address inputs. In the one−of−eight decoding
or demultiplexing mode, the addressed output follows the state of Data In
with all other outputs in the LOW state. In the Reset mode, all outputs are
LOW and unaffected by the address and data inputs. When operating the
VHC259 as an addressable latch, changing more than one bit of the
address could impose a transient wrong address. Therefore, this should
only be done while in the memory mode.
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MARKING DIAGRAMS
16
1
9
8
VHC259G
AWLYYWW
SOIC−16
D SUFFIX
CASE 751B
16
9
VHC
259
TSSOP−16
DT SUFFIX
CASE 948F
ALYWG
G
1
8
The MC74VHC259 input structure provides protection when voltages
up to 7 V are applied, regardless of the supply voltage. This allows the
MC74VHC259 to be used to interface 5 V circuits to 3 V circuits.
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
• High Speed: t = 7.6 ns (Typ) at V = 5 V
W, WW = Work Week
G or G = Pb−Free Package
PD
CC
• Low Power Dissipation: I = 2 μA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC OL
CC
ORDERING INFORMATION
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
Device
Package
Shipping
48 Units/Rail
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
MC74VHC259DG
MC74VHC259DR2G
MC74VHC259DTG
SOIC−16
SOIC−16 2500 Units/Reel
TSSOP−16 96 Units/Rail
• ESD Performance: HBM > 2000 V
• These Devices are Pb−Free and are RoHS Compliant
MC74VHC259DTR2G TSSOP−16 2500 Units/Reel
A0
A1
1
2
16
15
V
CC
RESET
3
4
14
13
A2
Q0
Q1
ENABLE
DATA IN
Q7
5
6
7
8
12
11
10
9
Q2
Q3
Q6
Q5
Q4
GND
Figure 1. Pin Assignment
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
September, 2014 − Rev. 5
MC74VHC259/D
MC74VHC259
4
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
A0
A1
A2
ADDRESS
INPUTS
6
7
NONINVERTING
OUTPUTS
9
10
11
12
13
DATA IN
PIN 16 = V
CC
PIN 8 = GND
15
14
RESET
ENABLE
Figure 2. Logic Diagram
BIN/OCT
DMUX
0
0
1
7
1
2
3
1
2
3
4
5
6
7
8
4
5
6
7
8
A0
A1
A2
A0
A1
A2
1
2
4
0
Q0
Q1
Q2
Q3
Q4
0
2
Q0
Q1
Q2
Q3
Q4
G
1
2
3
4
5
2
3
4
10
11
12
13
14
15
10
11
12
13
14
15
ID
EN
R
ID
Q5
Q6
Q7
5
Q5
Q6
Q7
EN
R
6
7
6
7
Figure 3. IEC Logic Symbol
LATCH SELECTION TABLE
MODE SELECTION TABLE
Address Inputs
Enable Reset
Mode
Latch
Addressed
A
C
B
L
H
Addressable Latch
H
L
H
L
Memory
L
L
L
L
L
Q0
Q1
8−Line Demultiplexer
H
H
L
Reset
L
L
H
H
L
Q2
Q3
H
H
H
H
H
L
L
L
H
L
Q4
Q5
Q6
Q7
H
H
H
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2
MC74VHC259
13
4
5
D
D
ꢀDATA INPUT
Q0
Q1
6
D
Q2
7
D
D
D
Q3
Q4
Q5
ꢀA0
ꢀ3 TO 8
DECODER
ADDRESS
INPUTS
ꢀA1
ꢀA2
9
10
14
ꢀENABLE
11
D
Q6
12
D
Q7
15
ꢀRESET
Figure 4. Expanded Logic Diagram
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3
MC74VHC259
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
CC
IN
V
DC Output Voltage
−0.5 to V +0.5
V
OUT
CC
I
I
I
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
Output Diode Current
DC Output Current, per Pin
OK
OUT
CC
DC Supply Current, V and GND Pins
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
V
Human Body Model (Note 1.)
Machine Model (Note 2.)
>2000
>200
V
ESD
Charged Device Model (Note 3.)
>2000
I
Latch−Up Performance
Above V and Below GND at 125°C (Note 4.)
$300
143
164
mA
LATCH−UP
CC
q
Thermal Resistance, Junction to Ambient
SOIC Package
TSSOP
°C/W
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
T
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
V
0
V
CC
V
OUT
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−55
0
125
20
°C
ns/V
A
t , t
V
CC
V
CC
= 3.3 V + 0.3 V
= 5.0 V + 0.5 V
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 5. Failure Rate vs. Time Junction Temperature
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4
MC74VHC259
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
−55°C ≤ T ≤ 125°C
A
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Unit
V
V
V
Minimum High−Level
Input Voltage
2.0
3.0to 5.5
1.5
1.5
V
IH
V
0.7
V
0.7
CCX
CCX
Maximum Low−Level
Input Voltage
2.0
3.0to 5.5
0.5
0.5
V
V
IL
V
0.3
V
0.3
CCX
CCX
V
I
= V or V
= −50 μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
Maximum High−Level
Output Voltage
IN
IH
IL
IL
IL
IL
OH
OH
V
IN
= V or V
V
V
V
IH
I
OL
= 4 mA
= 8 mA
3.0
4.5
2.58
3.94
2.48
3.8
I
OL
V
IN
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
Maximum Low−Level
Output Voltage
IH
I
OL
= 50 μA
V
IN
= V or V
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
I
OL
I
Input Leakage Current
V
= 5.5 V or GND
0 to 5.5
5.5
0.1
4.0
1.0
μA
μA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
40.0
CC
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
−55°C ≤ T
≤
A
125°C
T
A
= 25°C
T ≤ 85°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Maximum
Propagation Delay,
Data to Output
Test Conditions
Unit
t
t
,
ns
V
V
V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
C = 15pF
C = 50pF
L
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PLH
PHL
CC
CC
CC
L
C = 15pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
(Figures 6 and 11)
C = 50pF
L
t
t
,
Maximum
ns
C = 15pF
L
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PLH
PHL
Propagation Delay,
Address Select to
Output
C = 50pF
L
V
CC
= 5.0 0.5V
C = 15pF
L
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
C = 50pF
L
(Figures 7 and 11)
t
t
,
Maximum
ns
ns
V
CC
V
CC
V
CC
V
CC
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
C = 15pF
C = 50pF
L
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PLH
PHL
L
Propagation Delay,
Enable to Output
(Figures 8 and 11)
C = 15pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
C = 50pF
L
t
Maximum
C = 15pF
6.0
8.5
8.5
12.5
1.0
1.0
11.5
14.5
1.0
1.0
11.5
14.5
PHL
L
Propagation Delay,
Reset to Output
(Figures 9 and 11)
C = 50pF
L
C = 15pF
4.9
7.0
8.0
10.0
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
C = 50pF
L
C
C
Maximum Input
Capacitance
6
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0V
CC
30
Power Dissipation Capacitance (Note 1)
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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5
MC74VHC259
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= ≤ 85°C
T = ≤ 125°C
A
Min Typ Max Min Max
Min
5.5
5.5
4.5
3.0
2.0
2.0
Max
Symbol
Parameter
Test Conditions
Unit
t
Minimum Pulse Width, Reset or Enable
(Figure 10)
ns
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
5.0
5.0
4.5
3.0
2.0
2.0
5.5
5.5
4.5
3.0
2.0
2.0
w
su
h
t
t
Minimum Setup Time, Address or Data to Enable
(Figure 10)
ns
ns
ns
Minimum Hold Time, Enable to Address or Data
(Figure 8 or 9)
t t
Maximum Input, Rise and Fall Times
(Figure 6)
400
200
300
100
300
100
r,
f
V
CC
DATA IN
GND
t
r
t
f
V
CC
ADDRESS
SELECT
V
CC
50%
50%
50%
GND
DATA IN
GND
t
t
PLH
PHL
V
CC
50%
GND
t
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 6. Switching Waveform
Figure 7. Switching Waveform
V
CC
V
CC
GND
DATA IN
ENABLE
DATA IN
RESET
GND
t
t
w
w
t
w
V
CC
V
CC
50%
50%
50%
50%
GND
GND
t
t
PHL
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 8. Switching Waveform
Figure 9. Switching Waveform
DATA IN
OR
TEST POINT
OUTPUT
V
CC
50%
ADDRESS
SELECT
GND
t
h(H)
t
DEVICE
UNDER
TEST
h(H)
t
su
t
su
C *
L
ENABLE
V
CC
50%
GND
*Includes all probe and jig capacitance
Figure 10. Switching Waveform
Figure 11. Test Circuit
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6
MC74VHC259
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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7
MC74VHC259
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X KREF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
M
S
S
0.10 (0.004)
T
U
V
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
−V−
A
B
C
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
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