MC74VHC374DTR2 [ONSEMI]
AHC/VHC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, TSSOP-20;
| 型号： | MC74VHC374DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | AHC/VHC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, TSSOP-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总9页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC374
Octal D-Type Flip-Flop
with 3-State Output
The MC74VHC374 is an advanced high speed CMOS octal
flip−flip with 3−state output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
This 8−bit D−type flip−flop is controlled by a clock input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
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MARKING DIAGRAMS
20
SOIC−20
DW SUFFIX
CASE 751D
VHC374
AWLYYWWG
20
1
1
20
Features
VHC
374
TSSOP−20
DT SUFFIX
CASE 948E
• High Speed: f
= 185 MHz (Typ) at V = 5 V
CC
max
20
ALYWG
• Low Power Dissipation: I = 4 μA (Max) at T = 25°C
CC
A
1
G
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
1
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
20
SOEIAJ−20
M SUFFIX
CASE 967
VHC374
AWLYWWG
• Designed for 2 V to 5.5 V Operating Range
20
• Low Noise: V
= 0.9 V (Max)
OLP
1
1
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
VHC374 = Specific Device Code
A
WL, L
Y
WW, W
G or G
= Assembly Location
= Wafer Lot
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 266 FETs or 66.5 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
†
Device
Package
Shipping
MC74VHC374DWR2G SOIC−20 1000 Units/Reel
MC74VHC374DTR2G TSSOP−20 2500 Units/T&R
MC74VHC374MELG SOEIAJ−20 2000 Units/Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 6
MC74VHC374/D
MC74VHC374
3
2
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
20
V
CC
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
4
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
6
7
8
9
DATA
NONINVERTING
OUTPUTS
INPUTS
13
12
15
16
19
14
17
18
D5
D6
D7
11
1
CP
OE
GND 10
11
CP
Figure 2. PIN ASSIGNMENT
Figure 1. LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
CP
OUTPUT
Q
OE
D
L
L
L
H
L
X
X
H
L
No Change
Z
L, H,
X
H
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2
MC74VHC374
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
75
CC
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
stg
Storage Temperature
– 65 to + 150
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolute−maximum−rated
conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature
Input Rise and Fall Time
− 40
+ 85
_C
ns/V
A
t , t
r
V
CC
V
CC
= 3.3V
= 5.0V
0
0
100
20
f
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
1.50
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to
5.5
1.50
V
V
x 0.7
V
x 0.7
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0 to
5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
OH
Minimum High−Level
Output Voltage
V
I
= V or V
= − 50μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
in
IH
IL
OH
V
in
= V or V
IH
IL
I
I
= − 4mA
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
OL
Maximum Low−Level
Output Voltage
V
I
= V or V
= 50μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
in
IH
IL
OL
V
in
= V or V
IH
IL
I
I
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
OL
OL
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3
MC74VHC374
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
CC
Min
Typ
Max
Min
Max
V
Symbol
Parameter
Test Conditions
Unit
I
Maximum Input
Leakage Current
V
V
= 5.5V or GND
0 to 5.5
0.1
1.0
μA
in
in
I
Maximum
Three−State Leakage
Current
= V or V
IH
5.5
5.5
0.25
4.0
2.5
μA
μA
OZ
in
IL
V
= V or GND
out CC
I
Maximum Quiescent
Supply Current
V
in
= V or GND
40.0
CC
CC
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= − 40 to 85°C
Min
Typ
Max
Min
70
Max
Symbol
Parameter
Test Conditions
Unit
f
Maximum Clock Frequency
(50% Duty Cycle)
V
V
V
V
V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
C = 15pF
C = 50pF
L
80
55
130
85
ns
max
CC
CC
CC
CC
CC
L
50
C = 15pF
130
85
185
120
110
75
L
C = 50pF
L
t
t
t
,
Maximum Propagation Delay,
CP to Q
C = 15pF
8.1
10.6
12.7
16.2
1.0
1.0
15.0
18.5
ns
ns
ns
PLH
t
L
C = 50pF
L
PHL
C = 15pF
5.4
6.9
8.1
10.1
1.0
1.0
9.5
11.5
L
C = 50pF
L
,
Output Enable Time,
OE to Q
C = 15pF
L
7.1
9.6
11.0
14.5
1.0
1.0
13.0
16.5
PZL
t
R = 1kΩ
C = 50pF
L
PZH
L
V
CC
= 5.0 0.5V
C = 15pF
L
5.1
6.6
7.6
9.6
1.0
1.0
9.0
11.0
R = 1kΩ
C = 50pF
L
L
,
Output Disable Time,
OE to Q
V
CC
= 3.3 0.3V
C = 50pF
L
10.2
14.0
8.8
1.5
1.0
10
1.0
16.0
10.0
1.5
PLZ
t
R = 1kΩ
PHZ
L
V
CC
= 5.0 0.5V
C = 50pF
L
6.1
1.0
R = 1kΩ
L
t
,
Output to Output Skew
V
CC
= 3.3 0.3V
C = 50pF
L
ns
ns
OSLH
t
(Note 1)
OSHL
V
CC
= 5.0 0.5V
C = 50pF
L
1.0
(Note 1)
C
Maximum Input Capacitance
4
6
10
pF
pF
in
C
Maximum Three−State Output
Capacitance (Output in
out
High−Impedance State)
Typical @ 25°C, V = 5.0V
CC
32
C
Power Dissipation Capacitance (Note 2)
pF
PD
1. Parameter guaranteed by design. t = |t − t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /8 (per flip−flop). C is used to determine the
CC
CC(OPR
PD CC in CC PD
2
no−load dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
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4
MC74VHC374
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Parameter
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.6
0.9
− 0.9
3.5
OLP
OL
Quiet Output Minimum Dynamic V
− 0.6
V
OLV
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
1.5
V
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
T
A
= − 40
to 85°C
T
A
= 25°C
Typ
Limit
Limit
Symbol
Parameter
Minimum Pulse Width, CP
Test Conditions
Unit
t
w
V
V
= 3.3 0.3 V
= 5.0 0.5 V
5.0
5.0
5.5
5.0
ns
CC
CC
t
Minimum Setup Time, D to CP
Minimum Hold Time, D to CP
Maximum Input Rise and Fall Times
V
V
= 3.3 0.3 V
= 5.0 0.5 V
4.5
3.0
4.5
3.0
ns
ns
ns
su
CC
CC
t
V
CC
V
CC
= 3.3 0.3 V
= 5.0 0.5 V
2.0
2.0
2.0
2.0
h
t , t
r
V
CC
V
CC
= 3.3 0.3 V
= 5.0 0.5 V
f
SWITCHING WAVEFORMS
V
CC
V
CC
OE
50%
50%
GND
CP
GND
t
PLZ
t
PZL
HIGH
t
W
IMPEDANCE
50% V
1/f
Q
Q
CC
max
V
V
+0.3V
OL
t
t
PHL
PLH
t
t
PHZ
PZH
Q
-0.3V
50% V
OH
CC
50% V
CC
HIGH
IMPEDANCE
Figure 3.
Figure 4.
VALID
V
CC
50%
D
GND
t
h
t
su
V
CC
CP
50%
GND
Figure 5.
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5
MC74VHC374
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
CC
OUTPUT
TESTING t AND t
PLZ
.
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
C
C
C
C
C
C
C
C
11
1
CP
OE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
Figure 8. EXPANDED LOGIC DIAGRAM
INPUT
Figure 9. INPUT EQUIVALENT CIRCUIT
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6
MC74VHC374
PACKAGE DIMENSIONS
SOIC−20
DW SUFFIX
CASE 751D−05
ISSUE G
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
0.25
T A
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
C
T
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7
MC74VHC374
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
K
K1
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
M
S
S
V
0.10 (0.004)
T
U
S
T U
0.15 (0.006)
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
J J1
20
11
2X L/2
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
0.15 (0.006)
T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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8
MC74VHC374
PACKAGE DIMENSIONS
SOEIAJ−20
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.25
12.80
5.45
MAX
0.081
0.008
0.020
0.010
0.504
0.215
c
A
---
0.05
0.35
0.15
12.35
5.10
---
0.002
0.014
0.006
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
_
0.035
0.032
0
_
_
_
0.70
---
0.90
0.81
0.028
---
1
Z
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MC74VHC374/D
相关型号：
MC74VHC374MR2
Bus Driver, AHC/VHC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20
MOTOROLA
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