MC74VHC541DTG [ONSEMI]
Octal Bus Buffer; 八路总线缓冲器
| 型号： | MC74VHC541DTG |
| 厂家： | 
ONSEMI |
| 描述： | Octal Bus Buffer |
| 文件： | 总6页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC541
Octal Bus Buffer
The MC74VHC541 is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHC541 is a noninverting type. When either OE1 or
OE2 are high, the terminal outputs are in the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
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SOIC−20WB
SUFFIX DW
CASE 751D
20
20
1
Features
• High Speed: t = 3.7ns (Typ) at V = 5.0 V
PD
CC
TSSOP−20
SUFFIX DT
CASE 948E
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
1
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
SOEIAJ−20
SUFFIX M
CASE 967
• Designed for 2.0 V to 5.5 V Operating Range
20
• Low Noise: V
= 1.2 V (Max)
OLP
1
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
PIN ASSIGNMENT
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
• Pb−Free Packages are Available*
OE1
1
20
V
CC
A1
A2
A3
2
3
4
19
18
17
OE2
Y1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y2
A4
A5
A6
A7
A8
5
6
7
8
9
16
15
14
13
12
Y3
Y4
Y5
Y6
Y7
DATA
INPUTS
NONINVERTING
OUTPUTS
GND 10
11 Y8
FUNCTION TABLE
Inputs
Output Y
OE1 OE2
A
A8
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
1
OE1
OUTPUT
ENABLES
19
OE2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Figure 1. Logic Diagram
dimensions section on page 4 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
April, 2006 − Rev. 5
MC74VHC541/D
MC74VHC541
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Input Diode Current
– 0.5 to + 7.0
– 0.5 to + 7.0
CC
V
V
in
V
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
Output Diode Current
OK
V
out
should be constrained to the
I
DC Output Current, per Pin
25
out
range GND v (V or V ) v V
.
CC
in
out
Unused inputs must always be
tied to an appropriate logic voltage
I
DC Supply Current, V and GND Pins
50
CC
CC
P
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
D
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
V
in
5.5
V
V
out
0
V
V
CC
T
Operating Temperature, All Package Types
− 40
+ 85
_C
ns/V
A
t , t
r
Input Rise and Fall Time
= 5.0V 0.5V
V = 3.3V 0.3V
CC
0
0
100
20
f
V
CC
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T = − 40 to 85°C
A
V
V
CC
Min
1.50
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
V
Minimum High−Level Input
Voltage
2.0
1.50
V
IH
3.0 to 5.5
V
CC
x 0.7
V
CC
x 0.7
V
Maximum Low−Level Input
Voltage
2.0
3.0 to 5.5
0.50
0.50
V
V
IL
V
x 0.3
V
x 0.3
CC
CC
V
Minimum High−Level Output
Voltage
V
= V or V
= − 50mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
OH
in
IH
IL
I
OH
V
in
= V or V
IH
IL
I
I
= − 4mA
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
OH
OH
V
Maximum Low−Level Output
Voltage
V
= V or V
= 50mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IH
IL
I
OL
V
in
= V or V
IH
IL
I
OL
I
OL
= 4mA
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
I
Maximum Input Leakage
Current
V
V
= 5.5V or GND
0 to 5.5
0.1
0.25
4.0
1.0
mA
mA
mA
in
in
I
Maximum 3−State Leakage
Current
= V or V
IL IH
5.5
2.5
OZ
in
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current
V
in
= V or GND
5.5
40.0
CC
CC
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2
MC74VHC541
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = − 40 to 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation Delay,
A to Y
V
V
V
= 3.3 0.3V
= 5.0 0.5V
= 3.3 0.3V
C = 15pF
C = 50pF
L
5.0
7.5
7.0
10.5
1.0
1.0
8.5
12.0
ns
PLH
t
CC
CC
CC
L
PHL
C = 15pF
3.5
5.0
5.0
7.0
1.0
1.0
6.0
8.0
L
C = 50pF
L
,
Output Enable TIme,
OE to Y
C = 15pF
6.8
9.3
10.5
14.0
1.0
1.0
12.5
16.0
ns
ns
PZL
t
L
R = 1kW
C = 50pF
L
PZH
L
V
= 5.0 0.5V
C = 15pF
4.7
6.2
7.2
9.2
1.0
1.0
8.5
10.5
CC
L
R = 1kW
C = 50pF
L
L
,
Output Disable Time,
OE to Y
V
= 3.3 0.3V
C = 50pF
L
11.2
15.4
8.8
1.5
1.0
10
1.0
17.5
10.0
1.5
PLZ
CC
t
R = 1kW
PHZ
L
V
= 5.0 0.5V
C = 50pF
L
6.0
1.0
CC
R = 1kW
L
t
,
Output to Output Skew
V
= 3.3 0.3V
C = 50pF
L
ns
ns
OSLH
CC
t
(Note 1)
OSHL
V
= 5.0 0.5V
C = 50pF
L
1.0
CC
(Note 1)
C
in
Maximum Input Capacitance
4
6
10
pF
pF
C
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
out
Typical @ 25°C, V = 5.0V
CC
18
C
Power Dissipation Capacitance (Note 2)
= |t
pF
PD
1. Parameter guaranteed by design. t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I /8 (per bit). C is used to determine the no−load
CC(OPR
PD CC in CC PD
2
dynamic power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
0.9
Max
Symbol
Parameter
Unit
V
V
Quiet Output Maximum Dynamic V
1.2
− 1.2
3.5
OLP
OLV
OL
V
Quiet Output Minimum Dynamic V
− 0.9
V
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
IHD
V
1.5
ILD
SWITCHING WAVEFORMS
V
CC
OE1 or OE2
50%
50%
V
CC
GND
A
50%
t
t
PLZ
PZL
HIGH
IMPEDANCE
GND
t
t
PHL
PLH
50% V
t
Y
Y
CC
V
V
+0.3V
−0.3V
OL
t
50% V
PZH
PHZ
CC
Y
OH
50% V
CC
HIGH
IMPEDANCE
Figure 2.
Figure 3.
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3
MC74VHC541
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V WHEN
.
PZL
CC
TESTING t AND t
1kW
OUTPUT
OUTPUT
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
INPUT
Figure 6. Input Equivalent Circuit
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHC541DWR2
MC74VHC541DWR2G
SOIC−20WB
1000 / Tape & Reel
1000 / Tape & Reel
SOIC−20WB
(Pb−Free)
MC74VHC541DT
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
SOEIAJ−20
75 Units / Rail
75 Units / Rail
MC74VHC541DTG
MC74VHC541DTR2
MC74VHC541DTR2G
MC74VHC541MEL
MC74VHC541MELG
2500 / Tape & Reel
2500 / Tape & Reel
2000 / Tape & Reel
2000 / Tape & Reel
SOEIAJ−20
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MARKING DIAGRAMS
SOIC−20WB
TSSOP−20
SOEIAJ−20
20
1
20
1
20
1
74VHC541
AWLYWWG
A
= Assembly Location
VHC
541
VHC541
AWLYYWWG
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ALYWG
G
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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4
MC74VHC541
PACKAGE DIMENSIONS
SOIC−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
B
MILLIMETERS
1
10
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE B
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER
SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
0.25 (0.010)
N
S
0.15 (0.006) T U
6. TERMINAL NUMBERS ARE SHOWN
FOR REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
−W−
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
G
J1
K
D
H
DETAIL E
K1
L
0.100 (0.004)
6.40 BSC
0.252 BSC
0
−T− SEATING
PLANE
M
0
8
8
_
_
_
_
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5
MC74VHC541
PACKAGE DIMENSIONS
SOEIAJ−20
M SUFFIX
CASE 967−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
L
20
11
E
Q
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
1
H
E
E
_
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
L
1
10
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
DIM MIN
MAX
A
−−−
0.05
2.05
A
1
A
b
1
0.20 0.002
0.50 0.014
0.25 0.006
12.80 0.486
5.45 0.201
0.008
0.020
0.010
0.504
0.215
b
c
0.35
0.15
M
0.10 (0.004)
0.13 (0.005)
D
E
e
12.35
5.10
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
0.035
0
_
_
_
_
0.70
−−−
1
Z
0.81
−−− 0.032
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC541/D
相关型号：
MC74VHC541MR2
Bus Driver, AHC/VHC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, EIAJ, PLASTIC, SOIC-20
MOTOROLA
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