MC74VHC595_15 [ONSEMI]
8-Bit Shift Register with Output Storage Register;
| 型号： | MC74VHC595_15 |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Shift Register with Output Storage Register |
| 文件： | 总11页 (文件大小：117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC595
8-Bit Shift Register with
Output Storage Register
(3-State)
The MC74VHC595 is an advanced high speed 8−bit shift register
with an output storage register fabricated with silicon gate CMOS
technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHC595 contains an 8−bit static shift register which
feeds an 8−bit storage register.
www.onsemi.com
MARKING DIAGRAMS
16
9
VHC595G
AWLYWW
Shift operation is accomplished on the positive going transition of
the Shift Clock input (SCK). The output register is loaded with the
contents of the shift register on the positive going transition of the
Register Clock input (RCK). Since the RCK and SCK signals are
independent, parallel outputs can be held stable during the shift
operation. And, since the parallel outputs are 3−state, the VHC595 can
be directly connected to an 8−bit bus. This register can be used in
serial−to−parallel conversion, data receivers, etc.
SOIC−16
D SUFFIX
CASE 751B
1
8
16
9
VHC
595
TSSOP−16
DT SUFFIX
CASE 948F
ALYWG
G
8
1
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
W, WW = Work Week
G or G = Pb−Free Package
Features
(Note: Microdot may be in either location)
• High Speed: f
= 185 MHz (Typ) at V = 5 V
CC
max
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
PIN ASSIGNMENT
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
QB
QC
1
2
16 VCC
15 QA
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
QD
QE
3
4
5
6
7
8
14 SI
• Low Noise: V
= 1.0 V (Max)
OLP
13 OE
12 RCK
11 SCK
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
QF
QG
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
QH
10
SCLR
SQH
GND
9
• These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
†
Device
Package
Shipping
MC74VHC595DR2G
SOIC−16
(Pb−Free)
2500 Tape &
Reel
MC74VHC595DTR2G, TSSOP−16 2500 Tape &
NLV74VHC595DTR2G
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
February, 2015 − Rev. 6
MC74VHC595/D
MC74VHC595
LOGIC DIAGRAM
SERIAL
DATA
14
15
1
SI
QA
QB
INPUT
2
3
4
5
6
7
QC
QD
QE
QF
QG
QH
PARALLEL
DATA
SHIFT
REGISTER
STORAGE
REGISTER
OUTPUTS
11
10
12
13
SCK
SERIAL
DATA
9
SQH
SCLR
RCK
OE
OUTPUT
IEC LOGIC SYMBOL
13
12
OE
EN3
C2
RSK
SRG8
R
10
11
SCLR
SCK
C/1
14
15
SI
1D
2D
3
QA
1
QB
QC
2
3
4
QD
QE
5
6
7
9
QF
QG
QH
2D
3
SQH
www.onsemi.com
2
MC74VHC595
EXPANDED LOGIC DIAGRAM
13
12
14
OE
RCK
15
D
Q
Q
Q
Q
Q
Q
Q
Q
D
D
D
D
D
D
D
D
Q
Q
Q
Q
Q
Q
Q
Q
ꢀSI
QA
QB
QC
QD
QE
QF
QG
QH
SRA
SRB
SRC
SRD
SRE
SRF
SRG
SRH
STRA
STRB
STRC
STRD
STRE
STRF
STRG
STRH
R
D
1
R
D
2
R
D
3
PARALLEL
DATA
R
D
OUTPUTS
4
R
D
5
R
D
6
R
D
7
11
10
ꢀSCK
SCLR
R
9
SQH
www.onsemi.com
3
MC74VHC595
FUNCTION TABLE
Inputs
Resulting Function
Serial
Input
(SI)
Shift
Clock
(SCK)
Reg
Clock
(RCK)
Output
Enable
(OE)
Shift
Register
Contents
Storage
Register
Contents
Serial
Output
(SQH)
Parallel
Outputs
(QA − QH)
Reset
(SCLR)
Operation
Clear shift register
L
X
D
X
L, H, ↓
L, H, ↓
L
L
L
U
U
L
U
U
Shift data into shift
register
H
↑
D→SR ;
SR →SR
SR →SR
A
G
H
N
N+1
Registers remains
unchanged
H
H
X
X
L, H, ↓
L, H, ↓
X
L
L
U
U
**
U
*
**
Transfer shift register
contents to storage
register
↑
SR ³STR
SR
N
N
N
Storage register remains
unchanged
X
X
X
L, H, ↓
L
*
U
*
U
Enable parallel outputs
X
X
X
X
X
X
X
X
L
*
*
**
**
*
*
Enabled
Z
Force outputs into high
impedance state
H
SR = shift register contents
STR = storage register contents U = remains unchanged
D = data (L, H) logic level
↓ = High−to−Low
↑ = Low−to−High
* = depends on Reset and Shift Clock inputs
** = depends on Register Clock input
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
CC
DC Supply Voltage
DC Input Voltage
– 0.5 to + 7.0
– 0.5 to + 7.0
V
V
V
in
V
DC Output Voltage
Input Diode Current
Output Diode Current
– 0.5 to V + 0.5
V
out
IK
CC
I
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
I
OK
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Output Current, per Pin
DC Supply Current, V and GND Pins
25
in
out
CC
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
I
50
CC
level (e.g., either GND or V ).
P
D
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
500
450
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
stg
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
5.5
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
in
5.5
V
V
out
0
V
CC
V
T
Operating Temperature, All Package Types
− 55 + 125
_C
ns/V
A
t , t
r
Input Rise and Fall Time
V
CC
V
CC
= 3.3V 0.3V
=5.0V 0.5V
0
0
100
20
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
www.onsemi.com
4
MC74VHC595
The q of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
JA
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 1. Failure Rate vs. Time
Junction Temperature
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
= ≤ 85°C
T = ≤ 125°C
A
V
CC
Min
Typ
Max
Min
Max
Min
Max
(V)
Symbol
Parameter
Test Conditions
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
4.5
5.5
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
1.5
2.1
3.15
3.85
V
V
Maximum Low−Level
Input Voltage
2.0
3.0
4.5
5.5
0.59
0.9
1.35
1.65
0.59
0.9
1.35
1.65
0.59
0.9
1.35
1.65
V
V
IL
V
OH
Minimum High−Level
Output Voltage
V
= V or V
= − 50 μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
IN
IH
IL
IL
IL
IL
I
OH
V
IN
= V or V
IH IL
V
= V or V
IN
OH
OH
IH
I
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
OL
Maximum Low−Level
Output Voltage
V
V
I
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
IN
IH
= 50 μA
OL
V
IN
= V or V
IH IL
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
0.1
1.0
40.0
2.5
1.0
40.0
2.5
μA
μA
μA
IN
IN
I
Maximum Quiescent
Supply Current
V
IN
= V or GND
5.5
4.0
CC
CC
I
Three−State Output
Off−State Current
V
V
= V or V
IL
5.5
0.25
OZ
IN
IH
= V or
OUT
CC
GND
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
5
MC74VHC595
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T
A
= ≤ 85°C
T = ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
f
Maximum Clock
Frequency (50%
Duty Cycle)
MHz
V
V
V
= 3.3 0.3 V
80
150
70
70
max
CC
CC
CC
= 5.0 0.5 V
135
185
115
115
t
,
Propagation
Delay, SCK to
SQH
ns
ns
ns
ns
ns
= 3.3 0.3 V
= 5.0 0.5 V
= 3.3 0.3 V
= 5.0 0.5 V
= 3.3 0.3 V
= 5.0 0.5 V
= 3.3 0.3 V
C = 15pF
C = 50pF
L
8.8
11.3
13.0
16.5
1.0
1.0
15.0
18.5
1.0
1.0
15.0
18.5
PLH
L
t
PHL
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
C = 15pF
6.2
7.7
8.2
10.2
1.0
1.0
9.4
11.4
1.0
1.0
9.4
11.4
L
C = 50pF
L
t
Propagation
Delay,
CPLR to SQH
C = 15pF
8.4
10.9
12.8
16.3
1.0
1.0
13.7
17.2
1.0
1.0
13.7
17.2
PHL
L
C = 50pF
L
C = 15pF
5.9
7.4
8.0
10.0
1.0
1.0
9.1
11.1
1.0
1.0
9.1
11.1
L
C = 50pF
L
t
t
t
,
Propagation
Delay, RCK to
QA−QH
C = 15pF
7.7
10.2
11.9
15.4
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
PLH
L
t
C = 50pF
L
PHL
C = 15pF
5.4
6.9
7..4
9.4
1.0
1.0
8.5
10.5
1.0
1.0
8.5
10.5
L
C = 50pF
L
,
Output Enable
Time,
OE to QA−QH
C = 15pF
7.5
9.0
11.5
15.0
1.0
1.0
13.5
17.0
1.0
1.0
13.5
17.0
PZL
L
t
R = 1 kW
C = 50pF
L
PZH
L
V
CC
= 5.0 0.5 V
C = 15pF
4.8
8.3
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
10.0
12.0
L
R = 1 kW
C = 50pF
L
L
,
Output Disable
Time,
OE to QA−QH
V
CC
= 3.3 0.3 V
C = 50pF
L
12.1
15.7
10.3
10
1.0
16.2
1.0
16.2
PLZ
t
R = 1 kW
PHZ
L
V
CC
= 5.0 0.5 V
C = 50pF
L
7.6
1.0
11.0
1.0
11.0
R = 1 kW
L
C
Input Capacitance
4
6
10
10
10
10
pF
pF
IN
C
Three−State
Output
OUT
Capacitance
(Output in
High−Impedance
State), QA−QH
Typical @ 25°C, V = 5.0V
CC
87
C
Power Dissipation Capacitance (Note 1)
pF
PD
1. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
0.8
Max
1.0
Symbol
Characteristic
Quiet Output Maximum Dynamic V
Unit
V
V
OLP
OL
V
Quiet Output Minimum Dynamic V
− 0.8
− 1.0
3.5
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
1.5
V
ILD
www.onsemi.com
6
MC74VHC595
TIMING REQUIREMENTS (Input t = t = 3.0ns)
r
f
T
A
= − 40 to
T
A
= − 55 to
85°C
125°C
T
A
= 25_C
V
V
CC
Typ
Limit
Limit
Limit
Symbol
Parameter
Unit
t
su
Setup Time, SI to SCK
3.3
5.0
3.5
3.0
3.5
3.0
3.5
3.0
ns
t
Setup Time, SCK to RCK
Setup Time, SCLR to RCK
Hold Time, SI to SCK
3.3
5.0
8.0
5.0
8.5
5.0
8.5
5.0
ns
ns
ns
ns
ns
ns
ns
su(H)
t
3.3
5.0
8.0
5.0
9.0
5.0
9.0
5.0
su(L)
t
h
3.3
5.0
1.5
2.0
1.5
2.0
1.5
2.0
t
Hold Time, SCLR to RCK
3.3
5.0
0
0
0
0
1.0
1.0
h(L)
t
Recovery Time, SCLR to SCK
Pulse Width, SCK or RCK
Pulse Width, SCLR
3.3
5.0
3.0
2.5
3.0
2.5
3.0
2.5
rec
t
w
3.3
5.0
5.0
5.0
5.0
5.0
5.0
5.0
t
3.3
5.0
5.0
5.0
5.0
5.0
5.0
5.0
w(L)
www.onsemi.com
7
MC74VHC595
SWITCHING WAVEFORMS
t
w
V
CC
V
CC
50%
SCLR
SCK
SQH
50%
GND
GND
t
t
PHL
w
1/f
max
50% V
CC
SQH
SCK
t
t
PHL
PLH
t
rec
V
CC
50% V
CC
50%
GND
Figure 2.
Figure 3.
V
CC
V
CC
50%
RCK
OE
50%
GND
GND
t
t
PLZ
PZL
HIGH
IMPEDANCE
50% V
t
t
CC
PLH
PHL
QA-QH
V
V
+0.3V
OL
t
t
PHZ
PZH
QA-QH
-0.3V
50% V
OH
CC
QA-QH
50% V
CC
HIGH
IMPEDANCE
Figure 4.
Figure 5.
V
CC
SCLR
50%
V
CC
GND
50%
VALID
SCK
RCK
V
CC
GND
50%
SI
t
su(H)
GND
V
CC
t
su
t
h
50%
V
CC
GND
50%
SCK or RCK
t
w
GND
Figure 6.
Figure 7.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
.
CC
TESTING t AND t
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 8.
Figure 9.
www.onsemi.com
8
MC74VHC595
TIMING DIAGRAM
SCK
ꢀSI
SCLR
RCK
OE
QA
QB
QC
QD
QE
QF
QG
QH
SQH
NOTE:
output is in a high−impedance state.
INPUT EQUIVALENT CIRCUIT
INPUT
www.onsemi.com
9
MC74VHC595
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X KREF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
M
S
S
0.10 (0.004)
T
U
V
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
−V−
A
B
C
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
10
MC74VHC595
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74VHC595/D
相关型号：
MC74VHC74DTR2
AHC/VHC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, TSSOP-14
MOTOROLA
MC74VHC74DTRG
AHC/VHC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, LEAD FREE, TSSOP-14
ONSEMI
©2020 ICPDF网 联系我们和版权申明