MC74VHCT00ADTEL [ONSEMI]
Quad 2-Input NAND Gate; 四路2输入与非门
| 型号： | MC74VHCT00ADTEL |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Input NAND Gate |
| 文件： | 总7页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT00A
Quad 2--Input NAND Gate
The MC74VHCT00A is an advanced high speed CMOS 2--input
NAND gate fabricated with silicon gate CMOS technology. It
achieves high speed operation while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL--type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic--level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high--voltage power supply.
The MC74VHCT00A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT00A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage -- input/output voltage mismatch, battery backup, hot
insertion, etc.
http://onsemi.com
MARKING DIAGRAMS
14
1
VHCT00A
AWLYYWW
SOIC--14
D SUFFIX
CASE 751A
14
VHCT
00A
AWLYWW
1
TSSOP--14
DT SUFFIX
CASE 948G
• High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C
• TTL--Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
14
VHCT00A
ALYW
1
• Designed for 3.0 V to 5.5 V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
SOIC EIAJ--14
M SUFFIX
• Pin and Function Compatible with Other Standard Logic Families
CASE 965
• Chip Complexity: 48 FETs or 12 Equivalent Gates
• These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping
48 Units/Rail
MC74VHCT00AD
MC74VHCT00ADR2
MC74VHCT00ADT
SOIC--14
SOIC--14 2500 Units/Reel
TSSOP--14 96 Units/Rail
MC74VHCT00ADTEL TSSOP--14 2000 Units/Reel
MC74VHCT00ADTR2 TSSOP--14 2000 Units/Reel
SOIC
MC74VHCT00AM
48 Units/Rail
EIAJ--14
SOIC
EIAJ--14
MC74VHCT00AMEL
2000 Units/Reel
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 -- Rev. 3
MC74VHCT00A/D
MC74VHCT00A
1
2
A1
3
6
Y1
Y2
Y3
Y4
B1
V
B4
A4
Y4
B3
A3
Y3
CC
4
5
14
13
12
11
10
9
8
A2
B2
Y = AB
9
A3
B3
8
10
12
13
A4
B4
1
2
3
4
5
6
7
11
A1
B1
Y1
A2
B2
Y2 GND
Figure 1. Pin Assignment
Figure 2. Logic Diagram
FUNCTION TABLE
(Top View)
PIN ASSIGNMENT
Inputs
Output
Y
1
2
IN A1
IN B1
A
B
L
L
L
H
L
H
H
H
L
3
OUT Y1
H
H
4
IN A2
IN B2
H
5
6
OUT Y2
GND
7
A1
B1
A2
B2
A3
1
8
OUT Y3
&
3
Y1
2
4
5
9
9
IN A3
IN B3
10
11
12
13
14
Y2
Y3
6
OUT Y4
IN A4
8
B3 10
A4 12
B4 13
IN B4
Y4
11
V
CC
Figure 3. IEC LOGIC DIAGRAM
http://onsemi.com
2
MC74VHCT00A
MAXIMUM RATINGS (Note 1)
Symbol
Characteristics
Value
Unit
V
This device contains
protection circuitry to guard
against damage due to high
static voltages or electric
fields. However, pre-
cautions must be taken to
avoid applications of any
voltage higher than maxi-
mum rated voltages to this
high--impedancecircuit.For
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
--0.5 to +7.0
--0.5 to +7.0
--0.5 to 7.0
CC
IN
V
V
= 0
CC
V
OUT
High or Low State
--0.5 to V + 0.5
CC
I
I
I
I
Input Diode Current
Output Diode Current
-- 2 0
+20
+25
+50
mA
mA
mA
mA
mW
IK
V
< GND; V
> V
OUT CC
OK
OUT
proper operation, V and
DC Output Current, per Pin
in
OUT
CC
V
out
should be constrained
DC Supply Current, V and GND
CC
to the range GND ≤ (V or
in
V
out
) ≤ V
.
CC
P
Power Dissipation in Still Air,
SOIC Packages (Note 2)
TSSOP Package (Note 2)
500
450
D
Unused inputs must al-
ways be tied to an appropri-
ate logic voltage level (e.g.,
T
L
Lead temperature, 1 mm from case for 10 s
Storage temperature
260
°C
°C
V
either GND or V ). Un-
CC
T
stg
--65 to +150
used outputs must be left
open.
V
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 3000
ESD
I
Latch--Up Performance
(Note 6)
Above V and Below GND at 125°C
±300
mA
Latch--Up
CC
*
Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions
is not implied.
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute--maximum--rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
2. Derating -- SOIC Packages: –7 mW/_C from 65_ to 125_C
-- TSSOP Package: --6.1 mW/_C from 65_ to 125_C
3. Tested to EIA/JESD22--A114--A
4. Tested to EIA/JESD22--A115--A
5. Tested to JESD22--C101--A
6. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
3.0
0.0
Max
5.5
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
5.5
5.5
V
VCC = 0
High or Low State
0.0
0.0
V
OUT
V
CC
T
Operating Temperature Range
Input Rise and Fall Time
-- 5 5
+125
°C
A
t , t
r
V
V
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
ns/V
f
CC
CC
http://onsemi.com
3
MC74VHCT00A
The θ of the package is equal to 1/Derating. Higher junction temperatures may affect the expected lifetime of the device per the table and
JA
figure below.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 4. Failure Rate vs. Time
Junction Temperature
DC ELECTRICAL CHARACTERISTICS
V
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
CC
Symbol
Parameter
Test Conditions
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
V
V
Minimum High--Level
Input Voltage
3.0
4.5
5.5
1.4
2.0
2.0
1.4
2.0
2.0
1.4
2.0
2.0
V
IH
Maximum Low--Level
Input Voltage
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
IL
V
I
= V or V
= --50 μA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
V
Minimum High--Level
Output Voltage
IN
IH
IL
IL
OH
OH
V
= V or V
IN
IH IL
V
= V or V
IN
OH
OH
IH
I
I
= --4 mA
= --8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
I
= V or V
= 50 μA
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
Maximum Low--Level
Output Voltage
IN
IH
IL
IL
OL
OL
V
= V or V
IN
IH IL
V
= V or V
IN
OL
OL
IH
I
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
I
I
I
I
Maximum Input
Leakage Current
V
= 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
μA
μA
mA
μA
IN
IN
Maximum Quiescent
Supply Current
V
= V or GND
5.5
5.5
0.0
2.0
20
40
CC
IN
CC
Quiescent Supply
Current
Input: V = 3.4 V
1.35
0.5
1.50
5.0
1.65
10
CCT
OPD
IN
Output Leakage
Current
V
= 5.5 V
OUT
http://onsemi.com
4
MC74VHCT00A
AC ELECTRICAL CHARACTERISTICS C
= 50 pF, Input t = t = 3.0 ns
load
r
f
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Min
Typ
Max
Min
Max
Min
Max
Symbol
Parameter
Maximum
Propogation Delay,
Input A or B to Y
Test Conditions
Unit
t
t
,
V
V
= 3.3 ± 0.3 V
C
= 15 pF
= 50 pF
4.1
5.5
10.0
13.5
11.0
15.0
13.0
17.5
ns
PLH
PHL
CC
CC
L
L
C
= 5.0 ± 0.5 V
C
C
= 15 pF
= 50 pF
3.1
3.6
6.9
7.9
8.0
9.0
9.5
10.5
L
L
C
Maximum Input
Capacitance
5.5
10
10
10
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
17
C
PD
Power Dissipation Capacitance (Note 7)
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ¯ V ¯ f + I . C is used to determine the no--load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ¯ V
¯ f + I ¯ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V, Measured in SO Package)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Characteristic
Unit
V
V
V
Quiet Output Maximum Dynamic V
0.4
0.8
-- 0 . 8
2.0
OLP
OL
Quiet Output Minimum Dynamic V
-- 0 . 4
V
OLV
OL
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
0.8
V
ILD
TEST POINT
OUTPUT
3.0 V
A or B
50%
DEVICE
UNDER
TEST
GND
C *
L
t
t
PHL
PLH
V
V
OH
OL
Y
50% V
CC
*Includes all probe and jig capacitance
Figure 5. Switching Waveforms
Figure 6. Test Circuit
INPUT
OUTPUT
*
*Parastic Diode
Figure 7. Input Equivalent Circuit
Figure 8. Output Equivalent Circuit
http://onsemi.com
5
MC74VHCT00A
PACKAGE DIMENSIONS
D SUFFIX
SOIC PACKAGE
CASE 751A--03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-- A --
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
14
1
8
7
-- B --
P 7 PL
M
M
0.25 (0.010)
B
MILLIMETERS
DIM MIN MAX
INCHES
G
MIN
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
1.27 BSC
0.19
0.10
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
-- T --
J
M
0.050 BSC
K
SEATING
D 14 PL
PLANE
0.25 0.008
0.25 0.004
0.009
0.009
M
S
S
0.25 (0.010)
T
B
A
0
5.80
0.25
7
0
7
_
_
_
_
6.20 0.228
0.50 0.010
0.244
0.019
DT SUFFIX
TSSOP PACKAGE
CASE 948G--01
ISSUE O
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
-- U --
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE --W--.
DETAIL E
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
K1
MIN
MAX
0.200
0.177
0 . 0 4 7
0.006
0.030
-- V --
A
B
C
4.90
4.30
-- -- --
5.10 0.193
4.50 0.169
1 . 2 0
J J1
-- -- --
D
F
0.05
0.50
0.15 0.002
0.75 0.020
SECTION N--N
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60 0.020
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
0.024
0.008
0.006
0.012
0.010
-- W --
C
6.40 BSC
0.252 BSC
0.10 (0.004)
SEATING
PLANE
M
0
8
0
8
_
_
_
_
-- T --
H
G
DETAIL E
D
http://onsemi.com
6
MC74VHCT00A
M SUFFIX
SOIC EIAJ PACKAGE
CASE 965--01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
14
8
7
E
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
_
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
DETAIL P
Z
D
MILLIMETERS
INCHES
VIEW P
DIM MIN
MAX
2.05
0.20
0.50
0.27
10.50 0.390
5.45
MIN
MAX
0 . 0 8 1
0.008
0.020
0.011
0.413
0.215
A
e
A
-- -- --
0.05
0.35
0.18
9.90
5.10
-- -- --
0.002
0.014
0.007
c
A
1
b
c
D
E
e
0.201
b
A
1
1.27 BSC
0.050 BSC
H
E
M
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
0.13 (0.005)
0.10 (0.004)
0.50
L
E
M
1
Z
0
0.70
-- -- --
10
0.90
1 . 4 2
10
0.035
0 . 0 5 6
0
_
_
_
_
Q
0.028
-- -- --
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800--282--9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 61312, Phoenix, Arizona 85082--1312 USA
Phone: 480--829--7710 or 800--344--3860 Toll Free USA/Canada
Fax: 480--829--7709 or 800--344--3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2--9--1 Kamimeguro, Meguro--ku, Tokyo, Japan 153--0051
Phone: 81--3--5773--3850
For additional information, please contact your
local Sales Representative.
MC74VHCT00A/D
相关型号：
MC74VHCT00ADTR2
NAND Gate, AHCT/VHCT Series, 4-Func, 2-Input, CMOS, PDSO14, PLASTIC, TSSOP-14
MOTOROLA
©2020 ICPDF网 联系我们和版权申明