MC74VHCT14DR2 [ONSEMI]
AHCT/VHCT SERIES, HEX 1-INPUT INVERT GATE, PDSO14, SOIC-14;型号: | MC74VHCT14DR2 |
厂家: | ONSEMI |
描述: | AHCT/VHCT SERIES, HEX 1-INPUT INVERT GATE, PDSO14, SOIC-14 输入元件 光电二极管 逻辑集成电路 |
文件: | 总6页 (文件大小:84K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC74VHCT14A
Hex Schmitt Inverter
The MC74VHCT14A is an advanced high speed CMOS Schmitt
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the
MC74VHCT04A, but the inputs have hysteresis and, with its Schmitt
trigger function, the VHCT14A can be used as a line receiver which
will receive slow input signals.
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MARKING DIAGRAMS
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT14A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
14
VHCT14A
AWLYWW
SOIC−14
D SUFFIX
CASE 751A
1
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
14
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
VHCT
14A
ALYW
TSSOP−14
DT SUFFIX
CASE 948G
• High Speed: t = 5.5 ns (Typ) at V = 5.0 V
PD
CC
• Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C
CC
A
1
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
14
1
VHCT
14A
ALYW
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: 60 FETs or 15 Equivalent Gates
• Pb−Free Packages are Available*
SOEIAJ−14
M SUFFIX
CASE 965
A
= Assembly Location
= Year
WL, L = Wafer Lot
Y
W, WW = Work Week
FUNCTION TABLE
Inputs
A
Outputs
Y
L
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
June, 2004 − Rev. 3
MC74VHCT14A/D
MC74VHCT14A
1
3
5
2
4
6
A1
A2
A3
Y1
Y2
Y3
PIN CONNECTIONS
V
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
CC
14
Y = A
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
11
13
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3 GND
Pinout: 14−Lead Packages (Top View)
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +7.0
−0.5 to +7.0
CC
V
IN
Output in HIGH or LOW State (Note 1)
−0.5 to V +0.5 V
V
OUT
OUT
CC
V
CC
= 0 V
−0.5 to 7.0
−20
V
I
I
I
I
I
DC Input Diode Current
mA
mA
mA
mA
mA
°C
IK
DC Output Diode Current
$20
OK
O
DC Output Source/Sink Current
DC Supply Current per Supply Pin
$25
$50
CC
GND
DC Ground Current per Ground Pin
Storage Temperature Range
$50
T
T
T
−65 to +150
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
260
°C
L
+150
°C
J
q
SOIC
TSSOP
125
170
°C/W
JA
P
V
Power Dissipation in Still Air
SOIC
TSSOP
500
450
mW
V
D
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
>2000
>200
2000
ESD
I
Latch−Up Performance Above V and Below GND at 85°C (Note 5)
$300
mA
Latchup
CC
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum−rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. I absolute maximum rating must be observed.
O
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
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2
MC74VHCT14A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
5.5
Unit
V
V
V
V
V
Supply Voltage
CC
I
Input Voltage
5.5
V
Output Voltage (Note 6)
0
V
CC
V
O
O
V
CC
= 0 V
0
5.5
V
T
A
Operating Free−Air Temperature
−55
+125
°C
6. I absolute maximum rating must be observed.
O
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
V
CC
V
Min Typ Max Min Max Min Max
Symbol
Parameter
Test Conditions
Unit
V
V
V
V
Positive Threshold Voltage
4.5
5.5
1.9
2.1
1.9
2.1
1.9
2.1
V
V
V
V
T+
T−
H
Negative Threshold Voltage
Hysteresis Voltage
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
4.5
5.5
0.40
0.40
1.40 0.40 1.40 0.40 1.40
1.50 0.40 1.50 0.40 1.50
Minimum High−Level Output Voltage
V
= V or V
= −50 mA
4.5
4.4
4.5
0.0
4.4
4.4
OH
IN
IH
IL
I
= −50 mA
I
OH
OH
I
= −8.0 mA
5.5
4.5
3.94
3.80
3.66
OH
V
OL
Maximum Low−Level Output Voltage
V
IN
= V or V
0.1
0.1
0.1
V
IH
IL
I
OL
= 50 mA
I
= 8.0 mA
5.5
0.36
±0.1
2.0
0.44
±1.0
20
0.52
±1.0
40
OL
I
I
I
I
Maximum Input Leakage Current
Maximum Quiescent Supply Current
Quiescent Supply Current
V
= 5.5 V or GND 0 to 5.5
mA
mA
IN
IN
IN
V
= V or GND
5.5
5.5
0.0
CC
CC
Input: V = 3.4 V
1.35
0.5
1.50
5.0
1.65 mA
CCT
OFF
IN
Output Leakage Current
V
= 5.5 V
10
mA
OUT
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
Min Typ Max Min Max Min Max
Symbol
Parameter
Test Conditions
Unit
t
t
,
Maximum Propagation Delay, A to Y
V
CC
= 5.0 ± 0.5 V C = 15 pF
5.5
7.0
7.6
9.6
1.0
1.0
9.0
11.0
1.0
1.0
11.5
13.5
ns
PLH
PHL
L
C = 50 pF
L
C
Maximum Input Capacitance
2.0
10
10
10
pF
IN
Typical @ 25°C, V = 5.0 V
CC
11
C
Power Dissipation Capacitance (Note 7)
pF
PD
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /6 (per buffer). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
1.0
Symbol
Characteristic
Quiet Output Maximum Dynamic V
Unit
V
V
OLP
V
OLV
V
IHD
V
ILD
0.8
OL
Quiet Output Minimum Dynamic V
−0.8
−1.0
2.0
V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
0.8
V
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3
MC74VHCT14A
TEST POINT
OUTPUT
3.0V
GND
1.5V
A
Y
DEVICE
UNDER
TEST
t
t
PHL
PLH
C *
L
V
V
OH
1.5V
OL
*Includes all probe and jig capacitance
Figure 2. Switching Waveforms
Figure 3. Test Circuit
(a) A Schmitt−Trigger Squares Up Inputs With Slow Rise and Fall Times
(b) A Schmitt−Trigger Offers Maximum Noise Immunity
V
CC
V
CC
V
H
V
H
V
V
V
V
T+
T+
V
in
V
in
T−
T−
GND
GND
V
V
OH
OL
OH
OL
V
out
V
out
V
V
Figure 4. Typical Schmitt−Trigger Applications
ORDERING INFORMATION
Device
†
Package
Shipping
MC74VHCT14DR2
MC74VHCT14DR2G
SOIC−14
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−14
(Pb−Free)
MC74VHCT14DTR2
MC74VHCT14AM
MC74VHCT14AMEL
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
50 Units / Rail
SOEIAJ−14
(Pb−Free)
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MC74VHCT14A
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−A−
14
8
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
G
F
R X 45
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
_
C
−T−
SEATING
PLANE
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
J
M
K
0.19
0.10
0
D 14 PL
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
14X K REF
M
S
S
0.10 (0.004)
T U
V
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
MILLIMETERS
INCHES
MIN
K1
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
−V−
A
B
4.90
4.30
−−−
0.05
0.50
0.193
0.169
−−−
0.002
0.020
J J1
C
D
F
SECTION N−N
G
H
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
J
J1
K
−W−
C
K1
L
6.40 BSC
_
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
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5
MC74VHCT14A
PACKAGE DIMENSIONS
SOEIAJ−14
M SUFFIX
CASE 965−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
14
8
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
−−−
VIEW P
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
e
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
c
A
1
b
c
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
D
E
e
b
A
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
0.70
−−−
10
0.90 0.028
10
0.035
0.056
0
_
_
_
_
Q
1
Z
1.42
−−−
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC14/D
相关型号:
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