MC74VHCXXXXDT [ONSEMI]
Quad Analog Switch/Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS; 四路模拟开关/多路复用器/多路解复用器高性能硅栅CMOS
| 型号： | MC74VHCXXXXDT |
| 厂家： | 
ONSEMI |
| 描述： | Quad Analog Switch/Multiplexer/Demultiplexer High−Performance Silicon−Gate CMOS |
| 文件： | 总13页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductort
Quad Analog Switch/
Multiplexer/Demultiplexer
MC74VHC4066
High−Performance Silicon−Gate CMOS
The MC74VHC4066 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
D SUFFIX
14−LEAD SOIC PACKAGE
CASE 751A−03
OFF−channel
leakage
current.
This
bilateral
switch/multiplexer/demultiplexer controls analog and digital voltages
that may vary across the full power−supply range (from V to GND).
CC
The VHC4066 is identical in pinout to the metal−gate CMOS
MC14066 and the high−speed CMOS HC4066A. Each device has four
independent switches. The device has been designed so that the ON
DT SUFFIX
14−LEAD TSSOP PACKAGE
CASE 948G−01
resistances (R ) are much more linear over input voltage than R
ON
ON
of metal−gate CMOS analog switches.
The ON/OFF control inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs. For analog switches with voltage−level translators, see the
VHC4316.
ORDERING INFORMATION
MC74VHCXXXXD
MC74VHCXXXXDT
SOIC
TSSOP
• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
PIN ASSIGNMENT
V
CC
X
A
1
2
3
4
5
6
7
14
13
12
11
10
9
• Wide Power−Supply Voltage Range (V − GND) = 2.0 to 12.0 Volts
CC
A ON/OFF
CONTROL
Y
A
• Analog Input Voltage Range (V − GND) = 2.0 to 12.0 Volts
CC
D ON/OFF
CONTROL
Y
B
• Improved Linearity and Lower ON Resistance over Input Voltage
than the MC14016 or MC14066
• Low Noise
X
B
X
D
B ON/OFF
CONTROL
Y
Y
X
D
C
C ON/OFF
CONTROL
• Chip Complexity: 44 FETs or 11 Equivalent Gates
8
GND
w These devices are available in Pb−free package(s). Specifications herein
apply to both standard and Pb−free devices. Please see our website at
www.onsemi.com for specific Pb−free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
C
FUNCTION TABLE
On/Off Control
State of
Input
Analog Switch
L
H
Off
On
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 − Rev. 5
MC74VHC4066/D
1
2
3
X
Y
A
A
13
4
A ON/OFF CONTROL
X
B
Y
B
Y
C
Y
D
ANALOG
5
B ON/OFF CONTROL
OUTPUTS/INPUTS
8
9
X
C
6
C ON/OFF CONTROL
ANALOG INPUTS/OUTPUTS = X , X , X , X
D
A
B
C
11
12
10
PIN 14 = V
CC
PIN 7 = GND
X
D
D ON/OFF CONTROL
Figure 1. Logic Diagram
MAXIMUM RATINGS*
Symbol
V
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
DC Current Into or Out of Any Pin
– 0.5 to + 14.0
CC
V
IS
– 0.5 to V + 0.5
V
CC
V
in
– 0.5 to V + 0.5
V
CC
I
± 25
mA
mW
cuit. For proper operation, V and
in
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
T
stg
Storage Temperature
– 65 to + 150
260
_C
_C
Unused inputs must always be
tied to an appropriate logic voltage
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
level (e.g., either GND or V ).
CC
*Maximum Ratings are those values beyond which damage to the device may occur.
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
Max
Unit
V
V
CC
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time, ON/OFF Control
12.0
V
IS
GND
GND
—
V
CC
V
CC
V
V
in
V
V *
IO
1.2
V
T
A
– 55 + 125
_C
ns
t , t
r
f
Inputs (Figure 14)
V
V
V
V
= 2.0 V
= 3.0 V
= 4.5 V
= 9.0 V
0
0
0
0
0
1000
600
500
400
250
CC
CC
CC
CC
V
CC
= 12.0 V
*For voltage drops across the switch greater than 1.2 V (switch on), excessive V current may
CC
be drawn; i.e., the current out of the switch may contain both V
and switch input
CC
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
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2
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
v
V
V
CC
25_C
125_C
v 85_C
Symbol
Parameter
Test Conditions
= Per Spec
Unit
V
IH
Minimum High−Level Voltage
ON/OFF Control Inputs
R
R
2.0
3.0
1.5
2.1
1.5
2.1
1.5
2.1
V
on
on
4.5
9.0
12.0
3.15
6.3
8.4
3.15
6.3
8.4
3.15
6.3
8.4
V
IL
Maximum Low−Level Voltage
ON/OFF Control Inputs
= Per Spec
2.0
3.0
0.5
0.9
0.5
0.9
0.5
0.9
V
4.5
9.0
1.35
2.7
1.35
2.7
1.35
2.7
12.0
3.6
3.6
3.6
I
Maximum Input Leakage
Current
ON/OFF Control Inputs
V
= V or GND
12.0
± 0.1
± 1.0
± 1.0
μA
μA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
V
V
= V or GND
6.0
12.0
2
4
20
40
40
160
CC
in
IO
CC
= 0 V
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
v
V
V
CC
25_C
125_C
v 85_C
Symbol
Parameter
Test Conditions
Unit
R
Maximum “ON” Resistance
Ω
V
V
I
= V
2.0†
3.0†
4.5
9.0
12.0
—
—
—
—
—
—
200
100
100
on
in
IH
= V to GND
v 2.0 mA
IS
CC
120
70
70
160
85
85
S
(Figures 2 through 7)
V
V
I
= V
2.0
3.0
4.5
9.0
12.0
—
—
70
50
30
—
—
85
60
60
—
—
100
80
in
IH
= V or GND (Endpoints)
v 2.0 mA
IS
CC
S
(Figures 2 through 7)
80
ΔR
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
I
= V
IH
= 1/2 (V − GND)
v 2.0 mA
2.0
4.5
9.0
—
20
15
15
—
25
20
20
—
30
25
25
Ω
on
in
IS
CC
S
12.0
I
I
Maximum Off−Channel
Leakage
Current, Any One Channel
V
V
= V
IL
12.0
12.0
0.1
0.5
1.0
μA
μA
off
in
= V or GND
IO
CC
Switch Off (Figure NO TAG)
Maximum On−Channel
Leakage
V
V
= V
IH
0.1
0.5
1.0
on
in
= V or GND
IS
CC
Current, Any One Channel
(Figure NO TAG)
†At supply voltage (V ) approaching 3 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage
CC
operation, it is recommended that these devices only be used to control digital signals.
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3
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, ON/OFF Control Inputs: t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
v
V
V
CC
25_C
125_C
v 85_C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 18 and 13)
2.0
3.0
4.5
40
30
5
50
40
7
60
50
8
ns
PLH
t
PHL
9.0
12.0
5
5
7
7
8
8
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 14 and 15)
2.0
3.0
4.5
9.0
12.0
80
60
20
20
20
90
70
25
25
25
110
80
35
35
35
ns
ns
pF
PLZ
t
PHZ
,
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 14 and 15)
2.0
3.0
4.5
9.0
12.0
80
45
20
20
20
90
50
25
25
25
100
60
30
30
30
PZL
t
PZH
C
Maximum Capacitance
ON/OFF Control Input
—
10
10
10
Control Input = GND
Analog I/O
—
—
35
1.0
35
1.0
35
1.0
Feedthrough
Typical @ 25°C, V = 5.0 V
CC
15
C
Power Dissipation Capacitance (Per Switch) (Figure 17)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Limit*
25_C
74HC
V
V
CC
Symbol
Parameter
Test Conditions
= 1 MHz Sine Wave
Unit
BW
Maximum On−Channel Bandwidth or
Minimum Frequency Response
(Figure NO TAG)
f
in
4.5
9.0
12.0
150
160
160
MHz
Adjust f Voltage to Obtain 0 dBm at V
in
OS
Increase f Frequency Until dB Meter Reads
in
– 3 dB
R = 50 Ω, C = 10 pF
L
L
—
—
Off−Channel Feedthrough Isolation
(Figure NO TAG)
f
ꢀ Sine Wave
4.5
9.0
12.0
− 50
− 50
− 50
dB
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
L
L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
4.5
9.0
12.0
− 40
− 40
− 40
L
L
Feedthrough Noise, Control to
Switch
(Figure NO TAG)
V
v 1 MHz Square Wave (t = t = 6 ns)
4.5
9.0
12.0
60
130
200
mV
in
r
f
PP
Adjust R at Setup so that I = 0 A
L
S
R = 600 Ω, C = 50 pF
L
L
R = 10 kΩ, C = 10 pF
4.5
9.0
30
65
L
L
12.0
100
—
Crosstalk Between Any Two
Switches
(Figure 16)
f
ꢀ Sine Wave
4.5
9.0
12.0
– 70
– 70
– 70
dB
%
in
Adjust f Voltage to Obtain 0 dBm at V
in
IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
L
L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
4.5
9.0
12.0
– 80
– 80
– 80
L
L
THD
Total Harmonic Distortion
(Figure 20)
f
in
= 1 kHz, R = 10 kΩ, C = 50 pF
L
L
THD = THD
− THD
Measured
Source
V
V
= 4.0 V sine wave
4.5
9.0
12.0
0.10
0.06
0.04
IS
IS
PP
= 8.0 V sine wave
PP
V
IS
= 11.0 V sine wave
PP
*Guaranteed limits not tested. Determined by design and verified by qualification.
400
350
300
250
200
150
+25 _C
+125_C
−55_C
100
50
0
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
V , INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
is
Figure 2. Typical On Resistance, VCC = 2.0 V
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5
200
180
160
140
120
100
80
+25 _C
+125_C
−55_C
60
40
20
0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
V , INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
is
Figure 3. Typical On Resistance, VCC = 4.5 V
90
80
70
60
50
40
30
20
10
0
+25 _C
+125_C
−55_C
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
5.50
6.00
V , INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
is
Figure 4. Typical On Resistance, VCC = 6.0 V
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6
90
80
70
60
50
40
30
20
10
0
+25 _C
+125_C
−55_C
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00
V , INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
is
Figure 5. Typical On Resistance, VCC = 9.0 V
60
50
40
30
20
10
0
+25 _C
+125_C
−55_C
0.00
1.00
2.00
3.00
4.00
5.00
6.00
7.00
8.00
9.00 10.00 11.00 12.00
V , INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
is
Figure 6. Typical On Resistance, VCC = 12 V
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7
PLOTTER
V
CC
V
CC
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
14
GND
A
OFF
V
CC
−
+
V
CC
DEVICE
UNDER TEST
SELECTED
CONTROL
INPUT
V
IL
ANALOG IN
COMMON OUT
7
GND
Figure 7. On Resistance Test Set−Up
Figure 8. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
V
OS
V
CC
V
CC
14
V
CC
14
f
in
ON
dB
N/C
A
ON
0.1μF
C *
L
METER
GND
SELECTED
CONTROL
INPUT
V
CC
SELECTED
CONTROL
INPUT
V
IH
7
7
*Includes all probe and jig capacitance.
Figure 9. Maximum On Channel Leakage Current,
Figure 10. Maximum On−Channel Bandwidth
Test Set−Up
Test Set−Up
V
CC
V
CC/2
V
CC/2
V
OS
V
CC
V
IS
14
14
f
in
OFF
R
R
L
L
dB
V
OS
0.1μF
C *
L
R
L
METER
I
OFF/ON
S
C *
L
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
7
V ≤ 1 MHz
7
in
t = t = 6 ns
r
f
V
CC
CONTROL
*Includes all probe and jig capacitance.
GND
*Includes all probe and jig capacitance.
Figure 11. Off−Channel Feedthrough Isolation,
Test Set−Up
Figure 12. Feedthrough Noise, ON/OFF Control to
Analog Out, Test Set−Up
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8
V
CC
14
V
CC
ANALOG IN
ANALOG OUT
C *
TEST
ON
POINT
50%
ANALOG IN
L
GND
t
t
PHL
PLH
SELECTED
CONTROL
INPUT
V
CC
50%
7
ANALOG OUT
*Includes all probe and jig capacitance.
Figure 18. Propagation Delays, Analog In to
Analog Out
Figure 13. Propagation Delay Test Set−Up
1
POSITIONꢀꢀꢁWHEN TESTING t
AND t
PZH
PHZ
2
POSITIONꢀꢀWHEN TESTING t AND t
t
r
t
f
PLZ
PZL
1
2
V
CC
90%
50%
10%
V
CC
CONTROL
V
CC
1 kΩ
14
GND
1
2
t
t
t
PLZ
TEST
POINT
PZL
HIGH
ON/OFF
IMPEDANCE
C *
L
50%
50%
10%
90%
V
OL
SELECTED
CONTROL
INPUT
ANALOG
OUT
t
PZH
PHZ
V
OH
7
HIGH
IMPEDANCE
*Includes all probe and jig capacitance.
Figure 14. Propagation Delay, ON/OFF Control
to Analog Out
Figure 15. Propagation Delay Test Set−Up
V
IS
V
CC
V
CC
14
R
L
V
OS
A
f
in
ON
0.1 μF
14
OFF
N/C
OFF/ON
N/C
V
CC
OR GND
R
L
C *
L
R
L
C *
L
R
L
SELECTED
CONTROL
INPUT
V
CC/2
V
CC/2
SELECTED
CONTROL
INPUT
7
7
V
CC/2
ON/OFF CONTROL
*Includes all probe and jig capacitance.
Figure 16. Crosstalk Between Any Two Switches,
Figure 17. Power Dissipation Capacitance
Test Set−Up
Test Set−Up
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9
0
−ꢂ10
−ꢂ20
−ꢂ30
−ꢂ40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
V
OS
0.1 μF
TO
f
in
ON
DISTORTION
METER
C *
L
R
L
−ꢂ50
−ꢂ60
−ꢂ70
−ꢂ80
−ꢂ90
DEVICE
V
CC/2
SOURCE
SELECTED
CONTROL
INPUT
V
CC
7
1.0
2.0
FREQUENCY (kHz)
3.0
*Includes all probe and jig capacitance.
Figure 20. Total Harmonic Distortion, Test Set−Up
Figure 19. Plot, Harmonic Distortion
the example below, the difference between VCC and GND is
twelve volts. Therefore, using the configuration in Figure 21,
a maximum analog signal of twelve volts peak−to−peak can
be controlled.
When voltage transients above VCC and/or below GND
are anticipated on the analog channels, external diodes
(Dx) are recommended as shown in Figure 22. These
diodes should be small signal, fast turn−on types able to
absorb the maximum anticipated current surges during
clipping. An alternate method would be to replace the Dx
diodes with Mosorbs (high current surge protectors).
Mosorbs are fast turn−on devices ideally suited for precise
DC protection with no inherent wear out mechanism.
APPLICATION INFORMATION
The ON/OFF Control pins should be at VCC or GND logic
levels, VCC being recognized as logic high and GND being
recognized as a logic low. Unused analog inputs/outputs
may be left floating (not connected). However, it is
advisable to tie unused analog inputs and outputs to VCC or
GND through a low value resistor. This minimizes crosstalk
and feedthrough noise that may be picked−up by the
unused I/O pins.
The maximum analog voltage swings are determined by
the supply voltages VCC and GND. The positive peak
analog voltage should not exceed VCC. Similarly, the
negative peak analog voltage should not go below GND. In
V
CC
= 12 V
V
CC
V
CC
14
D
D
+ 12 V
0 V
D
D
+ 12 V
0 V
x
x
16
ANALOG I/O
ANALOG O/I
ON
ON
x
x
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
V
CC
OTHER CONTROL
INPUTS
(V OR GND)
OTHER CONTROL
INPUTS
(V OR GND)
7
CC
7
CC
Figure 21. 12 V Application
Figure 22. Transient Suppressor Application
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10
+
5 V
+ꢂ5 V
14
14
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
VHCT
R* R* R* R*
VHC4066
VHC4066
LSTTL/
NMOS
LSTTL/
NMOS
BUFFER
5
6
5
6
CONTROL
INPUTS
CONTROL
INPUTS
14
15
14
15
7
7
R* = 2 TO 10 kΩ
a. Using Pull-Up Resistors
b. Using HCT Buffer
Figure 23. LSTTL/NMOS to HCMOS Interface
V
DD
= 5 V
V
CC
= 5 TO 12 V
1
16
14
13
3
ANALOG
SIGNALS
ANALOG
SIGNALS
VHC4066
5
7
2
5
6
MC14504
9
4
CONTROL
INPUTS
11
14
6
14
15
10
8
7
Figure 24. TTL/NMOS−to−CMOS Level Converter Analog Signal
Peak−to−Peak Greater than 5 V
(Also see VHC4316)
1 OF 4
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
SWITCHES
1 OF 4
SWITCHES
COMMON I/O
1 OF 4
−
+
SWITCHES
OUTPUT
1 OF 4
INPUT
LF356 OR
SWITCHES
EQUIVALENT
1 OF 4
SWITCHES
0.01 μF
1
2
3
4
CONTROL INPUTS
Figure 25. 4−Input Multiplexer
Figure 26. Sample/Hold Amplifier
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11
OUTLINE DIMENSIONS
D SUFFIX
SOIC−14
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
8.75
4.00
1.75
0.49
1.25
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
0.337
0.150
0.054
0.014
0.016
−T−
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
M
S
S
0.25 (0.010)
T
B
A
K
M
P
R
_
_
_
_
5.80
0.25
6.20
0.50
0.228
0.010
0.244
0.019
DT SUFFIX
TSSOP
CASE 948G−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
14X K REF
M
S
S
0.10 (0.004)
T
U
V
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
L
N
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
INCHES
MIN
K1
DIM MIN
MAX
5.10
4.50
1.20
0.15
0.75
MAX
0.200
0.177
0.047
0.006
0.030
A
B
4.90
4.30
−−−
0.193
0.169
−−−
J J1
C
D
0.05
0.50
0.002
0.020
F
SECTION N−N
G
H
0.65 BSC
0.026 BSC
0.50
0.09
0.09
0.19
0.19
0.60
0.20
0.16
0.30
0.25
0.020
0.004
0.004
0.007
0.007
0.024
0.008
0.006
0.012
0.010
J
J1
K
−W−
C
K1
L
6.40 BSC
_
0.252 BSC
0
0.10 (0.004)
M
0
8
8
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
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