MJD200G [ONSEMI]
Complementary Plastic Power Transistors; 互补的塑料功率晶体管
| 型号： | MJD200G |
| 厂家： | 
ONSEMI |
| 描述： | Complementary Plastic Power Transistors |
| 文件： | 总6页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MJD200 (NPN)
MJD210 (PNP)
Complementary Plastic
Power Transistors
NPN/PNP Silicon DPAK For Surface
Mount Applications
http://onsemi.com
Designed for low voltage, low−power, high−gain audio
amplifier applications.
SILICON
POWER TRANSISTORS
5 AMPERES
Features
• Collector−Emitter Sustaining Voltage −
25 VOLTS, 12.5 WATTS
V
= 25 Vdc (Min) @ I = 10 mAdc
C
CEO(sus)
• High DC Current Gain − h = 70 (Min) @ I = 500 mAdc
FE
C
= 45 (Min) @ I = 2 Adc
C
4
= 10 (Min) @ I = 5 Adc
C
• Lead Formed for Surface Mount Applications in Plastic Sleeves
(No Suffix)
2
1
3
• Low Collector−Emitter Saturation Voltage −
DPAK
CASE 369C
STYLE 1
V
CE(sat)
= 0.3 Vdc (Max) @ I = 500 mAdc
C
= 0.75 Vdc (Max) @ I = 2.0 Adc
C
• High Current−Gain − Bandwidth Product −
f = 65 MHz (Min) @ I = 100 mAdc
T
C
• Annular Construction for Low Leakage −
= 100 nAdc @ Rated V
MARKING DIAGRAM
I
CBO
CB
• Epoxy Meets UL 94 V−0 @ 0.125 in
YWW
J2x0G
• ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
• Pb−Free Packages are Available
Y
= Year
MAXIMUM RATINGS
WW = Work Week
x = 1 or 0
G
Rating
Collector−Base Voltage
Collector−Emitter Voltage
Emitter−Base Voltage
Symbol
Max
40
Unit
Vdc
Vdc
Vdc
Adc
= Pb−Free Package
V
CB
V
25
CEO
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
V
8.0
EB
I
5.0
10
Collector Current − Continuous
− Peak
C
Base Current
I
1.0
Adc
B
P
12.5
0.1
W
W/°C
Total Power Dissipation @ T = 25°C
D
D
C
Derate above 25°C
Total Power Dissipation (Note 1)
P
1.4
0.011
W
W/°C
@ T = 25°C
A
Derate above 25°C
Operating and Storage Junction
Temperature Range
T , T
−65 to +150
°C
J
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. These ratings are applicable when surface mounted on the minimum pad
sizes recommended.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
August, 2006 − Rev. 8
MJD200/D
MJD200 (NPN) MJD210 (PNP)
THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Ambient (Note 2)
Symbol
Max
Unit
R
q
JC
10
°C/W
R
q
JA
89.3
°C/W
2. These ratings are applicable when surface mounted on the minimum pad sizes recommended.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage (Note 3), (I = 10 mAdc, I = 0)
V
CEO(sus)
25
−
Vdc
C
B
Collector Cutoff Current
(V = 40 Vdc, I = 0)
V
CBO
−
−
100
100
nAdc
mAdc
CB
E
(V = 40 Vdc, I = 0, T = 125°C)
CB
E
J
Emitter Cutoff Current (V = 8 Vdc, I = 0)
V
−
100
nAdc
−
BE
C
EBO
ON CHARACTERISTICS
DC Current Gain (Note 3),
h
FE
(I = 500 mAdc, V = 1 Vdc)
C
CE
70
45
10
−
180
−
(I = 2 Adc, V = 1 Vdc)
C
CE
(I = 5 Adc, V = 2 Vdc)
C
CE
Collector−Emitter Saturation Voltage (Note 3)
(I = 500 mAdc, I = 50 mAdc)
V
V
Vdc
CE(sat)
BE(sat)
C
B
−
−
−
0.3
0.75
1.8
(I = 2 Adc, I = 200 mAdc)
C
B
(I = 5 Adc, I = 1 Adc)
C
B
Base−Emitter Saturation Voltage (Note 3), (I = 5 Adc, I = 1 Adc)
−
−
2.5
1.6
Vdc
Vdc
C
B
Base−Emitter On Voltage (Note 3), (I = 2 Adc, V = 1 Vdc)
V
BE(on)
C
CE
DYNAMIC CHARACTERISTICS
Current−Gain − Bandwidth Product (Note 4)
f
65
−
MHz
pF
T
(I = 100 mAdc, V = 10 Vdc, f
= 10 MHz)
C
CE
test
Output Capacitance
MJD200
MJD210
C
−
−
80
120
ob
(V = 10 Vdc, I = 0, f = 0.1 MHz)
CB
E
3. Pulse Test: Pulse Width = 300 ms, Duty Cycle [ 2%.
4. f = ⎪h ⎪• f
.
test
T
fe
ORDERING INFORMATION
†
Device
MJD200
Package Type
Shipping
DPAK
75 Units / Rail
1800 / Tape & Reel
2500 / Tape & Reel
75 Units / Rail
MJD200G
DPAK
(Pb−Free)
MJD200RL
DPAK
MJD200RLG
DPAK
(Pb−Free)
MJD200T4
DPAK
MJD200T4G
DPAK
(Pb−Free)
MJD210
DPAK
MJD210G
DPAK
(Pb−Free)
MJD210RL
DPAK
1800 / Tape & Reel
2500 / Tape & Reel
MJD210RLG
DPAK
(Pb−Free)
MJD210T4
DPAK
MJD210T4G
DPAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
2
MJD200 (NPN) MJD210 (PNP)
T
A
T
C
2.5 25
V
CC
+ꢀ30 V
2
20
25 ms
R
+11 V
C
SCOPE
0
R
1.5 15
B
−ꢀ9 V
D
T (SURFACE MOUNT)
A
1
51
1
0.5
0
10
5
t , t ≤ 10 ns
r
f
DUTY CYCLE = 1%
T
C
−ꢀ4 V
R and R VARIED TO OBTAIN DESIRED CURRENT LEVELS
B
C
D MUST BE FAST RECOVERY TYPE, e.g.:
1
0
FOR PNP TEST CIRCUIT,
REVERSE ALL POLARITIES
ꢁ1N5825 USED ABOVE I ≈ 100 mA
ꢁMSD6100 USED BELOW I ≈ 100 mA
B
25
50
75
100
125
150
B
T, TEMPERATURE (°C)
Figure 1. Power Derating
Figure 2. Switching Time Test Circuit
1K
10K
5K
t
d
V
I /I = 10
= 30 V
500
CC
t
s
300
200
3K
2K
C B
I = I
B1 B2
T = 25°C
J
100
50
1K
500
30
20
300
200
t
r
V
= 30 V
CC
I /I = 10
C B
10
5
100
T = 25°C
J
50
3
2
30
20
MJD200
MJD210
MJD200
MJD210
t
f
1
0.01
10
0.01
0.03 0.05 0.1
0.2 0.3 0.5
1
2
3
5
10
0.03 0.05 0.1
0.02
0.2 0.3 0.5
1
2
3
5
10
0.02
I , COLLECTOR CURRENT (A)
C
I , COLLECTOR CURRENT (A)
C
Figure 3. Turn−On Time
Figure 4. Turn−Off Time
http://onsemi.com
3
+
2
*APPLIES FOR I /I ≤ h
C B FE/3
1.5
+1
0.5
0
+ꢀ0.5
−
−
−
0.5
−ꢀ0.5
−1
1.5
−ꢀ55°C to 25°C
−
2
−ꢀ55°C to 25°C
2.5
0.05 0.07 0.1
−ꢀ2.5
0.05 0.07 0.1
+
+
+
2.5
+ꢀ2.5
+ꢀ2
MJD200 (NPN) MJD210 (PNP)
NPN
PNP
MJD200
MJD210
400
200
400
T = 150°C
J
25°C
T = 150°C
J
200
25°C
−ꢀ55°C
100
80
100
80
−ꢀ55°C
60
40
60
40
V
V
= 1 V
= 2 V
V
V
= 1 V
= 2 V
CE
CE
CE
CE
20
20
0.05 0.07 0.1
0.2 0.3
0.5 0.7
1
2
3
5
0.05 0.07 0.1
0.2 0.3
0.5 0.7
1
2
3
5
I , COLLECTOR CURRENT (A)
C
I , COLLECTOR CURRENT (A)
C
Figure 5. DC Current Gain
2
2
T = 25°C
J
T = 25°C
J
1.6
1.2
0.8
0.4
0
1.6
1.2
0.8
V
@ I /I = 10
C B
V
@ I /I = 10
BE(sat) C B
BE(sat)
V
@ V = 1 V
CE
BE
V
@ V = 1 V
CE
BE
0.4
0
V
@ I /I = 10
C B
CE(sat)
V
@ I /I = 10
C B
CE(sat)
0.05 0.07 0.1
0.2 0.3
0.5 0.7
1
2
3
5
0.05 0.07 0.1
0.2 0.3
0.5 0.7
1
2
3
5
I , COLLECTOR CURRENT (A)
C
I , COLLECTOR CURRENT (A)
C
Figure 6. “On” Voltage
*APPLIES FOR I /I ≤ h
C B
FE/3
+ꢀ1.5
+ꢀ1
25°C to 150°C
−ꢀ55°C to 25°C
25°C to 150°C
q
for V
CE(sat)
*q for V
VC
VC
CE(sat)
0
−ꢀ55°C to 25°C
25°C to 150°C
25°C to 150°C
−ꢀ1
q
for V
BE
VB
−ꢀ1.5
q
for V
BE
VB
−ꢀ2
0.2 0.3
0.5 0.7
1
2
3
5
0.2 0.3
0.5 0.7
1
2
3
5
I , COLLECTOR CURRENT (A)
C
I , COLLECTOR CURRENT (A)
C
Figure 7. Temperature Coefficients
http://onsemi.com
4
MJD200 (NPN) MJD210 (PNP)
1
0.7
0.5
D = 0.5
0.2
0.1
0.3
0.2
P
(pk)
R
R
(t) = r(t) q
JC
q
q
JC
= 10°C/W MAX
0.05
JC
0.1
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.07
0.05
t
1
0.02
t
2
1
0.01
T
− T = P q
C (pk) JC
(t)
J(pk)
0.03
0.02
DUTY CYCLE, D = t /t
1 2
0 (SINGLE PULSE)
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
20
50
100
200
t, TIME (ms)
Figure 8. Thermal Response
10
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
5ꢂms
5
3
2
breakdown. Safe operating area curves indicate I − V
C
CE
T = 150°C
J
100ꢂms
500ꢂms
1ꢂms
dc
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
1
The data of Figure 9 is based on T
= 150°C; T is
J(pk)
C
BONDING WIRE LIMITED
THERMALLY LIMITED @ T = 25°C
ꢁ(SINGLE PULSE)
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided T
0.1
C
J(pk)
v 150°C. T
may be calculated from the data in
J(pk)
SECOND BREAKDOWN LIMITED
ꢁCURVES APPLY BELOW
ꢁRATED V
Figure 8. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
CEO
0.01
0.3
1
2
3
5
7
10
20 30
V
, COLLECTOR−EMITTER VOLTAGE (V)
CE
Figure 9. Active Region Safe Operating Area
200
T = 25°C
J
C
ib
100
70
50
C
ob
MJD200 (NPN)
MJD210 (PNP)
30
20
0.4 0.6
1
2
4
6
10
20
40
V , REVERSE VOLTAGE (V)
R
Figure 10. Capacitance
http://onsemi.com
5
MJD200 (NPN) MJD210 (PNP)
PACKAGE DIMENSIONS
DPAK
CASE 369C
ISSUE O
NOTES:
SEATING
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
PLANE
C
2. CONTROLLING DIMENSION: INCH.
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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MJD200/D
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