MM74HC175MTCX [ONSEMI]
带清零功能的四通道 D 型触发器;
| 型号： | MM74HC175MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 带清零功能的四通道 D 型触发器 触发器 |
| 文件： | 总7页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Quad D-Type Flip-Flop With
Clear
1
1
MM74HC175
SOIC−16
CASE 751B
TSSOP−16
CASE 948F
Description
The MM74HC175 high speed D−type flip−flop with
complementary outputs utilizes advanced silicon−gate CMOS
technology to achieve the high noise immunity and low power
consumption of standard CMOS integrated circuits, along with the
ability to drive 10 LS−TTL loads. Information at the D inputs of the
MM74HC175 is transferred to the Q and Q outputs on the positive
going edge of the clock pulse. Both true and complement outputs from
each flip flop are externally available. All four flip−flops are
controlled by a common clock and a common CLEAR. Clearing is
accomplished by a negative pulse at the CLEAR input. All four Q
outputs are cleared to a logical “0” and all four Q outputs to a logical
“1.” The 74HC logic family is functionally as well as pin−out
compatible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal diode
MARKING DIAGRAMS
16
1
16
HC
HC175A
AWLYWW
175A
ALYW
1
HC175A = Specific Device Code
A
L/WL
Y/YY
= Assembly Location
= Wafer Lot
= Year of Production, Last Number
W/WW = Work Week Number
CONNECTION DIAGRAM
clamps to V and ground.
CC
Features
• Typical Propagation Delay: 15 ns
• Wide Operating Supply Voltage Range: 2–6 V
• Low Input Current: 1 mA Maximum
• Low Quiescent Supply Current: 160 mA Maximum (74HC)
• High Output Drive Current: 4 mA Minimum (74HC)
• These are Pb−Free Devices
(Top View)
TRUTH TABLE
(Each Flip Flop)
Outputs
Inputs
Clock
D
X
H
Q
Q
H
L
Clear
L
L
H
H
X
↑
↑
H
L
H
L
Q
Q
H
0
L
0
X
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant
↑ = Transition from LOW−to−HIGH level
Q = The level of Q before the indicated
0
steady−state input conditions were established
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 4 of this data sheet.
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
November, 2022 − Rev. 1
MM74HC175/D
MM74HC175
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
CC
Supply Voltage
−0.5 to +7.0
V
IN
DC Input Voltage
−0.5 to V + 0.5
V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
−0.5 to V + 0.5
V
OUT
CC
I
, I
20
25
mA
mA
mA
°C
IK OK
I
OUT
I
DC V or GND Current, per Pin
50
CC
CC
T
STG
Storage Temperature Range
−65 to +150
P
D
Power Dissipation
(Note 2)
S. O. Package Only
mW
600
500
T
L
Lead Temperature (Soldering 10 seconds)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating − plastic “N” package: 12 mW/°C from 65°C to 85°C.
RECOMMENDED OPERATIONG CONDITIONS
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
Supply Voltage
6
V
IN
, V
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
0
V
CC
V
OUT
T
A
−55
+125
°C
ns
t , t
r
f
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
−
−
−
1000
500
400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 3)
T
A
= 25°C
T
A
−40°C to 85°C
T = −55°C to 125°C
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
Unit
V
IH
Minimum HIGH
Level Input Voltage
2.0
4.5
6.0
−
−
−
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
Maximum LOW
2.0
4.5
6.0
−
−
−
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
IL
Level Input Voltage
V
OH
Minimum HIGH
Level Output Voltage |I
V
OUT
= V or V
IH IL
IN
2.0
4.5
6.0
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
| ≤ 20 mA
V
= V or V
IL
| ≤ 4.0 mA
| ≤ 5.2 mA
V
V
IN
IH
4.5
6.0
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
|I
|I
OUT
OUT
V
OL
Maximum LOW
V
IN
= V or V
IH IL
| ≤ 20 mA
2.0
4.5
6.0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
Level Output Voltage |I
OUT
V
= V or V
IL
| ≤ 4.0 mA
| ≤ 5.2 mA
V
IN
IH
4.5
6.0
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
|I
|I
OUT
OUT
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2
MM74HC175
DC ELECTRICAL CHARACTERISTICS (Note 3) (continued)
T
A
= 25°C
T
A
−40°C to 85°C
T = −55°C to 125°C
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
= V or
Unit
I
IN
Maximum Input
Current
V
6.0
−
0.1
1.0
1.0
mA
IN
CC
GND
I
Maximum Quiescent
Supply Current
V
= V or
6.0
−
8
80
160
mA
CC
IN
CC
GND
I
= 0 mA
OUT
3. For a power supply of 5 V 10% the worst case output voltages (V , and V ) occur for HC at 4.5 V. Thus the 4.5 V values should be used
OH
OL
when designing with this supply. Worst case V and V occur at V = 5.5 V and 4.5 V respectively. (The V value at 5.5 V is 3.85 V.) The
IH
IL
CC
IH
worst case leakage current (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
IN CC
OZ
AC ELECTRICAL CHARACTERISTICS (V = 5 V, T = 25°C, CL = 15 pF, t = t = 6 ns)
CC
A
r
f
Symbol
Parameter
Maximum Operating Frequency
Conditions
Typ
60
15
13
−
Guaranteed Limit
Unit
MHz
ns
f
35
25
21
20
20
0
MAX
t
t
, t
Maximum Propagation Delay, Clock to Q or Q
Maximum Propagation Delay, Reset to Q or Q
Minimum Removal Time, Clear to Clock
Minimum Setup Time, Data to Clock
PHL PLH
, t
ns
PHL PLH
t
ns
REC
t
−
ns
S
H
t
Minimum Hold Time, Data from Clock
Minimum Pulse Width, Clock or Clear
−
ns
t
W
10
16
ns
AC ELECTRICAL CHARACTERISTICS (V = 2.0 V to 6.0 V, C = 50 pF, t = t = 6 ns unless otherwise specified)
CC
L
r
f
T
A
= 25°C
T
A
−40°C to 85°C
T = −55°C to 125°C
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
Unit
f
Maximum Operating
Frequency
2.0
4.5
6.0
12
60
70
6
30
35
5
24
28
4
20
24
MHz
MAX
t
t
, t
Maximum
Propagation Delay,
Clock to Q or Q
2.0
4.5
6.0
80
15
13
150
30
190
38
225
45
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
26
32
38
, t
Maximum
Propagation Delay,
Reset to Q or Q
2.0
4.5
6.0
64
14
12
125
25
21
158
32
27
186
37
32
PHL PLH
t
Minimum Removal
Time, Clear to Clock
2.0
4.5
6.0
−
−
−
100
20
17
125
25
21
150
30
25
REM
t
Minimum Setup
Time, Data to Clock
2.0
4.5
6.0
−
−
−
100
20
17
125
25
21
150
30
25
S
H
t
Minimum Hold Time,
Data from Clock
2.0
4.5
6.0
−
−
−
0
0
0
0
0
0
0
0
0
t
Minimum Pulse
Width, Clock or
Clear
2.0
4.5
6.0
30
9
8
80
16
14
100
20
17
120
24
20
W
t t
r, f
Maximum Input Rise
and Fall Time
2.0
4.5
6.0
−
−
−
1000
500
400
1000
500
400
1000
500
400
t
, t
Maximum Output
Rise and Fall Time
2.0
4.5
6.0
30
9
8
75
15
13
95
19
16
110
22
19
TLH THL
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3
MM74HC175
AC ELECTRICAL CHARACTERISTICS (V = 2.0 V to 6.0 V, C = 50 pF, t = t = 6 ns unless otherwise specified)
CC
L
r
f
T
A
= 25°C
T
A
−40°C to 85°C
T = −55°C to 125°C
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
Unit
C
Power Dissipation
Capacitance
(Note 4)
(per package)
150
−
−
pF
PD
−
−
−
−
−
−
−
−
C
Maximum Input
Capacitance
−
5
10
10
10
pF
IN
2
4. C determines the no load dynamic power consumption, P = C
V
f + I V , and the no load dynamic current consumption,
CC CC
PD
D
PD CC
I
= C
V
f + I
.
S
PD CC
CC
ORDERING INFORMATION
Device
†
Package
Shipping
MM74HC175M
MM74HC175MX
MM74HC175MTCX
48 Units / Tube
2500 / Tape & Reel
2500 Units / Tube
SOIC−16
(Pb−Free)
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
DATE 29 DEC 2006
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T B
STYLE 1:
STYLE 2:
STYLE 3:
STYLE 4:
PIN 1. COLLECTOR
2. BASE
3. EMITTER
4. NO CONNECTION
5. EMITTER
6. BASE
7. COLLECTOR
8. COLLECTOR
9. BASE
10. EMITTER
11. NO CONNECTION
12. EMITTER
13. BASE
PIN 1. CATHODE
2. ANODE
3. NO CONNECTION
4. CATHODE
5. CATHODE
6. NO CONNECTION
7. ANODE
8. CATHODE
9. CATHODE
10. ANODE
11. NO CONNECTION
12. CATHODE
13. CATHODE
14. NO CONNECTION
15. ANODE
PIN 1. COLLECTOR, DYE #1
2. BASE, #1
3. EMITTER, #1
4. COLLECTOR, #1
5. COLLECTOR, #2
6. BASE, #2
PIN 1. COLLECTOR, DYE #1
2. COLLECTOR, #1
3. COLLECTOR, #2
4. COLLECTOR, #2
5. COLLECTOR, #3
6. COLLECTOR, #3
7. COLLECTOR, #4
8. COLLECTOR, #4
9. BASE, #4
10. EMITTER, #4
11. BASE, #3
12. EMITTER, #3
13. BASE, #2
7. EMITTER, #2
8. COLLECTOR, #2
9. COLLECTOR, #3
10. BASE, #3
11. EMITTER, #3
12. COLLECTOR, #3
13. COLLECTOR, #4
14. BASE, #4
SOLDERING FOOTPRINT
14. COLLECTOR
15. EMITTER
16. COLLECTOR
14. EMITTER, #2
15. BASE, #1
16. EMITTER, #1
15. EMITTER, #4
16. COLLECTOR, #4
8X
6.40
16. CATHODE
16X
1.12
STYLE 5:
STYLE 6:
STYLE 7:
PIN 1. SOURCE N‐CH
PIN 1. DRAIN, DYE #1
2. DRAIN, #1
3. DRAIN, #2
4. DRAIN, #2
5. DRAIN, #3
6. DRAIN, #3
7. DRAIN, #4
8. DRAIN, #4
9. GATE, #4
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. CATHODE
9. ANODE
2. COMMON DRAIN (OUTPUT)
3. COMMON DRAIN (OUTPUT)
4. GATE P‐CH
5. COMMON DRAIN (OUTPUT)
6. COMMON DRAIN (OUTPUT)
7. COMMON DRAIN (OUTPUT)
8. SOURCE P‐CH
1
16
16X
0.58
9. SOURCE P‐CH
10. SOURCE, #4
11. GATE, #3
12. SOURCE, #3
13. GATE, #2
14. SOURCE, #2
15. GATE, #1
16. SOURCE, #1
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
15. ANODE
16. ANODE
10. COMMON DRAIN (OUTPUT)
11. COMMON DRAIN (OUTPUT)
12. COMMON DRAIN (OUTPUT)
13. GATE N‐CH
14. COMMON DRAIN (OUTPUT)
15. COMMON DRAIN (OUTPUT)
16. SOURCE N‐CH
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42566B
SOIC−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16
DATE 19 OCT 2006
1
SCALE 2:1
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
−V−
N
A
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
B
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
DETAIL E
H
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
16
XXXX
XXXX
ALYW
1
1
XXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
Y
W
= Year
= Work Week
0.65
PITCH
G or G = Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70247A
TSSOP−16
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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FAIRCHILD
MM74HC175M_NL
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16
FAIRCHILD
MM74HC175N_NL
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16
FAIRCHILD
MM74HC175SJX
D Flip-Flop, HC/UH Series, 1-Func, Positive Edge Triggered, 4-Bit, Complementary Output, CMOS, PDSO16, 5.30 MM, EIAJ TYPE2, SOP-16
FAIRCHILD
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