MM74HC240MTCX [ONSEMI]
反相八通道3态缓冲器;
| 型号： | MM74HC240MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 反相八通道3态缓冲器 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Inverting Octal 3-STATE
Buffer
SOIC−20 WB
CASE 751D−05
TSSOP−20 WB
CASE 948E
MM74HC240
General Description
MARKING DIAGRAMS
The MM74HC240 3−STATE buffer utilizes advanced silicon−gate
CMOS technology. It possesses high drive current outputs which
enable high speed operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power Schottky
devices, while retaining the advantage of CMOS circuitry, i.e., high
noise immunity and low power consumption. It has a fanout of 15
LS−TTL equivalent inputs.
20
1
20
HC
240A
ALYWG
G
HC240A
AWLYYWWG
1
The MM74HC240 is an inverting buffer and has two active LOW
enables (1G and 2G). Each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by
(SOIC−20 WB)
(TSSOP−20 WB)
HC240A = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
diodes to V and ground.
CC
L/WL
Y/YY
W/WW
G or G
Features
Typical Propagation Delay: 12 ns
3−STATE Outputs for Connection to System Buses
Wide Power Supply Range: 2–6 V
Low Quiescent Supply Current: 160 mA (74 Series)
Output Current: 6 mA
(Note: Microdot may be in either location)
CONNECTION DIAGRAM
V
2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
19 18 17 16 15 14 13 12 11
CC
These are Pb−Free Devices
20
2A4
2A3
2A2
1Y8
1Y7
1Y6
1Y5
2A1
2G
1
2
3
4
5
6
7
8
9
10
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
(Top View)
1A4
1A3
1A2
1Y4
1Y3
1Y2
TRUTH TABLE
1G
L
1A
L
1Y
H
H
Z
2G
L
2A
L
2Y
H
H
Z
L
H
L
L
H
L
V
CC
H
H
H
H
H
Z
H
Z
H = HIGH Level
L = LOW Level
Z = HIGH Impedance
1Y1
1A1
1G
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 4 of this data sheet.
Figure 1. Logic Diagram
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
November, 2022 − Rev. 1
MM74HC240/D
MM74HC240
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
CC
Supply Voltage
−0.5 to +7.0
V
IN
DC Input Voltage
−0.5 to V + 0.5
V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
−0.5 to V + 0.5
V
OUT
CC
I , I
IK OK
20
35
mA
mA
mA
C
I
OUT
I
DC VCC or GND Current, per Pin
Storage Temperature Range
70
CC
T
STG
−65 to +150
P
D
Power Dissipation
(Note 2)
S. O. Package Only
mW
600
500
T
L
Lead Temperature (Soldering 10 seconds)
260
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating − plastic “N” package: 12 mW/C from 65C to 85C.
RECOMMENDED OPERATIONG CONDITIONS (Note 1)
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
Supply Voltage
6
V
IN
, V
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
0
V
CC
V
OUT
T
A
−55
+125
C
ns
t , t
r
f
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
−
−
−
1000
500
400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (Note 3)
T
A
= 25C
−40C T 85C
−55C T 125C
A
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
Unit
V
IH
Minimum HIGH
Level Input Voltage
2.0
4.5
6.0
−
−
−
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
Maximum LOW
2.0
4.5
6.0
−
−
−
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
V
IL
Level Input Voltage
V
OH
Minimum HIGH
Level Output Voltage |I
V
OUT
= V or V
IH IL
2.0
4.5
6.0
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
IN
| 20 mA
V
IN
= V or V
IH IL
| 6.0 mA
| 7.8 mA
4.5
6.0
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
|I
|I
OUT
OUT
V
OL
Maximum LOW
Level Output Voltage |I
V
IN
= V or V
IH IL
| 20 mA
2.0
4.5
6.0
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OUT
V
= V or V
IL
| 6.0 mA
| 7.8 mA
V
IN
IH
4.5
6.0
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
|I
|I
OUT
OUT
I
IN
Maximum Input
Current
V
IN
= V or GND
6.0
−
0.1
1.0
1.0
mA
CC
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2
MM74HC240
DC ELECTRICAL CHARACTERISTICS (Note 3) (continued)
T
A
= 25C
−40C T 85C
−55C T 125C
A
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
= V or V
Unit
I
Maximum 3−STATE
Output Leakage
Current
V
V
6.0
−
0.5
5
10
mA
OZ
IN
IH
IL
= V or GND
OUT
CC
G = V , G = V
IH
IL
I
Maximum Quiescent
Supply Current
V
OUT
= V or GND
6.0
−
8.0
80
160
mA
CC
IN
CC
I
= 0 mA
3. For a power supply of 5 V 10% the worst case output voltages (V , and V ) occur for HC at 4.5 V. Thus the 4.5 V values should be used
OH
OL
when designing with this supply. Worst case V and V occur at V = 5.5 V and 4.5 V respectively. (The V value at 5.5 V is 3.85 V.) The
IH
IL
CC
IH
worst case leakage current (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
IN CC
OZ
AC ELECTRICAL CHARACTERISTICS
Guaranteed
Limit
Symbol
, t
Parameter
Conditions
C = 45 pF
Typ
12
Unit
ns
t
t
t
Maximum Propagation Delay
18
28
25
PHL PLH
L
, t
Maximum Enable Delay to Active Output
Maximum Disable Delay from Active Output
R = 1 kW, C = 45 pF
14
ns
PZH PZL
L
L
, t
R = 1 kW, C = 5 pF
13
ns
PHZ PLZ
L
L
AC ELECTRICAL CHARACTERISTICS (V = 2.0 V to 6.0 V, C = 50 pF, t = t = 6 ns (unless otherwise specified))
CC
L
r
f
T
A
= 25C
−40C T 85C
−55C T 125C
A
A
V
CC
Typ
Guaranteed Limits
(V)
Symbol
Parameter
Conditions
C = 50 pF
Unit
2.0
2.0
55
80
100
150
126
190
149
224
ns
ns
ns
ns
t
,
Maximum
Propagation Delay
PHL
L
t
C = 150 pF
PLH
L
C = 50 pF
4.5
4.5
12
22
20
30
25
38
30
45
L
C = 150 pF
L
C = 50 pF
6.0
6.0
11
28
17
26
21
32
25
38
L
C = 150 pF
L
t
,
Maximum Output
Enable Time
R = 1 kW
L
PZH
2.0
2.0
75
100
150
200
189
252
224
298
t
C = 50 pF
PZL
L
C = 150 pF
L
C = 50 pF
L
4.5
4.5
15
20
30
40
38
50
45
60
ns
ns
ns
L
C = 150 pF
C = 50 pF
6.0
6.0
13
17
26
34
32
43
38
51
L
C = 150 pF
L
t
,
Maximum Output
Disable Time
R = 1 kW
2.0
4.5
6.0
75
15
13
150
30
26
189
38
32
224
45
38
PHZ
L
t
C = 50 pF
PLZ
L
t
,
Maximum Output
Rise and Fall Time
2.0
4.5
6.0
−
−
−
60
12
10
75
15
13
90
18
15
ns
TLH
t
THL
C
Power Dissipation
Capacitance
(Note 4)
(per buffer)
pF
PD
G = V
G = V
−
−
12
50
−
−
−
−
−
−
IH
IL
C
Maximum Input
Capacitance
−
5
10
10
10
pF
pF
IN
C
OUT
Maximum Output
Capacitance
−
10
20
20
20
2
4. C determines the no load dynamic power consumption, P = C V
f + I V , and the no load dynamic current consumption,
CC CC
PD
D
PD
CC
I
= C V f + I
.
S
PD
CC
CC
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3
MM74HC240
ORDERING INFORMATION
Device
†
Package
Shipping
MM74HC240WM
MM74HC240WMX
MM74HC240MTCX
38 Units / Tube
SOIC−20 WB
(Pb−Free)
1000 Units / Tape & Reel
2500 Units / Tape & Reel
SOIC−20 WB
(Pb−Free)
TSSOP−20 WB
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X b
A
A1
b
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
c
D
E
e
A
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
20
SOLDERING FOOTPRINT*
20X
20X
0.52
1.30
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
20
11
10
1
XXXXX = Specific Device Code
11.00
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
WL
YY
WW
G
1.27
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42343B
SOIC−20 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
0.10 (0.004)
T U
V
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70169A
TSSOP−20 WB
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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