MM74HC373MTC [ONSEMI]
3 态八路 D 型锁存;
| 型号： | MM74HC373MTC |
| 厂家： | 
ONSEMI |
| 描述： | 3 态八路 D 型锁存 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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3-STATE Octal D-Type Latch
MM74HC373
SOIC−20 WB
CASE 751D−05
General Description
The MM74HC373 high speed octal D−type latches utilize advanced
silicon−gate CMOS technology. They possess the high noise
immunity and low power consumption of standard CMOS integrated
circuits, as well as the ability to drive 15 LS−TTL loads. Due
to the large output drive capability and the 3−STATE feature, these
devices are ideally suited for interfacing with bus lines in a bus
organized system.
SOIC−20, 300 mils
CASE 751BJ−01
When the LATCH ENABLE input is HIGH, the Q outputs will
follow the D inputs. When the LATCH ENABLE goes LOW, data
at the D inputs will be retained at the outputs until LATCH ENABLE
returns HIGH again. When a high logic level is applied
to the OUTPUT CONTROL input, all outputs go to a high impedance
state, regardless of what signals are present at the other inputs
and the state of the storage elements.
TSSOP−20 WB
CASE 948E
MARKING DIAGRAMS
SOIC−20
The 74HC logic family is speed, function, and pin−out compatible
with the standard 74LS logic family. All inputs are protected
20
HC373A
AWLYYWW
from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
1
• Typical Propagation Delay: 18 ns
• Wide Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 mA Maximum
• Low Quiescent Current: 160 mA Maximum (74 Series)
• Output Drive Capability: 15 LS−TTL Loads
• This is a Pb−Free Device
TSSOP−20
20
HC
373A
ALYW
1
LATCH
ENABLE
HC373A = Specific Device Code
V
8Q
19
7D
17
7Q
16
6Q
15
6D
14
5D
13
5Q
12
6
A
WL, L
Y
= Assembly Location
= Wafer Lot Number
= Year
8D
18
CC
20
11
WW, YW = Work Week
Q
D
G
D
G
Q
Q
D
G
D
G
Q
OE
OE
OE
OE
OE
OE
OE
OE
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
D
G
Q
2
D
G
Q
Q
6
D
G
D
G
Q
1
3
4
5
7
3D
8
9
10
GND
1Q
1D
2D
2Q
3Q
4D
4Q
OUTPUT
CONTROL
Pin Assignments for SOIC and TSSOP (Top View)
Figure 1. Connection Diagram
© Semiconductor Components Industries, LLC, 1983
1
Publication Order Number:
November, 2022 − Rev. 2
MM74HC373/D
MM74HC373
TRUTH TABLE
Output
Control
Latch
Enable
Data
H
373 Output
L
H
H
L
H
L
L
L
L
H
X
Q
0
X
X
Z
NOTES:
H
L
X
Q
= HIGH Level
= LOW Level
= Don’t Care
= Level of output before steady−state input conditions were
0
established.
= High Impedance
Z
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Rating
Value
Unit
V
V
CC
Supply Voltage
−0.5 to +7.0 V
V
IN
DC Input Voltage
−0.5 to V +0.5 V
V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per pin
−0.5 to V +0.5 V
V
OUT
CC
I , I
IK OK
20
35
mA
mA
mA
°C
I
OUT
I
DC V or GND Current, per pin
70
CC
CC
T
STG
Storage Temperature Range
Power Dissipation
−65 to +150
600
P
Note 2
mW
mW
°C
D
S. O. Package only
500
T
Lead Temperature (Soldering 10 seconds)
260
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating − plastic “N” package: 12 mW/°C from 65°C to 85°C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
Supply Voltage
6
V
IN
, V
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
0
V
CC
V
OUT
T
A
−55
−
+125
1000
500
°C
ns
ns
ns
t , t
r
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
f
−
−
400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MM74HC373
DC ELECTRICAL CHARACTERISTICS (Note 3)
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
125°C
Symbol
Parameter
Conditions
V
CC
Typ
Guaranteed Limits
Unit
V
IH
Minimum HIGH Level
Input Voltage
2.0 V
4.5 V
6.0 V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
V
IL
Maximum LOW Level
Input Voltage
2.0 V
4.5 V
6.0 V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
V
OH
Minimum HIGH Level
Output Voltage
V
= V or V
IL
⎪ ≤ 20 mA
2.0 V
4.5 V
6.0 V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
IN
IH
⎪I
OUT
V
⎪I
⎪I
= V or V
IH IL
IN
⎪ ≤ 6.0 mA
OUT
⎪ ≤ 7.8 mA
OUT
4.5 V
6.0 V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
V
OL
Maximum LOW Level
Output Voltage
V
= V or V
IL
⎪ ≤ 20 mA
2.0 V
4.5 V
6.0 V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
IN
IH
⎪I
OUT
V
⎪I
⎪I
= V or V
IH IL
IN
⎪ ≤ 6.0 mA
OUT
⎪ ≤ 7.8 mA
OUT
4.5 V
6.0 V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
I
IN
Maximum Input
Current
V
IN
= V or GND
6.0 V
0.1
1.0
1.0
mA
CC
I
Maximum 3−STATE
Output Leakage
Current
V
= V or V ,
6.0 V
0.5
5
10
mA
OZ
IN
IH
IL
OC = V
IH
V
OUT
= V or GND
CC
I
Maximum Quiescent
Supply Current
V
= V or GND
= 0 mA
6.0 V
8.0
80
160
mA
CC
IN
CC
I
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. For a power supply of 5 V 10% the worst case output voltages (V , and V ) occur for HC at 4.5 V. Thus the 4.5 V values should be used
OH
OL
when designing with this supply. Worst case V and V occur at V = 5.5 V and 4.5 V respectively. (The V value at 5.5 V is 3.85 V.) The
IH
IL
CC
IH
worst case leakage current (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
IN CC
OZ
AC ELECTRICAL CHARACTERISTICS
(V = 5 V, T = 25°C, t = t = 6 ns)
CC
A
r
f
Symbol
Parameter
Conditions
C = 45 pF
Typ
Guaranteed Limit
Unit
t
t
, t
Maximum Propagation Delay,
Data to Q
18
25
ns
PHL PLH
L
, t
Maximum Propagation Delay,
LE toQ
C = 45 pF
21
20
18
30
28
25
ns
ns
ns
PHL PLH
L
t
t
, t
Maximum Output Enable Time
R = 1 kW,
L
C = 45 pF
L
PZH PZL
, t
Maximum Output Disable Time
R = 1 kW,
L
PHZ PLZ
C = 5 pF
L
t
Minimum Set Up Time
Minimum Hold Time
Minimum Pulse Width
5
ns
ns
ns
s
t
H
10
16
t
W
9
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
MM74HC373
AC ELECTRICAL CHARACTERISTICS
(V = 2.0−6.0 V, C = 50 pF, t = t = 6 ns, unless otherwise specified)
CC
L
r
f
T
A
= 25°C
T
A
= −40 to
85°C
T
A
= −55 to
125°C
Symbol
Parameter
Conditions
C = 50 pF
V
Typ
Guaranteed Limits
Unit
CC
t
, t
Maximum Propagation
Delay, Data to Q
2.0 V
2.0 V
50
80
150
200
188
250
225
300
ns
ns
PHL PLH
L
C = 150 pF
L
C = 50 pF
C = 150 pF
L
4.5 V
4.5 V
22
30
30
40
37
50
45
60
ns
ns
L
C = 50 pF
C = 150 pF
L
6.0 V
6.0 V
19
26
26
35
31
44
39
53
ns
ns
L
t
, t
Maximum Propagation
Delay, LE to Q
C = 50 pF
C = 150 pF
L
2.0 V
2.0 V
63
110
175
225
220
280
263
338
ns
ns
PHL PLH
L
C = 50 pF
C = 150 pF
L
4.5 V
4.5 V
25
35
35
45
44
56
52
68
ns
ns
L
C = 50 pF
C = 150 pF
L
6.0 V
6.0 V
21
28
30
39
37
49
45
59
ns
ns
L
t
, t
Maximum Output
Enable Time
R = 1 kW
C = 50 pF
L
PZH PZL
L
2.0 V
2.0 V
50
80
150
200
188
250
225
300
ns
ns
C = 150 pF
L
C = 50 pF
C = 150 pF
L
4.5 V
4.5 V
21
30
30
40
37
50
45
60
ns
ns
L
C = 50 pF
C = 150 pF
L
6.0 V
6.0 V
19
26
26
35
31
44
39
53
ns
ns
L
t
, t
Maximum Output
Disable Time
R = 1 kW
C = 50 pF
L
2.0 V
4.5 V
6.0 V
50
21
19
150
30
26
188
37
31
225
45
39
ns
ns
ns
PHZ PLZ
L
t
Minimum Set Up Time
Minimum Hold Time
Minimum Pulse Width
2.0 V
4.5 V
6.0 V
−
−
−
50
9
9
60
13
11
75
15
13
ns
ns
ns
s
t
H
2.0 V
4.5 V
6.0 V
−
−
−
5
5
5
5
5
5
5
5
5
ns
ns
ns
t
W
2.0 V
4.5 V
6.0 V
30
10
9
80
16
14
100
20
18
120
24
20
ns
ns
ns
t
, t
Maximum Output Rise
and Fall Time
C = 50 pF
L
2.0 V
4.5 V
6.0 V
25
7
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
THL TLH
C
Power Dissipation
(per latch)
PD
Capacitance (Note 4)
OC = V
OC = GND
−
−
30
50
−
−
−
−
−
−
pF
pF
CC
C
Maximum Input
Capacitance
−
5
10
10
10
pF
IN
C
Maximum Output
Capacitance
−
15
20
20
20
pF
OUT
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
4. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
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4
MM74HC373
ORDERING INFORMATION
Device
†
Package
Shipping
MM74HC373WM
SOIC−20 WB
(Pb−Free and Halide Free)
38 Units / Tube
MM74HC373WMX
SOIC−20, 300 mils
(Pb−Free and Halide Free)
1000 / Tape & Reel
MM74HC373MTC
MM74HC373MTCX
TSSOP−20 WB
(Pb−Free)
75 Units / Tube
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20, 300 mils
CASE 751BJ−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
2.64
0.30
2.55
0.51
0.33
13.00
10.64
7.60
2.36
2.49
A
A1
A2
b
0.10
2.05
0.31
0.41
0.27
c
0.20
E1
E
D
12.60
10.01
7.40
12.80
10.30
7.50
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.75
1.27
8º
0.81
L
b
e
θ
5º
15º
θ1
PIN#1 IDENTIFICATION
TOP VIEW
D
h
h
q1
q
A2
A
q1
L
c
A1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34287E
SOIC−20, 300 MILS
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X b
A
A1
b
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
c
D
E
e
A
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
20
SOLDERING FOOTPRINT*
20X
20X
0.52
1.30
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
20
11
10
1
XXXXX = Specific Device Code
11.00
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
WL
YY
WW
G
1.27
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42343B
SOIC−20 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
0.10 (0.004)
T U
V
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70169A
TSSOP−20 WB
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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