MM74HC74AMX [ONSEMI]
双路 D 型触发器，带预置和清除;
| 型号： | MM74HC74AMX |
| 厂家： | 
ONSEMI |
| 描述： | 双路 D 型触发器，带预置和清除 PC 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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14
Dual D-Type Flip-Flop
with Preset and Clear
1
SOIC−14
CASE 751EF
MM74HC74A
The MM74HC74A utilizes advanced silicon−gate CMOS
technology to achieve operating speeds similar to the equivalent
LS−TTL part. It possesses the high noise immunity and low power
consumption of standard CMOS integrated circuits, along with the
ability to drive 10 LS−TTL loads.
14
1
TSSOP−14 WB
CASE 948G
This flip−flop has independent data, preset, clear, and clock inputs
and Q and Q outputs. The logic level present at the data input is
transferred to the output during the positive−going transition of the
clock pulse. Preset and clear are independent of the clock and
accomplished by a low level at the appropriate input.
MARKING DIAGRAM
14
HC74A
AWLYWW
The 74HC logic family is functionally and pinout compatible with
the standard 74LS logic family. All inputs are protected from damage
due to static discharge by internal diode clamps to V and ground.
CC
1
SOIC−14 NB
Features
• Typical Propagation Delay: 12 ns
14
• Wide Power Supply Range: 2 V – 6 V
• Low Quiescent Current: 80 mA maximum (74HC Series)
• Low Input Current: 1 mA Maximum
• Fanout of 10 LS−TTL Loads
HC
74A
ALYW
1
TSSOP−14 WB
• These Devices are Pb−Free, Halide Free and are RoHS Compliant
HC74A = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
= Year
WW, W = Work Week
Connection Diagram
Y
TRUTH TABLE
Inputs
Outputs
PR
L
CLR
CLK
X
D
X
X
X
Q
Q
L
H
L
L
H
L
H
X
H
L
X
H
H
(Note1) (Note1)
H
H
H
H
H
H
↑
↑
L
H
L
H
L
L
H
X
Q0
Q0
Q0 = the level of Q before the indicated input
conditions were established.
1. This configuration is nonstable; that is, it will
not persist when preset and clear inputs return
to their inactive (HIGH) level.
Figure 1. Pin Assignments for SOIC and TSSOP
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 1983
1
Publication Order Number:
November, 2022 − Rev. 2
MM74HC74A/D
MM74HC74A
Logic Diagram
Figure 2. Logic Diagram
Parameter
MAXIMUM RATINGS (Note 2)
Symbol
Rating
V
CC
Supply Voltage
–0.5 to +7.0 V
V
IN
DC Input Voltage
–0.5 to V + 0.5 V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5 V
OUT
CC
I , I
IK OK
20 mA
25 mA
I
OUT
I
DC V or GND Current, per Pin
50 mA
CC
CC
T
Storage Temperature Range
Power Dissipation
–65°C to +150°C
600 mW
STG
P
(Note 3)
S.O. Package Only
Lead Temperature (Soldering 10 Seconds)
D
500 mW
T
260°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Unless otherwise specified all voltages are referenced to ground.
3. Power Dissipation temperature derating − plastic “N” package: –12 mW/°C from 65°C to 85°C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2
Max
Unit
V
V
CC
Supply Voltage
6
V
, V
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
0
V
V
IN OUT
CC
T
A
–55
−
+125
1000
500
°C
ns
ns
ns
t , t
r
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
f
−
−
400
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MM74HC74A
DC CHARACTERISTICS (Note 4)
T
= −40°C
T = −55°C
A
A
to 85°C
to 125°C
T
A
= 25°C
Typ
−
Guaranteed Limits
Symbol
Parameter
V
CC
(V)
Conditions
Unit
V
IH
Minimum HIGH Level Input
Voltage
2.0
1.5
1.5
3.15
4.2
1.5
3.15
4.2
0.5
1.35
1.8
1.9
4.4
5.9
3.7
V
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
−
3.15
4.2
−
V
IL
Maximum LOW Level Input
Voltage
−
0.5
0.5
V
V
−
1.35
1.8
1.35
1.8
−
V
OH
Minimum HIGH Level Output
Voltage
V
|I
= V or V ,
2.0
4.5
6.0
4.3
1.9
1.9
IN
IH
IL
| ≤ 20 mA
OUT
4.4
4.4
5.9
5.9
V
IN
= V or V ,
3.98
3.84
IH
IL
|I
| ≤ 4.0 mA
OUT
6.0
V
OUT
= V or V ,
5.2
5.48
5.34
5.2
IN
IH
IL
|I
| ≤ 5.2 mA
V
OL
Maximum LOW Level Output
Voltage
2.0
4.5
6.0
4.5
V
|I
= V or V ,
OUT
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.4
V
IN
IH
IL
| ≤ 20 mA
0
0.1
0.1
V
= V or V ,
0.2
0.26
0.33
IN
IH
IL
|I
| ≤ 4.0 mA
OUT
6.0
V
OUT
= V or V ,
0.2
0.26
0.33
0.4
IN
IH
IL
|I
| ≤ 5.2 mA
I
Maximum Input Current
6.0
6.0
V
V
= V or GND
−
−
0.1
4.0
1.0
40
1.0
80
mA
mA
IN
IN
CC
I
Maximum Quiescent Supply
Current
= V or GND,
CC
= 0 mA
CC
IN
I
OUT
4. For a power supply of 5 V 10% the worst case output voltages (V , and V ) occur for HC at 4.5 V. Thus the 4.5 V values should be used
OH
OL
when designing with this supply. Worst case V and V occur at V = 5.5 V and 4.5 V respectively. (The V value at 5.5 V is 3.85 V.) The
IH
IL
CC
IH
worst case leakage current (I , I , and I ) occur for CMOS at the higher voltage and so the 6.0 V values should be used.
IN CC
OZ
AC CHARACTERISTICS (V = 5 V, T = 25°C, C = 15 pF, t = t = 6 ns)
CC
A
L
r
f
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
72
Unit
MHz
ns
f
Maximum Operating Frequency
30
30
MAX
t
t
, t
Maximum Propagation Delay,
Clock to Q or Q
10
PHL PLH
, t
Maximum Propagation Delay,
Preset or Clear to Q or Q
17
6
40
5
ns
ns
PHL PLH
t
Minimum Removal Time,
Preset or Clear to Clock
REM
t
Minimum Setup Time, Data to Clock
Minimum Hold Time, Clock to Data
10
0
20
0
ns
ns
ns
s
t
H
t
W
Minimum Pulse Width Clock, Preset or Clear
8
16
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3
MM74HC74A
AC CHARACTERISTICS (C = 50 pF, t = t = 6 ns (unless otherwise specified))
L
r
f
T
= −40°C
T = −55°C
A
A
to 85°C
to 125°C
T
A
= 25°C
Typ
22
72
94
34
12
10
66
20
16
20
6
Guaranteed Limits
Symbol
Parameter
V
CC
(V)
Conditions
Unit
f
Maximum Operating Frequency
2.0
6
5
24
28
140
28
24
190
38
33
65
13
11
100
20
17
0
4
20
24
165
33
28
225
45
38
75
15
13
120
24
20
0
ns
MAX
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
30
35
110
22
19
150
30
26
50
10
9
t
t
, t
Maximum Propagation Delay,
Clock to Q or Q
ns
ns
ns
ns
ns
ns
ns
ns
PHL PLH
, t
Maximum Propagation Delay,
Preset or Clear to Q or Q
PHL PLH
t
Minimum Removal Time,
Preset or Clear to Clock
REM
5
t
s
Minimum Setup Time,
Data to Clock
35
10
8
80
16
14
0
t
H
Minimum Hold Time,
Clock to Data
−
−
0
0
0
−
0
0
0
t
W
Minimum Pulse Width Clock,
Preset or Clear
30
9
80
16
14
75
15
13
1000
500
400
−
101
20
17
95
19
16
119
24
20
110
22
19
8
t
, t
Maximum Output Rise and Fall Time
Maximum Input Rise and Fall Time
25
7
TLH THL
6
t , t
−
1000
500
400
−
1000
500
400
−
r
f
−
−
C
PD
Power Dissipation Capacitance
(Note 5)
(per flip−flop)
80
pF
pF
C
IN
Maximum Input Capacitance
5
10
10
10
2
5. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
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4
MM74HC74A
ORDERING INFORMATION
Part Number
†
Package
Shipping
MM74HC74AM
SOIC−14, Case 751EF
(Pb−Free, Halide Free)
55 Units / Tube
96 Units / Tube
MM74HC74AMTC
MM74HC74AMX
MM74HC74AMTCX
TSSOP−14, Case 948G−01
(Pb−Free, Halide Free)
SOIC−14, Case 751EF
(Pb−Free, Halide Free)
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−14 WB, Case 948G−01
(Pb−Free, Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC14
CASE 751EF
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13739G
SOIC14
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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