MM74HCT05MTC [ONSEMI]
六路转换器（开路漏极）;
| 型号： | MM74HCT05MTC |
| 厂家： | 
ONSEMI |
| 描述： | 六路转换器（开路漏极） 栅 光电二极管 逻辑集成电路 触发器 转换器 |
| 文件： | 总7页 (文件大小：276K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Hex Inverter (Open Drain)
MM74HCT05
14
1
SOIC−14
CASE 751EF
General Description
The MM74HCT05 is a logic function fabricated by using advanced
silicon−gate CMOS technology, which provides the inherent benefits
of CMOS—low quiescent power and wide power supply range. The
device is also input and output characteristic and pinout compatible
with standard DM74LS logic families. The MM74HCT05 open drain
Hex Inverter requires the addition of an external resistor to perform a
wire−NOR function.
14
1
TSSOP−14 WB
CASE 948G
All inputs are protected from static discharge damage by internal
MARKING DIAGRAMS
diodes to V and ground.
CC
14
14
MM74HCT devices are intended to interface between TTL and
NMOS components and standard CMOS devices. These parts are also
plug−in replacements for LS−TTL devices and can be used to reduce
power consumption in existing designs.
XXX
XXX
XXXXX
AWLYWW
ALYW
1
1
SOIC−14
Features
TSSOP−14 WB
XXXXX = Specific Device Code
= Assembly Location
WL, L = Wafer Lot
= Year
• Open Drain for Wire−NOR Function
• LS−TTL Pinout and Threshold Compatible
• Fanout of 10 LS−TTL Loads
• Typical Propagation Delays:
A
Y
WW, W = Work Week
♦ t
♦ t
(with 1 kW Resistor) 10 ns
(with 1 kW Resistor) 12 ns
PZL
PLZ
LOGIC DIAGRAM
• These are Pb−Free Devices
Connection Diagram
TYPICAL APPLICATION
Top View
ORDERING INFORMATION
See detailed ordering and shipping information on page 4 of
this data sheet.
Figure 1. Connection Diagram
© Semiconductor Components Industries, LLC, 1984
1
Publication Order Number:
November, 2022 − Rev. 2
MM74HCT05/D
MM74HCT05
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Rating
V
CC
Supply Voltage
–0.5 to +7.0 V
V
IN
DC Input Voltage
–0.5 to V + 0.5 V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5 V
OUT
CC
I , I
IK OK
20 mA
25 mA
I
OUT
I
DC V or GND Current, per Pin
50 mA
CC
CC
T
Storage Temperature Range
Power Dissipation
–65°C to +150°C
600 mW
STG
P
Note 2
S.O. Package Only
Lead Temperature (Soldering 10 Seconds)
D
500 mW
T
260°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating − plastic “N” package: –12 mW/°C from 65°C to 85°C.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
Supply Voltage
5.5
V
IN
DC Input Voltage
V
CC
V
V
DC Output Voltage
0
5.5
+85
500
V
OUT
T
Operating Temperature Range
Input Rise or Fall Times
–40
−
°C
ns
A
t , t
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
MM74HCT05
DC ELECTRICAL CHARACTERISTICS
(V = 5 V 10% unless otherwise specified)
CC
T
= −40°C
A
to 85°C
T
A
= 25°C
Typ
−
Guaranteed Limits
Symbol
Parameter
Conditions
Unit
V
V
IH
Minimum HIGH Level Input Voltage
Maximum LOW Level Input Voltage
Maximum LOW Level Output Voltage
2.0
0.8
2.0
0.8
V
IL
−
V
V
OL
0
0.1
0.1
V
V
IN
= V or V , |I | ≤ 20 mA
IL OUT
IH
V
V
= V or V , |I
CC
| = 4.0 mA,
0.2
0.26
0.33
IN
IH
IL OUT
= 4.5 V
V
V
= V or V , |I
CC
| = 4.8 mA,
0.2
0.26
0.33
IN
IH
IL OUT
= 5.5 V
I
Maximum Input Current
V
IN
V
IN
V
IN
V
IN
V
CC
= V or GND, V or V
−
−
−
−
−
0.1
0.5
2.0
0.3
−
1.0
5.0
20
mA
mA
mA
mA
mA
IN
CC
IH
IL
I
Maximum HIGH Level Output Leakage Current
Maximum Quiescent Supply Current
= V or V , V
= V
LKG
IH
IL OUT CC
I
= V or GND, I
= 0 mA
CC
CC
OUT
= 2.4 V or 0.5 V (Note 3)
= 4.5 V−5.5 V, V = 5.5 V
0.4
10
I
Off State Current
OHZ
O
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This is measured per input with all other inputs held at V or ground.
CC
AC ELECTRICAL CHARACTERISTICS
(V = 5 V, T = 25°C, C = 15 pF, t = t = 6 ns unless otherwise specified)
CC
A
L
r
f
Symbol
Parameter
Conditions
R = 1 kW
Typ
8
Guaranteed Limit
Unit
ns
t
t
Maximum Propagation Delay
Maximum Propagation Delay
15
16
PZL
PLZ
L
R = 1 kW
L
9
ns
AC ELECTRICAL CHARACTERISTICS
(V = 5 V 10%, C = 50 pF, t = t = 6 ns unless otherwise specified)
CC
L
r
f
T
= −40°C
A
to 85°C
T
A
= 25°C
Typ
10
12
10
−
Guaranteed Limits
Symbol
Parameter
Conditions
R = 1 kW
Unit
ns
t
t
Maximum Propagation Delay
Maximum Propagation Delay
Maximum Output Fall Time
Power Dissipation Capacitance
Maximum Input Capacitance
22
20
15
20
5
28
25
19
−
PZL
PLZ
THL
L
R = 1 kW
L
ns
t
ns
C
PD
(per gate) R = ∞ (Note 4)
pF
pF
L
C
IN
−
10
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
4. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
I
= C
V
f + I
.
S
PD CC
CC
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3
MM74HCT05
ORDERING INFORMATION
Part Number
†
Package
Shipping
MM74HCT05M
SOIC−14, Case 751EF
(Pb−Free, Halide−Free)
1100 Units / Tube
MM74HCT05MX
SOIC−14, Case 751EF
(Pb−Free, Halide−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
MM74HCT05MTCX
TSSOP−14 WB, Case 948G
(Pb−Free, Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC14
CASE 751EF
ISSUE O
DATE 30 SEP 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13739G
SOIC14
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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