MM74HCT273MTC [ONSEMI]
八路 D 型触发器,带清除;型号: | MM74HCT273MTC |
厂家: | ONSEMI |
描述: | 八路 D 型触发器,带清除 光电二极管 逻辑集成电路 触发器 |
文件: | 总9页 (文件大小:253K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Octal D-Type Flip-Flop
with Clear
SOIC−20 WB
CASE 751D−05
MM74HCT273
General Description
The MM74HCT273 utilizes advanced silicon−gate CMOS
technology. It has an input threshold and output drive similar
to LS−TTL with the low standby power of CMOS.
These positive edge−triggered flip−flops have a common clock
and clear−independent Q outputs. Data on a D input, having
the specified set−up and hold time, is transferred to the corresponding
Q output on the positive−going transition of the clock pulse.
The asynchronous clear forces all outputs LOW when it is LOW.
All inputs to this device are protected from damage due
TSSOP−20 WB
CASE 948E
MARKING DIAGRAM
to electrostatic discharge by diodes to V and ground.
CC
20
MM74HCT devices are intended to interface TTL and NMOS
components to CMOS components. These parts can be used as plug−in
replacements to reduce system power consumption in existing
designs.
HCT273A
AWLYYWW
1
Features
SOIC−20
• Typical Propagation Delay: 18 ns
• Low Quiescent Current: 160 mA Maximum (74HCT Series)
• Fanout of 10 LS−TTL Loads
• This is a Pb−Free Device
20
HCT
273A
ALYW
Connection Diagram
1
TSSOP−20 WB
HCT273A = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
WL, L
YY, Y
WW, W
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
Top View
Figure 1. Pin Assignments for SOIC and TSSOP
© Semiconductor Components Industries, LLC, 1984
1
Publication Order Number:
November, 2022 − Rev. 2
MM74HCT273/D
MM74HCT273
TRUTH TABLE (Each Flip−Flop)
Inputs
Outputs
Clear
Clock
D
X
H
L
Q
L
L
H
H
H
X
↑
↑
L
H
L
X
Q0
NOTE:
H
L
X
↑
= HIGH Level (steady−state)
= LOW Level (steady−state)
= Don’t Care
= Transition from LOW−to−HIGH level
Q0 = The level of Q before the indicated steady−state input conditions were established.
Logic Diagram
Figure 2. Logic Diagram
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2
MM74HCT273
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Rating
V
CC
Supply Voltage
–0.5 to +7.0 V
V
IN
DC Input Voltage
–0.5 to V + 0.5 V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5 V
OUT
CC
I , I
IK OK
20 mA
25 mA
I
OUT
I
DC V or GND Current, per Pin
50 mA
CC
CC
T
Storage Temperature Range
Power Dissipation
–65°C to +150°C
500 mW
STG
P
S.O. Package only
D
T
L
Lead Temperature (Soldering 10 Seconds)
260°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
Supply Voltage
5.5
V , V
IN OUT
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
V
CC
V
T
A
−55
+125
500
°C
ns
t , t
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
MM74HCT273
DC ELECTRICAL CHARACTERISTICS (V = 5 V 10%, unless otherwise specified)
CC
T
= −40°C
T = −55°C
A
to 125°C
A
to 85°C
T
A
= 25°C
Typ
Guaranteed Limits
Symbol
Parameter
Conditions
Unit
V
Minimum HIGH Level Input
Voltage
−
2.0
0.8
− 0.1
2.0
2.0
0.8
V
IH
V
Maximum LOW Level Input
Voltage
−
0.8
V
V
IL
V
OH
Minimum HIGH Level Output
Voltage
V
= V or V
| = 20 mA
V
CC
V
CC
V
− 0.1
V
− 0.1
IN
IH
IL
CC
CC
|I
OUT
V
= V or V
| = 4.0 mA, V = 4.5 V
CC
4.2
5.2
0
3.98
4.98
0.1
3.84
3.7
V
V
IN
IH
IL
|I
OUT
V
IN
= V or V
IL
4.84
0.1
4.7
0.1
0.4
0.4
1.0
160
0.9
IH
|I
OUT
| = 4.8 mA, V = 5.5 V
CC
V
OL
Minimum LOW Level Voltage
V
IN
= V or V
V
IH
IL
|I
OUT
| = 20 mA
V
IN
= V or V
0.2
0.2
−
0.26
0.26
0.1
0.33
0.33
1.0
V
IH
IL
|I
OUT
| = 4.0 mA, V = 4.5 V
CC
V
IN
= V or V
IL
V
IH
|I
OUT
| = 4.8 mA, V = 5.5 V
CC
I
IN
Maximum Input Current
V
V
= V or GND,
mA
mA
mA
IN
CC
or V
IH
IL
I
Maximum Quiescent Supply
Current
V
IN
= V or GND,
−
8
80
CC
CC
I
= 0 mA
OUT
V
IN
= 2.4 V or 0.5 V
−
0.6
0.8
(Note 2)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Measured per pin, all other inputs held at V or GND.
CC
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4
MM74HCT273
AC ELECTRICAL CHARACTERISTICS (V = 5 V, T = 25°C, C = 15 pF, t = t = 6 ns)
CC
A
L
r
f
Symbol
Parameter
Conditions
Typ
68
18
21
−1
6
Guaranteed Limit
Unit
MHz
ns
f
Maximum Operating Frequency
30
30
30
5
MAX
t
t
, t
Maximum Propagation Delay from Clock to Q
Maximum Propagation Delay from Clear to Q
Minimum Removal Time, Clear to Clock
Minimum Set−Up Time D to Clock
PHL PLH
, t
ns
PHL PLH
t
ns
REM
t
S
20
5
ns
t
H
Minimum Hold Time Clock to D
−3
10
ns
t
W
Minimum Pulse Width Clock or Clear
16
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS (V = 5.0 V 10%, C = 50 pF, t = t = 6 ns (unless otherwise specified))
CC
L
r
f
T
= −40°C
T = −55°C
A
to 125°C
A
to 85°C
T
A
= 25°C
Typ
68
Guaranteed Limits
Symbol
Parameter
Conditions
Unit
MHz
ns
f
Maximum Operating Frequency
27
37
21
46
18
56
MAX
t
t
, t
Maximum Propagation
Delay from Clock to Q
22
PHL PLH
, t
Maximum Propagation
Delay from Clear to Q
25
35
44
52
ns
PHL PLH
t
Minimum Removal Time Clear to Clock
Minimum Set−Up Time D to Clock
Minimum Hold Time Clock to D
−1
6
5
20
5
6
25
5
7
30
5
ns
ns
ns
ns
ns
ns
pF
pF
REM
t
S
H
t
−3
10
−
t
W
Minimum Pulse Width Clock or Clear
Maximum Input Rise and Fall Time, Clock
Maximum Output Rise and Fall Time
Power Dissipation Capacitance (Note 3)
Maximum Input Capacitance
16
500
15
−
25
30
t , t
500
19
−
500
22
−
r
f
t
, t
11
50
6
THL TLH
C
(Per Flip−Flop)
PD
C
10
10
10
IN
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
3. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
2
I
= C
V
f + I
.
S
PD CC
CC
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5
MM74HCT273
ORDERING INFORMATION
Part Number
†
Package
Shipping
MM74HCT273WM
SOIC−20 WB, Case 751D−05
(Pb−Free and Halide−Free)
38 Units / Tube
1000 Units / Tape & Reel
75 Units / Tube
MM74HCT273WMX
MM74HCT273MTC
MM74HCT273MTCX
TSSOP−20 WB, Case 948E
(Pb−Free)
2500 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X b
A
A1
b
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
c
D
E
e
A
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
20
SOLDERING FOOTPRINT*
20X
20X
0.52
1.30
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
20
11
10
1
XXXXX = Specific Device Code
11.00
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
WL
YY
WW
G
1.27
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42343B
SOIC−20 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
0.10 (0.004)
T U
V
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70169A
TSSOP−20 WB
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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