MM74HCT373WM [ONSEMI]
3态八路D型锁存器;
| 型号： | MM74HCT373WM |
| 厂家： | 
ONSEMI |
| 描述： | 3态八路D型锁存器 驱动 光电二极管 逻辑集成电路 锁存器 |
| 文件： | 总12页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
3-STATE Octal D-Type Latch /
3-STATE Octal D-Type Flip-Flop
SOIC−20 WB
CASE 751D−05
MM74HCT373/MM74HCT374
General Description
The MM74HCT373 octal D−type latches and MM74HCT374 Octal
D−type flip flops advanced silicon−gate CMOS technology, which
provides the inherent benefits of low power consumption and wide
power supply range, but are LS−TTL input and output characteristic
& pin−out compatible. The 3−STATE outputs are capable of driving
15 LSTTL loads. All inputs are protected from damage due to static
discharge by internal diodes to VCC and ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the outputs until
LATCH ENABLE returns HIGH again. When a high logic level is
applied to the OUTPUT CONTROL input, all outputs go to a high
impedance state, regardless of what signals are present at the other
inputs and the state of the storage elements.
SOIC−20, 300 mils
CASE 751BJ−01
TSSOP20, 4.4x6.5
CASE 948AQ−01
TSSOP−20 WB
CASE 948E
The MM74HCT374 are positive edge triggered flip−flops. Data
at the D inputs, meeting the setup and hold time requirements, are
transferred to the Q outputs on positive going transitions
of the CLOCK (CK) input. When a high logic level is applied
to the OUTPUT CONTROL (OC) input, all outputs go to a high
impedance state, regardless of what signals are present at the other
inputs and the state of the storage elements.
MARKING DIAGRAMS
20
HCT37xA
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS devices. These
parts are also plug in replacements for LS−TTL devices and can be
used to reduce power consumption in existing designs.
AWLYYWW
1
SOIC−20
Features
20
• TTL Input Characteristic Compatible
• Typical Propagation Delay: 20 ns
• Low Input Current: 1 mA Maximum
• Low Quiescent Current: 160 mA Maximum
• Compatible with Bus−oriented Systems
• Output Drive Capability: 15 LS−TTL Loads
• These are Pb−Free Devices
HCT
37xA
ALYW
1
TSSOP−20 WB
HCT37xA = Specific Device Code
x = 3 or 4
A
= Assembly Location
= Wafer Lot
= Year
WL, L
YY, Y
WW, W
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 1984
1
Publication Order Number:
November, 2022 − Rev. 2
MM74HCT373/D
MM74HCT373/MM74HCT374
Connection Diagrams
MM74HCT373
(Top View)
MM74HCT374
(Top View)
Figure 1. Pin Assignments for SOIC and TSSOP
Truth Tables
MM74HCT373
MM74HCT374
Output Control
LE
H
H
L
Data
H
373 Output
Output Control
Clock
Data
H
374 Output
L
L
H
L
L
L
↑
↑
L
H
L
L
L
L
X
Q
L
X
Q
0
0
H
X
X
Z
H
X
X
Z
NOTES: H = HIGH Level
NOTES: H = HIGH Level
L
Q
= LOW Level
L
= LOW Level
= Don’t Care
= Transition from LOW−to−HIGH
= High Impedance State
= The level of the output before steady state input
conditions were established.
= Level of output before steady−state input
conditions were established.
= High Impedance
X
↑
Z
Q
0
Z
0
Logic Diagrams
MM74HCT373
MM74HCT374
Figure 2. Logic Diagrams
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2
MM74HCT373/MM74HCT374
ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Rating
V
CC
Supply Voltage
–0.5 to +7.0 V
V
IN
DC Input Voltage
–0.5 to V + 0.5 V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5 V
OUT
CC
I , I
IK OK
20 mA
35 mA
I
OUT
I
DC V or GND Current, per Pin
70 mA
CC
CC
T
Storage Temperature Range
Power Dissipation
–65°C to +150°C
500 mW
STG
P
S.O. Package only
D
T
L
Lead Temperature (Soldering 10 Seconds)
260°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Unless otherwise specified all voltages are referenced to ground.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
Supply Voltage
5.5
V , V
IN OUT
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
V
CC
V
T
A
–55
+125
500
°C
ns
t , t
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
MM74HCT373/MM74HCT374
DC ELECTRICAL CHARACTERISTICS (V = 5 V 10%, unless otherwise specified)
CC
T
= −40°C
T = −55°C
A
to 125°C
A
to 85°C
T
A
= 25°C
Typ
Guaranteed Limits
Symbol
Parameter
Conditions
Unit
V
Minimum HIGH Level Input
Voltage
−
2.0
0.8
− 0.1
2.0
2.0
0.8
V
IH
V
Maximum LOW Level Input
Voltage
−
0.8
V
V
IL
V
OH
Minimum HIGH Level Output
Voltage
V
= V or V
| = 20 mA
V
CC
V
CC
V
− 0.1
V
− 0.1
IN
IH
IL
CC
CC
|I
OUT
V
= V or V
| = 6.0 mA, V = 4.5 V
CC
4.2
5.7
0
3.98
4.98
0.1
3.84
3.7
V
V
IN
IH
IL
|I
OUT
V
IN
= V or V
IL
4.84
0.1
4.7
0.1
0.4
0.4
1.0
10
IH
|I
OUT
| = 7.2 mA, V = 5.5 V
CC
V
OL
Maximum LOW Level Voltage
V
IN
= V or V
V
IH
IL
|I
OUT
| = 20 mA
V
IN
= V or V
0.2
0.2
−
0.26
0.26
0.1
0.33
0.33
1.0
V
IH
IL
|I
OUT
| = 6.0 mA, V = 4.5 V
CC
V
IN
= V or V
IL
V
IH
|I
OUT
| = 7.2 mA, V = 5.5 V
CC
I
IN
Maximum Input Current
V
V
= V or GND,
mA
mA
mA
mA
IN
CC
or V
IH
IL
I
I
Maximum 3−STATE
V
OUT
= V or GND,
−
0.5
5.0
OZ
CC
Output Leakage Current
Enable = V or V
IH
IL
Maximum Quiescent Supply
Current
V
IN
= V or GND,
−
8.0
80
160
1.5
CC
CC
I
= 0 mA
OUT
V
IN
= 2.4 V or 0.5 V
−
1.0
1.3
(Note 2)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Measured per pin. All others tied to V or ground.
CC
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4
MM74HCT373/MM74HCT374
AC ELECTRICAL CHARACTERISTICS
(MM74HCT373: V = 5.0 V, T = 25°C, t = t = 6 ns, unless otherwise specified)
CC
A
r
f
Symbol
, t
Parameter
Conditions
C = 45 pF
Typ
Guaranteed Limit
Unit
t
t
Maximum Propagation Delay
Data to Output
18
25
ns
PHL PLH
L
, t
Maximum Propagation Delay
Latch Enable to Output
C = 45 pF
L
21
20
18
30
28
25
ns
ns
ns
PHL PLH
t
t
, t
Maximum Enable Propagation Delay
Control to Output
C = 45 pF
L
PZH PZL
R = 1 kW
L
, t
Maximum Disable Propagation Delay
Control to Output
C = 5 pF
L
PHZ PLZ
R = 1 kW
L
t
Minimum Clock Pulse Width
−
−
−
16
5
ns
ns
ns
W
t
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
S
t
10
H
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS
(MM74HCT373: V = 5.0 V 10%, t = t = 6 ns, unless otherwise specified)
CC
r
f
T
= −40°C
T = −55°C
A
to 125°C
A
to 85°C
T
A
= 25°C
Typ
22
30
25
32
21
Guaranteed Limits
Symbol
, t
Parameter
Conditions
C = 50 pF
Unit
ns
t
t
Maximum Propagation
Delay Data to Output
30
40
35
45
30
37
50
44
56
37
45
60
53
68
45
PHL PLH
L
C = 150 pF
L
ns
, t
Maximum Propagation
Delay Latch Enable to Output
C = 50 pF
L
ns
PHL PLH
C = 150 pF
L
ns
t
, t
Maximum Enable Propagation Delay
Control to Output
C = 50 pF
ns
PZH PZL
L
R = 1 kW
L
C = 150 pF
L
30
21
40
30
50
37
60
45
ns
ns
L
R = 1 kW
t
, t
Maximum Disable Propagation Delay
Control to Output
C = 50 pF
L
PHZ PLZ
R = 1 kW
L
t
, t
Maximum Output Rise and Fall Time
Minimum Clock Pulse Width
C = 50 pF
8
−
−
−
−
−
−
−
12
16
5
15
20
6
18
24
8
ns
ns
ns
ns
pF
pF
pF
pF
THL TLH
L
t
W
t
S
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
t
H
10
10
20
5
13
10
20
−
20
10
20
−
C
IN
C
Maximum Output Capacitance
OUT
C
PD
Power Dissipation Capacitance (Note 3)
OC = V
CC
OC = GND
52
−
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
3. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
2
I
= C
V
f + I
.
S
PD CC
CC
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5
MM74HCT373/MM74HCT374
AC ELECTRICAL CHARACTERISTICS
(MM74HCT374: V = 5.0 V, T = 25°C, t = t = 6 ns, unless otherwise specified)
CC
A
r
f
Symbol
Parameter
Conditions
Typ
50
Guaranteed Limit
Unit
MHz
ns
f
Maximum Clock Frequency
30
32
MAX
t
, t
Maximum Propagation Delay
Data to Output
C = 45 pF
20
PHL PLH
L
t
t
, t
Maximum Enable Propagation Delay
Control to Output
C = 45 pF
L
19
17
28
25
ns
ns
PZH PZL
L
R = 1 kW
, t
Maximum Disable Propagation Delay
Control to Output
C = 5 pF
L
PHZ PLZ
R = 1 kW
L
t
Minimum Clock Pulse Width
−
−
−
20
5
ns
ns
ns
W
t
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
S
t
16
H
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS
(MM74HCT374: V = 5.0 V 10%, t = t = 6 ns, unless otherwise specified)
CC
r
f
T
= −40°C
T = −55°C
A
to 125°C
A
to 85°C
T
A
= 25°C
Typ
−
Guaranteed Limits
Symbol
Parameter
Conditions
Unit
MHz
ns
f
Minimum Clock Pulse Width
30
36
46
30
24
45
57
37
20
48
69
45
MAX
t
, t
Maximum Propagation Delay to Output
C = 50 pF
22
30
21
PHL PLH
L
C = 150 pF
ns
L
t
, t
Maximum Enable Propagation Delay
Control to Output
C = 50 pF
R = 1 kW
ns
PZH PZL
L
L
C = 150 pF
L
30
21
40
30
50
37
60
45
ns
ns
L
R = 1 kW
t
, t
Maximum Disable Propagation Delay
Control to Output
C = 50 pF
L
PHZ PLZ
R = 1 kW
L
t
, t
Maximum Output Rise and Fall Time
Minimum Clock Pulse Width
C = 50 pF
8
−
−
−
−
−
−
−
12
16
20
5
15
20
25
5
18
24
30
5
ns
ns
ns
ns
pF
pF
pF
pF
THL TLH
L
t
W
t
S
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
t
H
C
IN
10
20
5
10
20
−
10
20
−
C
Maximum Output Capacitance
OUT
C
PD
Power Dissipation Capacitance (Note 4)
OC = V
CC
OC = GND
58
−
−
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
4. C determines the no load dynamic power consumption, P = C
V
f + I
V
, and the no load dynamic current consumption,
PD
D
PD CC
CC CC
2
I
= C
V
f + I
.
S
PD CC
CC
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6
MM74HCT373/MM74HCT374
ORDERING INFORMATION
Part Number
†
Package
Shipping
MM74HCT373WMX
SOIC−20, Case 751BJ
1000 Units / Tape & Reel
2500 Units / Tape & Reel
(Pb−Free and Halide−Free)
MM74HCT373MTCX
TSSOP−20 WB, Case 948E
(Pb−Free)
MM74HCT374WM
MM74HCT374WMX
MM74HCT374MTCX
SOIC−20 WB, Case 751D−05
(Pb−Free and Halide−Free)
38 Units / Tube
1000 Units / Tape & Reel
2500 Units / Tape & Reel
TSSOP20, Case 948AQ−01
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20, 300 mils
CASE 751BJ−01
ISSUE O
DATE 19 DEC 2008
SYMBOL
MIN
NOM
MAX
2.64
0.30
2.55
0.51
0.33
13.00
10.64
7.60
2.36
2.49
A
A1
A2
b
0.10
2.05
0.31
0.41
0.27
c
0.20
E1
E
D
12.60
10.01
7.40
12.80
10.30
7.50
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.75
1.27
8º
0.81
L
b
e
θ
5º
15º
θ1
PIN#1 IDENTIFICATION
TOP VIEW
D
h
h
q1
q
A2
A
q1
L
c
A1
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34287E
SOIC−20, 300 MILS
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE H
DATE 22 APR 2015
SCALE 1:1
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
20X b
A
A1
b
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
B
T
0.25
A
c
D
E
e
A
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
SEATING
PLANE
L
18X e
q
_
_
A1
c
T
GENERIC
MARKING DIAGRAM*
RECOMMENDED
20
SOLDERING FOOTPRINT*
20X
20X
0.52
1.30
XXXXXXXXXXX
XXXXXXXXXXX
AWLYYWWG
20
11
10
1
XXXXX = Specific Device Code
11.00
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1
WL
YY
WW
G
1.27
PITCH
DIMENSIONS: MILLIMETERS
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42343B
SOIC−20 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
0.10 (0.004)
T U
V
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70169A
TSSOP−20 WB
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP20, 4.4x6.5
CASE 948AQ−01
ISSUE A
DATE 19 MAR 2009
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
6.60
6.50
4.50
0.05
0.80
0.19
0.09
6.40
6.30
4.30
E1
E
c
D
6.50
6.40
E
E1
e
4.40
0.65 BSC
0.60
L
0.45
0.75
L1
1.00 REF
0º
8º
θ
e
TOP VIEW
D
c
A2
A
θ1
L
A1
L1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34453E
TSSOP20, 4.4X6.5
PAGE 1 OF 1
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