MM74HCT74MTCX [ONSEMI]
双路 D 类触发器，带预设和清除输入;
| 型号： | MM74HCT74MTCX |
| 厂家： | 
ONSEMI |
| 描述： | 双路 D 类触发器，带预设和清除输入 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Dual D-Type Flip-Flop with
Preset and Clear
14
1
SOIC−14 NB
CASE 751A−03
MM74HCT74
14
General Description
1
The MM74HCT74 utilizes advanced silicon−gate CMOS
technology to achieve operation speeds similar to the equivalent
LS−TTL part. It possesses the high noise immunity and low power
consumption of standard CMOS integrated circuits, along with the
ability to drive 10 LS−TTL loads.
TSSOP−14 WB
CASE 948G
This flip−flop has independent data, preset, clear, and clock inputs
and Q and Q outputs. The logic level present at the data input is
transferred to the output during the positive−going transition of the
clock pulse. Preset and clear are independent of the clock and
accomplished by a low level at the appropriate input.
MARKING DIAGRAM
14
HCT74A
AWLYWW
The 74HCT logic family is functionally and pin−out compatible
with the standard 74LS logic family. All inputs are protected from
damage due to static discharge by internal diode clamps to VCC and
ground.
1
SOIC−14 NB
14
MM74HCT devices are intended to interface between TTL and
NMOS components and standard CMOS devices. These parts are also
plug−in replacements for LS−TTL devices and can be used to reduce
power consumption in existing designs.
HCT
74A
ALYW
1
TSSOP−14
Features
HCT74A = Specific Device Code
• Typical Propagation Delay: 18 ns
• Low Quiescent Current: 80 mA Maximum (74HCT Series)
• Low Input Current: 1 mA Maximum
• Fanout of 10 LS−TTL Loads
A
WL, L
Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
• Meta−stable Hardened
• These Devices are Pb−Free, Halide Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
Connection Diagram
Top View
Figure 3. Pin Assignments for SOIC and TSSOP
© Semiconductor Components Industries, LLC, 1984
4
Publication Order Number:
November, 2022 − Rev. 2
MM74HCT74D
MM74HCT74
TRUTH TABLE
Inputs
Outputs
PR
L
CLR
H
CLK
X
D
Q
Q
X
X
X
H
L
H
L
H
L
L
X
L
H
L
X
H (Note 4)
H (Note 4)
H
H
H
H
↑
H
L
L
H
H
↑
H
L
X
Q0
Q0
Q0 = the level of Q before the indicated input conditions were established.
4. This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (HIGH) level.
Logic Diagram
Figure 4. Logic Diagram
ABSOLUTE MAXIMUM RATINGS (Note 5)
Symbol
Parameter
Rating
V
CC
Supply Voltage
–0.5 to +7.0 V
V
IN
DC Input Voltage
–0.5 to V + 0.5 V
CC
V
DC Output Voltage
Clamp Diode Current
DC Output Current, per Pin
–0.5 to V + 0.5 V
OUT
CC
I , I
IK OK
20 mA
25 mA
I
OUT
I
DC V or GND Current, per Pin
50 mA
CC
CC
T
Storage Temperature Range
Power Dissipation
–65°C to +150°C
500 mW
STG
P
S.O. Package Only
D
T
L
Lead Temperature (Soldering 10 Seconds)
260°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. Unless otherwise specified all voltages are referenced to ground.
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5
MM74HCT74
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
Supply Voltage
5.5
V , V
IN OUT
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
V
CC
V
T
A
–55
−
+125
500
°C
ns
t , t
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS (V = 5 V 10% (unless otherwise specified))
CC
T
= −40°C T = −55°C
A
A
to 85°C
to 125°C
T
A
= 25°C
Typ
Guaranteed Limits
Symbol
Parameter
Conditions
Unit
V
V
IH
Minimum HIGH Level Input Voltage
Maximum LOW Level Input Voltage
Minimum HIGH Level Output Voltage
2.0
0.8
2.0
0.8
2.0
0.8
V
IL
V
V
OH
VCC
V
– 0.1
V
CC
– 0.1
V – 0.1
CC
V
V
IN
= V or V , |I
| = 20 mA
IH
IL OUT
CC
V
V
= V or V , |I
| = 4.0 mA, 4.2
3.98
3.84
3.7
IN
IH
IL OUT
= 4.5 V
CC
V
V
= V or V , |I
| = 4.8 mA, 5.2
4.98
4.84
4.7
IN
IH
IL OUT
= 5.5 V
CC
V
OL
Maximum LOW Level Voltage
0
0.1
0.1
0.1
0.4
V
V
= V or V , |I
| = 20 mA
IN
IH
IL OUT
V
V
= V or V , |I
| = 4.0 mA, 0.2
0.26
0.33
IN
CC
IH
IL OUT
= 4.5 V
V
V
= V or V , |I
| = 4.8 mA, 0.2
0.26
0.33
0.4
IN
IH
IL OUT
= 5.5 V
CC
I
Maximum Input Current
V
IN
V
IN
V
IN
= V or GND, V or V
−
−
−
0.5
2.0
0.3
0.5
20
1.0
80
mA
mA
IN
CC
IH
IL
I
Maximum Quiescent Supply Current
= V or GND, I
= 0 mA
CC
CC
OUT
= 2.4 V or 0.5 V (Note 6)
0.4
0.5
mA
6. This is measured per input with all other inputs held at V or ground.
CC
AC CHARACTERISTICS (V = 5.0 V, t = t = 6 ns, C = 15 pF, T = 25°C (unless otherwise noted))
CC
r
f
L
A
Symbol
Parameter
Conditions
Typ
50
18
18
−
Guaranteed Limit Unit
f
Maximum Operating Frequency from Clock to Q or Q
Maximum Propagation Delay Clock to Q or Q
30
30
30
20
20
0
MHz
ns
MAX
t
t
, t
PHL PLH
, t
Maximum Propagation Delay from Preset or Clear to Q or Q
Minimum Removal Time, Preset or Clear to Clock
Minimum Setup Time Data to Clock
ns
PHL PLH
t
ns
REM
t
−
ns
S
H
t
Minimum Hold Time Clock to Data
–3
8
ns
t
W
Minimum Pulse Width Clock, Preset or Clear
16
ns
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6
MM74HCT74
AC CHARACTERISTICS (V = 5.0 V 10%, C = 50 pF, t = t = 6 ns (unless otherwise noted))
CC
L
r
f
T
A
= 25°C
T = −40°C to 85°C
A
Typ
−
Guaranteed Limits
Symbol
Parameter
Maximum Operating Frequency
Maximum Propagation Delay from Clock to Q or Q
Conditions
Unit
MHz
ns
fMAX
27
21
44
44
t
t
, t
21
21
35
35
PHL PLH
, t
Maximum Propagation Delay from Preset or Clear to Q or
Q
ns
PHL PLH
t
Minimum Removal Time Preset or Clear to Clock
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
−
−
20
20
0
25
25
0
ns
ns
ns
ns
ns
ns
pF
pF
REM
t
S
H
t
–3
9
t
W
Minimum Pulse Width Clock, Preset or Clear
Maximum Clock Input Rise and Fall Time
Maximum Output Rise and Fall Time
Power Dissipation Capacitance (Note 7)
Maximum Input Capacitance
16
20
t , t
−
500
15
−
500
19
−
r
f
t
,
−
THL tTLH
C
(per flip−fl op)
10
5
PD
IN
C
10
10
IN
2
7. C determines the no load dynamic power consumption, P = C
V
f + I V , and the no load dynamic current consumption,
CC CC
PD
D
PD CC
I
S
= C
V
f + I
.
PD CC
CC
ORDERING INFORMATION
Part Number
†
Package
Shipping
MM74HCT74M
SOIC−14, Case 751A−03
(Pb−Free, Halide−Free)
55 Units / Tube
MM74HCT74MX
SOIC−14, Case 751A−03
(Pb−Free, Halide−Free)
2500 Units / Tape & Reel
2500 Units / Tape & Reel
MM74HCT74MTCX
TSSOP−14, Case 948G−01
(Pb−Free, Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70246A
TSSOP−14 WB
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
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and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
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