MMBT3640LT1_技术文档

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MMBT3640LT1

Switching Transistor

PNP Silicon

MAXIMUM RATINGS

Rating

Symbol

Value

−12

Unit

Vdc

Collector−Emitter Voltage

Collector−Base Voltage

Emitter−Base Voltage

V

CEO

V

CBO

V

EBO

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−12

Vdc

−4.0

−80

Vdc

3

Collector Current — Continuous

THERMAL CHARACTERISTICS

Characteristic

I

C

mAdc

1

2

Symbol

Max

Unit

Total Device Dissipation FR−5

Board

P

225

mW

D

CASE 318−08, STYLE 6

SOT−23 (TO−236AB)

(1)

T = 25°C

1.8

556

300

mW/°C

°C/W

mW

A

Derate above 25°C

Thermal Resistance,

Junction−to−Ambient

R

q

JA

COLLECTOR

3

Total Device Dissipation

P

D

(2)

Alumina Substrate, T = 25°C

A

1

Derate above 25°C

2.4

mW/°C

°C/W

BASE

Thermal Resistance, Junction to

Ambient

R

417

q

JA

2

Junction and Storage Temperature

DEVICE MARKING

T , T

−55 to +150

°C

J

stg

EMITTER

MMBT3640LT1 = 2J

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)

A

Characteristic

Symbol

Min

Max

Unit

OFF CHARACTERISTICS

Collector−Emitter Breakdown Voltage (I = −100 μAdc, V = 0)

V

−12

−4.0

—

Vdc

μAdc

C

BE

(BR)CES

V

CEO(sus)

(1)

Collector−Emitter Sustaining Voltage (I = −10 mAdc, I = 0)

C

B

Collector−Base Breakdown Voltage (I = −100 mAdc, I = 0)

V

C

E

(BR)CBO

(BR)EBO

Emitter−Base Breakdown Voltage (I = −100 mAdc, I = 0)

E

C

Collector Cutoff Current

(V = −6.0 Vdc, V = 0)

I

CES

—

−0.01

−1.0

CE

BE

(V = −6.0 Vdc, V = 0, T = 65°C)

CE

BE

A

Base Cutoff Current (V = −6.0 Vdc, V = 0)

I

B

—

−10

nAdc

CE

EB

1. FR−5 = 1.0 ꢀ 0.75 ꢀ 0.062 in.

2. Alumina = 0.4 ꢀ 0.3 ꢀ 0.024 in. 99.5% alumina.

Preferred devices are ON Semiconductor recommended choices for future use and best overall value.

1

Publication Order Number:

August, 2006 − Rev. 2

MMBT3640LT1/D

MMBT3640LT1

ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (Continued)

A

Characteristic

ON CHARACTERISTICS⁽³⁾

DC Current Gain

Symbol

Min

Max

Unit

h

FE

—

(I = −10 mAdc, V = −0.3 Vdc)

30

20

120

—

C

CE

(I = −50 mAdc, V = −1.0 Vdc)

C

CE

Collector−Emitter Saturation Voltage

(I = −10 mAdc, I = −1.0 mAdc)

V

Vdc

CE(sat)

—

−0.2

−0.6

−0.25

C

B

(I = −50 mAdc, I = −5.0 mAdc)

C

B

(I = −10 mAdc, I = −1.0 mAdc, T = 65°C)

C

B

A

Base−Emitter Saturation Voltage

(I = −10 mAdc, I = −0.5 mAdc)

BE(sat)

−0.75

−0.8

—

−0.95

−1.0

−1.5

C

B

(I = −10 mAdc, I = −1.0 mAdc)

C

B

(I = −50 mAdc, I = −5.0 mAdc)

C

B

SMALL−SIGNAL CHARACTERISTICS

Current−Gain — Bandwidth Product

f

MHz

pF

T

(I = −10 mAdc, V = −5.0 Vdc, f = 100 MHz)

500

—

C

CE

Output Capacitance

C

obo

(V = −5.0 Vdc, I = 0, f = 1.0 MHz)

3.5

CB

E

Input Capacitance

C

pF

ibo

(V = −0.5 Vdc, I = 0, f = 1.0 MHz)

—

EB

C

SWITCHING CHARACTERISTICS

Delay Time

t

—

10

30

20

12

d

(V = −6.0 Vdc, I = −50 mAdc,

CC

C

ns

V

EB(off)

= −1.9 Vdc, I = −5.0 mAdc)

B1

Rise Time

t

r

Storage Time

t

s

(V = −6.0 Vdc, I = −50 mAdc,

CC

C

ns

I

B1

= I = −5.0 mAdc)

B2

Fall Time

t

f

Turn−On Time

t

on

(V = −6.0 Vdc, I = −50 mAdc, V

= −1.9 Vdc, I = −5.0 mAdc)

—

25

60

CC

C

EB(off)

B1

(V = −1.5 Vdc, I = −10 mAdc, I = −0.5 mAdc)

CC

C

B1

Turn−Off Time

t

off

ns

(V = −6.0 Vdc, I = −50 mAdc, V

= −1.9 Vdc, I = I = −5.0 mAdc)

—

35

75

CC

C

EB(off)

B1

B2

(V = −1.5 Vdc, I = −10 mAdc, I = I = −0.5 mAdc)

CC

C

B1

B2

3. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2.0%.

V

BB

= +1.9 V

1.0 k

V

CC

= −6.0 V

110

V

BB

= −6.0 V

5.0 k

V

CC

= 1.5 V

130

0

V

out

V

out

5.0 V

0

0.1 μF

680

5.0 k

V

in

V

in

−6.8 V

TO SAMPLING SCOPE

INPUT Z ≥ 100 k

RISE TIME ≤ 1.0 ns

TO SAMPLING SCOPE

INPUT Z ≥ 100 k

RISE TIME ≤ 1.0 ns

PULSE SOURCE

51

RISE TIME ≤ 1.0 ns

PULSE WIDTH ≥ 200 ns

Z = 50 OHMS

in

PULSE WIDTH ≥ 100 ns

= 50 OHMS

Z

in

NOTES: Collector Current = 50 mA,

NOTES: Turn−On and Turn−Off Time

NOTES: Base Currents = 5.0 mA.

NOTES: Collector Current = 10 mA,

NOTES: Turn−On and Turn−Off Time

NOTES: Base Currents = 0.5 mA.

FALL TIME ≤ 1.0 ns

Figure 1.

Figure 2.

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2

MMBT3640LT1

200

100

−1.4

T = 25°C

J

V

CE

= −1.0 V

−1.2

−1.0

−0.8

−0.6

−0.4

T = 125°C

J

V

@ I /I = 10

C B

BE(sat)

25°C

70

50

−55°C

V

@ V = −1.0 V

CE

BE(on)

30

20

V

@ I /I = 10

C B

−0.2

0

CE(sat)

10

−0.1 −0.2

−0.5 −1.0 −2.0

−5.0 −10 −20

−50 −100

−0.1 −0.2

−0.5 −1.0 −2.0 −5.0 −10 −20

−50 −100

I , COLLECTOR CURRENT (mA)

C

I , COLLECTOR CURRENT (mA)

C

Figure 3. DC Current Gain

Figure 4. “On” Voltages

−1.0

−0.8

−0.6

−0.4

−0.2

0

+0.5

*APPLIES FOR I /I ≤ h /4

C B

FE

T = 25°C

J

25°C to 125°C

0

−0.5

−1.0

−1.5

−2.0

R

θ

for V

CE(sat)

VC

I

C

= −1.0 mA −5.0 mA

−20 mA

−80 mA

−55°C to 25°C

25°C to 125°C

−55°C to 25°C

−5.0 −10 −20 −50 −100

R

θ

for V

BE

VB

−0.01 −0.02 −0.05 −0.1 −0.2

−0.5 −1.0 −2.0

−5.0 −10

−0.1 −0.2

−0.5 −1.0 −2.0

I , COLLECTOR CURRENT (mA)

I , BASE CURRENT (mA)

B

C

Figure 5. Collector Saturation Region

Figure 6. Temperature Coefficients

2000

5.0

T = 25°C

J

f = 100 MHz

T = 25°C

J

V

CE

= −10 V

3.0

2.0

1000

800

−1.0 V

C

obo

600

400

C

ibo

1.0

0.7

0.5

200

−1.0

−2.0 −3.0 −5.0 −7.0 −10

−20 −30 −50 −70 −100

−0.2 −0.3 −0.5 −0.7 −1.0

−2.0 −3.0 −5.0 −7.0 −10

−20

I , COLLECTOR CURRENT (mA)

C

V , REVERSE VOLTAGE (VOLTS)

R

Figure 7. Current−Gain — Bandwidth Product

Figure 8. Capacitance

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3

MMBT3640LT1

INFORMATION FOR USING THE SOT−23 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the to-

tal design. The footprint for the semiconductor packages

must be the correct size to insure proper solder connection

interface between the board and the package. With the cor-

rect pad geometry, the packages will self align when sub-

jected to a solder reflow process.

0.037

0.95

0.037

0.95

0.079

2.0

0.035

0.9

0.031

0.8

inches

mm

SOT−23

SOT−23 POWER DISSIPATION

SOLDERING PRECAUTIONS

The power dissipation of the SOT−23 is a function of the

pad size. This can vary from the minimum pad size for sol-

dering to a pad size given for maximum power dissipation.

Power dissipation for a surface mount device is determined

The melting temperature of solder is higher than the

rated temperature of the device. When the entire device is

heated to a high temperature, failure to complete soldering

within a short time could result in device failure. There-

fore, the following items should always be observed in or-

der to minimize the thermal stress to which the devices are

subjected.

by T , the maximum rated junction temperature of the

J(max)

die, R , the thermal resistance from the device junction

θJA

to ambient, and the operating temperature, T . Using the

A

values provided on the data sheet for the SOT−23 package,

P can be calculated as follows:

D

• Always preheat the device.

• The delta temperature between the preheat and solder-

ing should be 100°C or less.*

T_J(max)− T_A

P_D=

R_θ

JA

• When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum tem-

perature ratings as shown on the data sheet. When

using infrared heating with the reflow soldering meth-

od, the difference shall be a maximum of 10°C.

• The soldering temperature and time shall not exceed

260°C for more than 10 seconds.

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values

into the equation for an ambient temperature T of 25°C,

A

one can calculate the power dissipation of the device which

in this case is 225 milliwatts.

150°C − 25°C

556°C/W

P_D=

= 225 milliwatts

• When shifting from preheating to soldering, the maxi-

mum temperature gradient shall be 5°C or less.

The 556°C/W for the SOT−23 package assumes the use

of the recommended footprint on a glass epoxy printed cir-

cuit board to achieve a power dissipation of 225 milliwatts.

There are other alternatives to achieving higher power dis-

sipation from the SOT−23 package. Another alternative

would be to use a ceramic substrate or an aluminum core

board such as Thermal Clad™. Using a board material such

as Thermal Clad, an aluminum core board, the power dis-

sipation can be doubled using the same footprint.

• After soldering has been completed, the device should

be allowed to cool naturally for at least three minutes.

Gradual cooling should be used as the use of forced

cooling will increase the temperature gradient and

result in latent failure due to mechanical stress.

• Mechanical stress or shock should not be applied dur-

ing cooling.

* Soldering a device without preheating can cause exces-

sive thermal shock and stress which can result in damage

to the device.

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4

MMBT3640LT1

PACKAGE DIMENSIONS

SOT−23 (TO−236)

CASE 318−08

ISSUE AF

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD

FINISH THICKNESS. MINIMUM LEAD THICKNESS

IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

A

L

3

INCHES

DIM MIN MAX

MILLIMETERS

S

C

B

MIN

2.80

1.20

0.89

0.37

1.78

MAX

3.04

1.40

1.11

1

2

A

B

C

D

G

H

J

0.1102 0.1197

0.0472 0.0551

0.0350 0.0440

0.0150 0.0200

0.0701 0.0807

V

G

0.50

2.04

0.100

0.177

0.69

1.02

2.64

0.60

0.0005 0.0040 0.013

0.0034 0.0070 0.085

K

L

0.0140 0.0285

0.0350 0.0401

0.0830 0.1039

0.0177 0.0236

0.35

0.89

2.10

0.45

S

V

H

J

D

K

STYLE 6:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your local

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MMBT3640LT1/D

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5


型号：	MMBT3640LT1
厂家：	ONSEMI
描述：	12 V，80 mA，开关双极结晶体管开关晶体管
文件：	总6页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MMBT3640LT1 [ONSEMI]

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