MPS5172 [ONSEMI]

General Purpose Transistor NPN Silicon; 通用晶体管NPN硅
MPS5172
型号: MPS5172
厂家: ONSEMI    ONSEMI
描述:

General Purpose Transistor NPN Silicon
通用晶体管NPN硅

晶体 晶体管
文件: 总6页 (文件大小:99K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MPS5172  
General Purpose Transistor  
NPN Silicon  
Features  
Pb−Free Packages are Available*  
http://onsemi.com  
COLLECTOR  
3
MAXIMUM RATINGS  
2
Rating  
Collector−Emitter Voltage  
Collector−Base Voltage  
Symbol  
Value  
25  
Unit  
Vdc  
Vdc  
BASE  
V
CEO  
CBO  
V
25  
1
Emitter−Base Voltage  
V
EBO  
5.0  
Vdc  
EMITTER  
Collector Current − Continuous  
I
C
100  
mAdc  
Total Device Dissipation @ T = 25°C  
P
D
625  
5.0  
mW  
mW/°C  
A
Derate above 25°C  
Total Power Dissipation @ T = 60°C  
P
P
450  
mW  
A
D
Total Device Dissipation @ T = 25°C  
1.5  
12  
W
mW/°C  
C
D
TO−92 (TO−226)  
CASE 29  
Derate above 25°C  
1
2
3
STYLE 1  
Operating and Storage Junction  
Temperature Range  
T , T  
−55 to +150  
°C  
J
stg  
THERMAL CHARACTERISTICS  
Characteristic  
MARKING DIAGRAM  
Symbol  
Max  
200  
Unit  
°C/W  
°C/W  
Thermal Resistance, Junction−to−Ambient  
Thermal Resistance, Junction−to−Case  
R
q
JA  
JC  
R
q
83.3  
MPS  
5172  
AYWW G  
G
Maximum ratings are those values beyond which device damage can occur.  
Maximumratings applied to the device are individual stress limit values (not normal  
operating conditions) and are not valid simultaneously. If these limits are exceeded,  
device functional operation is not implied, damage may occur and reliability may  
be affected.  
MPS5172 = Device Code  
A
= Assembly Location  
Y
= Year  
WW  
G
= Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
Device  
MPS5172  
MPS5172G  
Package  
Shipping  
5000 / Bulk  
5000 / Bulk  
TO−92  
TO−92  
(Pb−Free)  
MPS5172RLRM  
TO−92  
2000/Ammo Pack  
2000/Ammo Pack  
MPS5172RLRMG  
TO−92  
*For additional information on our Pb−Free strategy and soldering details, please  
downloadthe ON Semiconductor Soldering and Mounting Techniques Reference  
Manual, SOLDERRM/D.  
(Pb−Free)  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
December, 2005 − Rev. 2  
MPS5172/D  
MPS5172  
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)  
A
Characteristic  
OFF CHARACTERISTICS  
Symbol  
Min  
Max  
Unit  
Collector−Emitter Breakdown Voltage (Note 1)  
V
25  
Vdc  
(BR)CEO  
(I = 10 mA, I = 0)  
C
B
Collector Cutoff Current  
I
100  
nAdc  
CES  
(V = 25 V, I = 0)  
CE  
B
Collector Cutoff Current  
I
CBO  
(V = 25 V, I = 0)  
100  
10  
nAdc  
mAdc  
CB  
E
E
(V = 25 V, I = 0, T = 100°C)  
CB  
A
Emitter Cutoff Current  
I
100  
nAdc  
EBO  
(V = 5.0 V, I = 0)  
EB  
C
ON CHARACTERISTICS (Note 1)  
DC Current Gain  
h
100  
500  
0.25  
1.25  
FE  
(V = 10 V, I = 10 mA)  
CE  
C
Collector−Emitter Saturation Voltage  
V
Vdc  
Vdc  
CE(sat)  
(I = 10 mAdc, I = 1.0 mAdc)  
C
B
Base−Emitter On Voltage  
V
0.5  
BE(on)  
(I = 10 mAdc, V = 10 V)  
C
CE  
SMALL−SIGNAL CHARACTERISTICS  
Collector−Base Capacitance  
C
h
1.6  
10  
pF  
cb  
(V = 10 V, f = 1.0 MHz)  
CB  
Small−Signal Current Gain  
(I = 10 mAdc, V = 10 Vdc, f = 1.0 kHz)  
100  
750  
fe  
C
CE  
1. Pulse Test: Pulse Width 300 ms, Duty Cycle 2.0%.  
http://onsemi.com  
2
 
MPS5172  
TYPICAL STATIC CHARACTERISTICS  
400  
200  
T = 125°C  
J
25°C  
−ꢀ55°C  
100  
80  
60  
V
V
= 1.0 V  
= 10 V  
CE  
CE  
40  
0.004 0.006 0.01  
0.02 0.03 0.05 0.07 0.1  
0.2 0.3  
0.5 0.7 1.0  
3.0  
2.0  
5.0 7.0 10  
20 30  
50 70 100  
I , COLLECTOR CURRENT (mA)  
C
Figure 1. DC Current Gain  
1.0  
0.8  
0.6  
0.4  
0.2  
0
100  
T = 25°C  
PULSE WIDTH = 300 ms  
DUTY CYCLE 2.0%  
A
T = 25°C  
J
I
= 500 mA  
B
80  
60  
400 mA  
300 mA  
I
= 1.0 mA  
10 mA  
50 mA  
100 mA  
C
200 mA  
100 mA  
40  
20  
0
0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0  
5.0 10 20  
0
5.0  
10  
15  
20  
25  
30  
35  
40  
I , BASE CURRENT (mA)  
B
V
CE  
, COLLECTOR−EMITTER VOLTAGE (VOLTS)  
Figure 2. Collector Saturation Region  
Figure 3. Collector Characteristics  
1.4  
1.2  
1.6  
0.8  
0
*APPLIES for I /I h /2  
C B  
FE  
T = 25°C  
J
25°C to 125°C  
55°C to 25°C  
1.0  
0.8  
0.6  
0.4  
*q for V  
VC  
CE(sat)  
V
@ I /I = 10  
C B  
BE(sat)  
−ꢀ0.8  
−ꢀ1.6  
−ꢀ2.4  
V
BE(on)  
@ V = 1.0 V  
CE  
25°C to 125°C  
55°C to 25°C  
0.2  
0
q
for V  
BE  
VB  
V
@ I /I = 10  
C B  
CE(sat)  
50 100  
50 100  
0.1 0.2  
0.5 1.0  
2.0  
5.0  
10  
20  
0.1  
0.2  
0.5  
1.0 2.0  
5.0 10 20  
I , COLLECTOR CURRENT (mA)  
C
I , COLLECTOR CURRENT (mA)  
C
Figure 4. “On” Voltages  
Figure 5. Temperature Coefficients  
http://onsemi.com  
3
MPS5172  
TYPICAL DYNAMIC CHARACTERISTICS  
500  
10  
7.0  
5.0  
T = 25°C  
J
T = 25°C  
f = 100 MHz  
J
f = 1.0 MHz  
300  
200  
C
ib  
V
CE  
= 20 V  
5.0 V  
C
ob  
3.0  
2.0  
100  
70  
50  
1.0  
0.5 0.7 1.0  
2.0 3.0  
5.0 7.0 10  
20 30  
50  
0.05 0.1  
0.2  
0.5 1.0 2.0  
5.0  
10  
20  
50  
I , COLLECTOR CURRENT (mA)  
C
V , REVERSE VOLTAGE (VOLTS)  
R
Figure 6. Current−Gain − Bandwidth Product  
Figure 7. Capacitance  
http://onsemi.com  
4
MPS5172  
1.0  
0.7  
0.5  
D = 0.5  
0.2  
0.3  
0.2  
0.1  
0.1  
0.07  
0.05  
FIGURE 9  
DUTY CYCLE, D = t /t  
1 2  
0.05  
D CURVES APPLY FOR POWER  
PULSE TRAIN SHOWN  
P
(pk)  
0.02  
0.01  
READ TIME AT t (SEE AN−569)  
1
0.03  
0.02  
t
1
Z
T
= r(t) R  
q
q
JA  
Z
q
JA(t)  
JA(t)  
− T = P  
J(pk)  
A
(pk)  
SINGLE PULSE  
t
2
0.01  
0.01 0.02  
0.05 0.1 0.2  
0.5 1.0 2.0  
5.0  
10 20  
50  
100 200  
500 1.0ꢂk 2.0ꢂk 5.0ꢂk 10ꢂk 20ꢂk  
100ꢂk  
50ꢂk  
t, TIME (ms)  
Figure 8. Thermal Response  
4
3
10  
DESIGN NOTE: USE OF THERMAL RESPONSE DATA  
V
CC  
= 30 Vdc  
A train of periodical power pulses can be represented by  
the model as shown in Figure 9. Using the model and the de-  
vice thermal response the normalized effective transient  
thermal resistance of Figure 8 was calculated for various  
duty cycles.  
10  
10  
2
I
CEO  
1
0
10  
To find Z  
, multiply the value obtained from Figure  
JA(t)  
q
I
8 by the steady state value R  
Example:  
.
JA  
CBO  
q
10  
AND  
I
@ V  
= 3.0 Vdc  
CEX  
BE(off)  
The MPS3904 is dissipating 2.0 watts peak under the follow-  
ing conditions:  
−1  
10  
10  
t = 1.0 ms, t = 5.0 ms. (D = 0.2)  
−2  
1
2
40 20  
0
+20 +40 +60 +80 +100 +120 +140 +160  
Using Figure 8 at a pulse width of 1.0 ms and D = 0.2, the  
reading of r(t) is 0.22.  
T , JUNCTION TEMPERATURE (°C)  
J
The peak rise in junction temperature is therefore  
Figure 10.  
DT = r(t) x P  
x R  
= 0.22 x 2.0 x 200 = 88°C.  
JA  
(pk)  
q
For more information, see ON Semiconductor Applica-  
tion Note AN569/D, available from the Literature Distribu-  
tion Center or on our website at www.onsemi.com.  
400  
100 ms  
1.0 ms  
200  
100  
10 ms  
1.0 s  
The safe operating area curves indicate I −V limits  
C
CE  
T
= 25°C  
C
of the transistor that must be observed for reliable operation.  
Collector load lines for specific circuits must fall below the  
limits indicated by the applicable curve.  
dc  
60  
40  
T = 25°C  
A
dc  
The data of Figure 11 is based upon T  
= 150°C; T or  
C
J(pk)  
20  
10  
T = 150°C  
J
T is variable depending upon conditions. Pulse curves are  
A
valid for duty cycles to 10% provided T  
150°C. T  
J(pk)  
J(pk)  
CURRENT LIMIT  
THERMAL LIMIT  
SECOND BREAKDOWN LIMIT  
may be calculated from the data in Figure 8. At high case or  
ambient temperatures, thermal limitations will reduce the  
power that can be handled to values less than the limitations  
imposed by second breakdown.  
6.0  
4.0  
40  
2.0  
4.0 6.0 8.0 10  
20  
V
CE  
, COLLECTOR−EMITTER VOLTAGE (VOLTS)  
Figure 11.  
http://onsemi.com  
5
 
MPS5172  
PACKAGE DIMENSIONS  
TO−92 (TO−226)  
CASE 29−11  
ISSUE AL  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
A
B
2. CONTROLLING DIMENSION: INCH.  
3. CONTOUR OF PACKAGE BEYOND DIMENSION R  
IS UNCONTROLLED.  
R
4. LEAD DIMENSION IS UNCONTROLLED IN P AND  
BEYOND DIMENSION K MINIMUM.  
P
L
SEATING  
PLANE  
INCHES  
DIM MIN MAX  
MILLIMETERS  
K
MIN  
4.45  
4.32  
3.18  
0.407  
1.15  
2.42  
0.39  
12.70  
6.35  
2.04  
−−−  
MAX  
5.20  
5.33  
4.19  
0.533  
1.39  
2.66  
0.50  
−−−  
A
B
C
D
G
H
J
0.175  
0.170  
0.125  
0.016  
0.045  
0.095  
0.015  
0.500  
0.250  
0.080  
−−−  
0.205  
0.210  
0.165  
0.021  
0.055  
0.105  
0.020  
−−−  
D
X X  
G
J
H
V
K
L
−−−  
−−−  
C
N
P
R
V
0.105  
0.100  
−−−  
2.66  
2.54  
−−−  
SECTION X−X  
0.115  
0.135  
2.93  
3.43  
1
N
−−−  
−−−  
N
STYLE 1:  
PIN 1. EMITTER  
2. BASE  
3. COLLECTOR  
3. SOURCE  
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any  
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over  
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MPS5172/D  

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