MT9M031I12STC-DPBR1 [ONSEMI]
1/3âinch CMOS Digital Image Sensor;
| 型号： | MT9M031I12STC-DPBR1 |
| 厂家： | 
ONSEMI |
| 描述： | 1/3âinch CMOS Digital Image Sensor 时钟 传感器 换能器 |
| 文件： | 总23页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MT9M021, MT9M031
MT9M021/MT9M031
1/3‐inch CMOS Digital
Image Sensor
Description
The MT9M021/MT9M031 from ON Semiconductor is a 1/3-inch
CMOS digital image sensor with an active-pixel array of 1280 (H) ×
960 (V). It includes sophisticated camera functions such as auto
exposure control, windowing, scaling, row skip mode, and both video
and single frame modes. It is designed for low light performance and
features a global shutter for accurate capture of moving scenes. It is
programmable through a simple two-wire serial interface.
The MT9M021/MT9M031 produces extraordinarily clear, sharp
digital pictures, and its ability to capture both continuous video and
single frames makes it the perfect choice for a wide range of
applications, including scanning and HD video.
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IBGA63 9 y 9
CASE 503AQ
Table 1. KEY PERFORMANCE PARAMETERS
Parameter
Optical Format
Typical Value
1/3-inch (6 mm)
Active Pixels
1280 (H) × 960 (V) = 1.2 Mp
3.75 mm
ILCC48 10 y 10
Pixel Size
CASE 847AJ
Color Filter Array
Shutter Type
RGB Bayer or Monochrome
Global Shutter
Input Clock Range
Output Pixel Clock (Maximum)
6–50 MHz
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
74.25 MHz
Output
Serial
Parallel
HiSPi (iBGA Package Only)
12-bit
Features
Frame Rate
Full Resolution
720p
• Superior Low-light Performance
• HD Video (720p60)
45 fps
60 fps
• Global Shutter
Responsivity
Monochrome
Color
6.1 V/lux−sec
5.3 V/lux−sec
• Video/Single Frame Mode
• Flexible Row-skip Modes
• On-chip AE and Statistics Engine
• Parallel and Serial Output
• Support for External LED or Flash
• Auto Black Level Calibration
• Context Switching
SNR
38 dB
64 dB
MAX
Dynamic Range
Supply Voltage
I/O
Digital
Analog
HiSPi
1.8 or 2.8 V
1.8 V
2.8 V
0.4 V
Power Consumption
< 400 mW
Applications
Operating Temperature (Ambient)
Package Options
–30°C to + 70°C
• Scene Processing
• Scanning and Machine Vision
• 720p60 Video Applications
9 × 9 mm 63-pin iBGA
10 × 10 mm 48-pin iLCC
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
January, 2017 − Rev. 10
MT9M021/D
MT9M021, MT9M031
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number
Product Description
Orderable Product Attribute Description
MT9M021IA3XTC−DPBR1
MT9M021IA3XTC−DRBR
MT9M021IA3XTM−DPBR1
MT9M021IA3XTM−DRBR1
MT9M021IA3XTMZ−DPBR
MT9M021IA3XTMZ−DRBR
MT9M021IA3XTMZ−TPBR
MT9M031D00STMC24BC1−200
MT9M031I12STC−DPBR1
MT9M031I12STC−DRBR
MT9M031I12STM−DPBR
MT9M031I12STM−DRBR1
MT9M031I12STMZ−DRBR
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1 MP 1/6″ SOC
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Tape & Reel with Protective Film, Double Side BBAR Glass
Die Sales, 200 mm Thickness
1 MP 1/6″ SOC
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack with Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
Dry Pack without Protective Film, Double Side BBAR Glass
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
1.2 MP 1/3″ GS CIS
See the ON Semiconductor Device Nomenclature
document (TND310/D) for a full description of the naming
convention used for image sensors. For reference
documentation, including information on evaluation kits,
please visit our web site at www.onsemi.com.
GENERAL DESCRIPTION
The ON Semiconductor MT9M021/MT9M031 can be
operated in its default mode or programmed for frame size,
exposure, gain, and other parameters. The default mode
output is a full-resolution image at 45 frames per second
(fps). It outputs 12-bit raw data, using either the parallel or
serial (HiSPi) output ports. The device may be operated in
video (master) mode or in frame trigger mode.
A dedicated FLASH pin can be programmed to control
external LED or flash exposure illumination.
The MT9M021/MT9M031 includes additional features
to allow application-specific tuning: windowing, adjustable
auto-exposure control, auto black level correction, on-board
temperature sensor, and row skip and digital binning modes.
The sensor is designed to operate in a wide temperature
range (–30°C to +70°C).
FRAME_VALID and LINE_VALID signals are output on
dedicated pins, along with a synchronized pixel clock.
FUNCTIONAL OVERVIEW
The MT9M021/MT9M031 is a progressive-scan sensor
that generates a stream of pixel data at a constant frame rate.
It uses an on-chip, phase-locked loop (PLL) that can be
optionally enabled to generate all internal clocks from
a single master input clock running between 6 and 50 MHz.
The maximum output pixel rate is 74.25 Mp/s,
corresponding to a clock rate of 74.25 MHz. Figure 1 shows
a block diagram of the sensor.
Temperature
Sensor
External
Clock
OTPM
Memory
PLL
Active Pixel Sensor
(APS)
Array
Power
Timing and Control
(Sequencer)
Auto Exposure
and Stats Engine
Serial
Output
Pixel Data Path
(Signal Processing)
Parallel
Output
Analog Processing and
A/D Conversion
Flash
Trigger
Two-wire
Serial
Control Registers
Interface
Figure 1. Block Diagram
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2
MT9M021, MT9M031
User interaction with the sensor is through the two-wire
from the columns is sequenced through an analog signal
chain (providing offset correction and gain), and then
through an analog-to-digital converter (ADC). The output
from the ADC is a 12-bit value for each pixel in the array.
The ADC output passes through a digital processing signal
chain (which provides further data path corrections and
applies digital gain). The pixel data are output at a rate of up
to 74.25 Mp/s, in parallel to frame and line synchronization
signals.
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 1.2 Mp Active-Pixel Sensor array. The
MT9M021/MT9M031 features global shutter technology
for accurate capture of moving images. The exposure of the
entire array is controlled by programming the integration
time by register setting. All rows simultaneously integrate
light prior to readout. Once a row has been read, the data
FEATURES OVERVIEW
The MT9M021/MT9M031 Global Sensor shutter has
a wide array of features to enhance functionality and to
increase versatility. A summary of features follows. Please
refer to the MT9M021/MT9M031 Developer Guide for
detailed feature descriptions, register settings, and tuning
guidelines and recommendations.
• PLL
An on chip PLL provides reference clock flexibility and
supports spread spectrum sources for improved EMI
performance.
• Reset
The MT9M021/MT9M031 may be reset by a register
write, or by a dedicated input pin.
• Operating Modes
The MT9M021/MT9M031 works in master (video),
trigger (single frame), or Auto Trigger modes. In
master mode, the sensor generates the integration and
readout timing. In trigger mode, it accepts an external
trigger to start exposure, then generates the exposure
and readout timing. The exposure time is programmed
through the two-wire serial interface for both modes.
• Output Enable
The MT9M021/MT9M031 output pins may be
tri-stated using a dedicated output enable pin.
• Temperature Sensor
• Black Level Correction
• Row Noise Correction
• Column Correction
NOTE: Trigger mode is not compatible with the HiSPi
interface.
• Test Patterns
Several test patterns may be enabled for debug
purposes. These include a solid color, color bar, fade to
grey, and a walking 1s test pattern.
• Window Control
Configurable window size and blanking times allow
a wide range of resolutions and frame rates. Digital
binning and skipping modes are supported, as are
vertical and horizontal mirror operations.
• Context Switching
Context switching may be used to rapidly switch
between two sets of register values. Refer to the
MT9M021/MT9M031 Developer Guide for a complete
set of context switchable registers.
• Gain
The MT9M021/MT9M031 Global Shutter sensor can
be configured for analog gain of up to 8x, and digital
gain of up to 8x.
• Automatic Exposure Control
The integrated automatic exposure control may be used
to ensure optimal settings of exposure and gain are
computed and updated every other frame. Refer to the
MT9M021/MT9M031 Developer Guide for more
details.
• HiSPi
The MT9M021/MT9M031 Global Shutter image sensor
supports two or three lanes of Streaming-SP or
Packetized-SP protocols of ON Semiconductor’s
High-Speed Serial Pixel Interface.
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3
MT9M021, MT9M031
TYPICAL CONFIGURATION AND PINOUT
Digital
I/O
Digital
Core
HiSPi
PLL
Power
Analog
Analog
1
1
1
1
1
1
Power
Power
Power
Power
Power
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
Master Clock
(6−50 MHz)
EXTCLK
To Controller
7
S
S
DATA
SLVS3_P
7
CLK
SLVS3_N
From
Controller
OE_BAR
SLVSC_P
SLVSC_N
STANDBY
RESET_BAR
FLASH
TEST
D
A
GND
GND
Digital
Ground
Analog
Ground
V
DD
_IO
V
DD
V
DD
_SLVS
V
DD
_PLL
V
AA
V
AA
_PIX
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S at all times.
CLK
4. The parallel interface output pads can be left unconnected if the serial output interface is used.
5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the MT9M021/MT9M031 demo
headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is
minimized.
7. Although 4 serial lanes are shown, the MT9M021/MT9M031 supports only 2- or 3-lane HiSPi.
Figure 2. Serial 4-lane HiSPi Interface
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MT9M021, MT9M031
Digital
I/O
Digital
Core
PLL
Power
Analog
Analog
1
1
1
1
1
Power
Power
Power
Power
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Master Clock
(6−50 MHz)
D
[11:0]
OUT
EXTCLK
PIXCLK
To Controller
S
DATA
LINE_VALID
S
CLK
FRAME_VALID
From
Controller
TRIGGER
OE_BAR
STANDBY
FLASH
RESET_BAR
TEST
D
A
GND
GND
Digital
Ground
Analog
Ground
V
DD
_IO
V
DD
V
DD
_PLL
V
AA
V
AA
_PIX
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two-wire speed.
3. This pull-up resistor is not required if the controller drives a valid logic level on S at all times.
CLK
4. The serial interface output pads can be left unconnected if the parallel output interface is used.
5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible
to the pad. Actual values and results may vary depending on the layout and design considerations. Refer to the MT9M021/MT9M031 demo
headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes be placed in a manner such that coupling with the digital power planes is
minimized.
Figure 3. Parallel Pixel Data Interface
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5
MT9M021, MT9M031
1
2
3
4
5
6
7
8
A
B
SLVS0N
SLVS0P
SLVS1N
SLVS1P
V
V
STANDBY
DD
DD
V
_PLL
SLVSCN
SLVSCP
SLVS3N
SLVS2N
SLVS3P
SLVS2P
V
DD
V
V
AA
DD
AA
C
D
E
EXTCLK
V
DD
_SLVS
D
D
D
V
V
A
GND
A
GND
GND
GND
DD
S
S
CLK
S
DATA
D
V
_PIX
V
AA
_PIX
ADDR
GND
DD
AA
LINE_
VALID
FRAME_
VALID
PIXCLK
FLASH
V
V
V
V
_IO
_IO
_IO
_IO
RESERVED RESERVED
GND
GND
GND
DD
DD
DD
F
G
H
D
D
D
8
4
0
D
D
D
9
5
1
D
10
OUT
D 11
OUT
D
D
D
TEST
RESERVED
OE_BAR
OUT
OUT
D
6
D
7
3
TRIGGER
OUT
OUT
OUT
OUT
OUT
RESET_
BAR
D
2
D
V
_IO
OUT
OUT
OUT
GND
DD
DD
Top View
(Ball Down)
Figure 4. 9 y 9 mm 63-ball iBGA Package
Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE
Name
iBGA Pin
A2
Type
Output
Output
Output
Output
Input
Description
HiSPi serial data, lane 0, differential N
HiSPi serial data, lane 0, differential P
HiSPi serial data, lane 1, differential N
HiSPi serial data, lane 1, differential P
Standby-mode enable pin (active HIGH)
PLL power
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
STANDBY
A3
A4
A5
A8
V
_PLL
B1
Power
Output
DD
SLVSC_N
B2
HiSPi serial DDR clock differential N
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MT9M021, MT9M031
Table 3. PIN DESCRIPTIONS − 63-BALL IBGA PACKAGE (continued)
Name
iBGA Pin
Type
Output
Output
Output
Power
Input
Description
HiSPi serial DDR clock differential P
SLVSC_P
SLVS2_N
SLVS2_P
B3
B4
HiSPi serial data, lane 2, differential N
HiSPi serial data, lane 2, differential P
Analog power
B5
V
AA
B7, B8
EXTCLK
_SLVS
C1
External input clock
V
C2
Power
Output
Output
Power
Power
Power
Input
HiSPi power
DD
SLVS3_N
SLVS3_P
C3
HiSPi serial data, lane 3, differential N
HiSPi serial data, lane 3, differential P
Digital GND
C4
D
C5, D4, D5, E5, F5, G5, H5
GND
V
DD
A6, A7, B6, C6, D6
Digital power
A
GND
C7, C8
Analog GND
S
ADDR
D1
Two-Wire Serial address select
Two-Wire Serial clock input
Two-Wire Serial data I/O
Pixel power
S
CLK
D2
Input
S
DATA
D3
I/O
V
AA
_PIX
D7, D8
Power
Output
Output
Output
Output
Power
Output
Output
Output
Output
Input
LINE_VALID
FRAME_VALID
PIXCLK
E1
Asserted when D
Asserted when D
Pixel clock out. D
line data is valid
OUT
OUT
OUT
E2
frame data is valid
E3
is valid on rising edge of this clock
FLASH
E4
Control signal to drive external light sources
I/O supply power
V
DD
_IO
E6, F6, G6, H6, H7
D
8
OUT
9
OUT
F1
F2
F3
F4
F7
G1
G2
G3
G4
G7
G8
H1
H2
H3
H4
H8
Parallel pixel data output
D
Parallel pixel data output
D
D
10
11
Parallel pixel data output
OUT
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to D
Parallel pixel data output
OUT
TEST
)
GND
D
4
Output
Output
Output
Output
Input
OUT
OUT
OUT
OUT
D
D
D
5
6
7
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
TRIGGER
OE_BAR
Exposure synchronization input
Output enable (active LOW)
Parallel pixel data output (LSB)
Parallel pixel data output
Input
D
D
D
D
0
1
2
3
Output
Output
Output
Output
Input
OUT
OUT
OUT
OUT
Parallel pixel data output
Parallel pixel data output
RESET_BAR
Asynchronous reset (active LOW). All settings are restored to factory
default
Reserved
E7, E8, F8
N/A
Reserved (do not connect)
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MT9M021, MT9M031
7
8
D
D
D
D
D
7
NC
NC
42
41
40
39
OUT
OUT
OUT
OUT
OUT
8
9
9
V
AA
10
10
11
A
GND
11
12
13
14
15
V
_PIX
_PIX
38
37
36
35
34
AA
V
DD
_IO
V
AA
PIXCLK
V
AA
V
S
A
GND
DD
V
AA
CLK
16
17
18
S
Reserved
Reserved
Reserved
33
32
31
DATA
RESET_BAR
_IO
V
DD
Figure 5. 10 y 10 mm 48-pin iLCC Package, Parallel Output
Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL
Pin Number
Name
Type
Output
Output
Output
Power
Input
Description
1
2
3
4
5
6
7
8
9
D
D
D
4
5
6
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
PLL power
OUT
OUT
OUT
V
_PLL
DD
EXTCLK
External input clock
Digital ground
D
Power
Output
Output
Output
GND
D
D
D
7
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
OUT
OUT
OUT
8
9
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8
MT9M021, MT9M031
Table 4. PIN DESCRIPTIONS − 48-PIN ILCC PACKAGE, PARALLEL (continued)
Pin Number
10
11
Name
Type
Output
Output
Power
Output
Power
Input
Description
D
10
Parallel pixel data output
Parallel pixel data output (MSB)
I/O supply power
OUT
OUT
D
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
V
DD
_IO
PIXCLK
Pixel clock out. D
is valid on rising edge of this clock
OUT
V
DD
Digital power
S
CLK
Two-Wire Serial clock input
Two-Wire Serial data I/O
S
DATA
I/O
RESET_BAR
_IO
Input
Asynchronous reset (active LOW). All settings are restored to factory default
I/O supply power
V
DD
Power
Power
V
DD
Digital power
NC
NC
No connection
No connection
STANDBY
OE_BAR
Input
Input
Standby-mode enable pin (active HIGH)
Output enable (active LOW)
Two-Wire Serial address select
S
ADDR
Input
TEST
FLASH
Input
Manufacturing test enable pin (connect to D
)
GND
Output
Input
Flash output control
TRIGGER
FRAME_VALID
LINE_VALID
Exposure synchronization input
Output
Output
Power
N/A
Asserted when D
Asserted when D
Digital ground
frame data is valid
line data is valid
OUT
OUT
D
GND
Reserved
Reserved
Reserved
Reserved (do not connect)
Reserved (do not connect)
Reserved (do not connect)
Analog power
N/A
N/A
V
AA
Power
Power
Power
Power
Power
Power
Power
A
GND
Analog ground
V
AA
Analog power
V
_PIX
_PIX
Pixel power
AA
V
AA
Pixel power
A
GND
Analog ground
V
AA
Analog power
NC
NC
NC
No connection
No connection
No connection
D
Power
Output
Output
Output
Output
Digital ground
GND
D
D
D
D
0
Parallel pixel data output (LSB)
Parallel pixel data output
Parallel pixel data output
Parallel pixel data output
OUT
OUT
OUT
OUT
1
2
3
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MT9M021, MT9M031
ELECTRICAL SPECIFICATIONS
Two-Wire Serial Register Interface
The electrical characteristics of the two-wire serial
Unless otherwise stated, the following specifications
apply to the following conditions:
register interface (S
Table 5.
, S
) are shown in Figure 6 and
CLK DATA
V
DD
V
DD
V
DD
= 1.8 V –0.10/+0.15;
_IO = V _PLL = V = V _PIX = 2.8 V 0.3 V;
DD
AA
AA
_SLVS = 0.4 V –0.1/+0.2;
T = −30°C to +70°C;
A
Output Load = 10 pF;
PIXCLK Frequency = 74.25 MHz;
HiSPi off.
S
DATA
t
t
LOW
BUF
t
t
f
SU;DAT
t
t
r
t
f
t
r
HD;STA
S
CLK
t
t
t
SU;STA
SU;STO
HD;STA
t
t
HIGH
HD;DAT
S
Sr
P
S
NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.
Figure 6. Two-Wire Serial Bus Timing Parameters
Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS
(f
= 27 MHz; V = 1.8 V; V _IO = 2.8 V; V = 2.8 V; V _PIX = 2.8 V; V _PLL = 2.8 V; T = 25°C)
EXTCLK
DD
DD
AA
AA
DD
A
Standard Mode
Fast-Mode
Min
Max
Min
0
Max
400
−
Parameter
Clock Frequency
Symbol
Unit
S
CLK
f
0
100
−
kHz
SCL
Hold Time (Repeated) START
Condition
t
4.0
0.6
ms
HD;STA
LOW Period of the S
Clock
Clock
t
4.7
4.0
4.7
−
−
−
1.3
0.6
0.6
−
−
−
ms
ms
ms
CLK
LOW
HIGH Period of the S
t
HIGH
CLK
Set-up Time for a Repeated
START Condition
t
SU;STA
Data Hold Time
t
0 (Note 4)
3.45 (Note 5)
0 (Note 6)
0.9 (Note 5)
ms
ns
ns
HD;DAT
Data Set-up Time
t
250
−
−
100 (Note 6)
−
SU;DAT
Rise Time of both S
and
t
r
1000
20 + 0.1Cb
(Note 7)
300
DATA
S
CLK
Signals
Fall Time of both S
Signals
and S
t
f
−
300
20 + 0.1Cb
(Note 7)
300
ns
DATA
CLK
Set-up Time for STOP Condition
t
4.0
4.7
−
−
0.6
1.3
−
−
ms
ms
SU;STO
Bus Free Time between a STOP
and START Condition
t
BUF
Capacitive Load for each Bus Line
Cb
−
−
400
3.3
−
−
400
3.3
pF
pF
Serial Interface Input Pin
Capacitance
CIN_SI
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10
MT9M021, MT9M031
Table 5. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)
(f
= 27 MHz; V = 1.8 V; V _IO = 2.8 V; V = 2.8 V; V _PIX = 2.8 V; V _PLL = 2.8 V; T = 25°C)
EXTCLK
DD
DD
AA
AA
DD
A
Standard Mode
Fast-Mode
Min
Max
Min
−
Max
30
Parameter
Symbol
CLOAD_SD
RSD
Unit
pF
S
S
Max Load Capacitance
−
30
DATA
Pull-up Resistor
1.5
4.7
1.5
4.7
kW
DATA
2
1. This table is based on I C standard (v2.1 January 2000). Philips Semiconductor.
2
2. Two-wire control is I C-compatible.
3. All values referred to V
= 0.9 V _IO and V
= 0.1 V _IO levels. Sensor EXCLK = 27 MHz.
ILmax DD
IHmin
DD
4. A device must internally provide a hold time of at least 300 ns for the S
signal to bridge the undefined region of the falling edge of S
.
DATA
CLK
5. The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the S
signal.
HD;DAT
LOW
CLK
2
2
6. A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system, but the requirement t
250 ns must then be met. This
SU;DAT
will automatically be the case if the device does not stretch the LOW period of the S
signal. If such a device does stretch the LOW period
CLK
of the S
signal, it must output the next data bit to the S
line t max + t
= 1000 + 250 = 1250 ns (according to the Standard-mode
CLK
DATA
r
SU;DAT
2
I C-bus specification) before the S
line is released.
CLK
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the MT9M021/MT9M031 launches pixel
data, FV and LV with the falling edge of PIXCLK. The
using the rising edge of PIXCLK. The launch edge of
PIXCLK can be configured in register R0x3028. See
Figure 7 and Table 6 for I/O timing (AC) characteristics.
expectation is that the user captures D [11:0], FV and LV
OUT
t
t
t
t
FP
R
F
RP
90%
10%
90%
10%
90%
10%
90%
10%
t
EXTCLK
EXTCLK
PIXCLK
t
PD
Pxl_0
Pxl_1
Pxl_2
Pxl_n
Data[11:0]
t
t
PFL
t
t
PLH
PFH
LINE_VALID/
PLL
FRAME_VALID
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
Figure 7. I/O Timing Diagram
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11
MT9M021, MT9M031
Table 6. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (1.8 V VDD_IO) (Note 1)
Symbol
Definition
Input Clock Frequency
Input Clock Period
Condition
Min
6
Typ
−
Max
50
Unit
MHz
ns
f
t
EXTCLK
EXTCLK
20
−
−
166
4
t
R
Input Clock Rise Time
Input Clock Fall Time
PIXCLK Rise Time
PLL Enabled
PLL Enabled
3
ns
t
F
−
3
4
ns
t
Slew Setting = 4 (Default)
Slew Setting = 4 (Default)
2.3
3
−
4.6
4.4
60
ns
RP
t
FP
PIXCLK Fall Time
−
ns
PIXCLK Duty Cycle
PIXCLK Frequency (Note 2)
PIXCLK to Data Valid
PIXCLK to FV HIGH
PIXCLK to LV HIGH
PIXCLK to FV LOW
PIXCLK to LV LOW
40
6
50
−
%
f
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
74.25
4.5
4.5
4.5
4.5
4.5
MHz
ns
PIXCLK
t
−3
−3
−3
−3
−3
2.3
1.5
2.3
1.5
2
PD
t
ns
PFH
t
ns
PLH
t
ns
PFL
t
ns
PLL
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V _IO, and −30°C
DD
at 110% of V _IO. All values are taken at the 50% transition point. The loading used is 20 pF.
DD
2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
Table 7. I/O TIMING CHARACTERISTICS, PARALLEL OUTPUT (2.8 V VDD_IO) (Note 1)
Symbol
Definition
Condition
Min
Typ
Max
Unit
f
t
Input Clock Frequency
Input Clock Period
6
20
−
−
−
50
166
4
MHz
ns
EXTCLK
EXTCLK
t
R
Input Clock Rise Time
Input Clock Fall Time
PIXCLK Rise Time
PLL Enabled
PLL Enabled
3
ns
t
F
−
3
4
ns
t
Slew Setting = 4 (Default)
Slew Setting = 4 (Default)
2.3
3
−
4.6
4.4
60
74.25
4
ns
RP
t
FP
PIXCLK Fall Time
−
ns
PIXCLK Duty Cycle
PIXCLK Frequency (Note 2)
PIXCLK to Data Valid
PIXCLK to FV HIGH
PIXCLK to LV HIGH
PIXCLK to FV LOW
PIXCLK to LV LOW
40
6
50
−
%
f
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
Nominal Voltages, PLL Enabled
MHz
ns
PIXCLK
t
−3
−3
−3
−3
−3
2.3
1.5
2.3
1.5
2
PD
t
4
ns
PFH
t
4
ns
PLH
t
4
ns
PFL
t
4
ns
PLL
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V _IO, and −30°C
DD
at 110% of V _IO. All values are taken at the 50% transition point. The loading used is 20 pF.
DD
2. Jitter from PIXCLK is already taken into account in the data for all of the output parameters.
Table 8. I/O RISE SLEW RATE (2.8 V VDD_IO) (Note 1)
Parallel Slew (R0x306E[15:13])
Condition
Min
Typ
Max
Unit
7
6
5
4
3
2
1
0
Default
Default
Default
Default
Default
Default
Default
Default
1.08
0.77
0.58
0.44
0.32
0.23
0.16
0.10
1.77
1.26
0.95
0.70
0.51
0.37
0.25
0.15
2.72
1.94
1.46
1.08
0.78
0.56
0.38
0.22
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V _IO, and −30°C
DD
at 110% of V _IO. All values are taken at the 50% transition point. The loading used is 20 pF.
DD
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12
MT9M021, MT9M031
Table 9. I/O FALL SLEW RATE (2.8 V VDD_IO) (Note 1)
Parallel Slew (R0x306E[15:13])
Condition
Default
Default
Default
Default
Default
Default
Default
Default
Min
1.00
0.76
0.60
0.46
0.35
0.25
0.17
0.11
Typ
1.62
1.24
0.98
0.75
0.56
0.40
0.27
0.16
Max
2.41
1.88
1.50
1.16
0.86
0.61
0.41
0.24
Unit
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
7
6
5
4
3
2
1
0
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V _IO, and −30°C
DD
at 110% of V _IO. All values are taken at the 50% transition point. The loading used is 20 pF.
DD
Table 10. I/O RISE SLEW RATE (1.8 V VDD_IO) (Note 1)
Parallel Slew (R0x306E[15:13])
Condition
Default
Default
Default
Default
Default
Default
Default
Default
Min
0.41
0.30
0.24
0.19
0.14
0.10
0.07
0.04
Typ
0.65
0.47
0.37
0.28
0.21
0.15
0.10
0.06
Max
1.10
0.79
0.61
0.46
0.34
0.24
0.16
0.10
Unit
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
7
6
5
4
3
2
1
0
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V _IO, and −30°C
DD
at 110% of V _IO. All values are taken at the 50% transition point. The loading used is 20 pF.
DD
Table 11. I/O FALL SLEW RATE (1.8 V VDD_IO) (Note 1)
Parallel Slew (R0x306E[15:13])
Condition
Default
Default
Default
Default
Default
Default
Default
Default
Min
0.42
0.32
0.26
0.20
0.16
0.12
0.08
0.05
Typ
0.68
0.51
0.41
0.32
0.24
0.18
0.12
0.07
Max
1.11
0.84
0.67
0.52
0.39
0.28
0.19
0.11
Unit
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
V/ns
7
6
5
4
3
2
1
0
1. Minimum and maximum values are taken at the temperature and voltage limits; for instance, 70°C ambient at 90% of V _IO, and −30°C
DD
at 110% of V _IO. All values are taken at the 50% transition point. The loading used is 20 pF.
DD
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13
MT9M021, MT9M031
DC Electrical Characteristics
The DC electrical characteristics are shown in Table 12,
Table 13, Table 14, and Table 15.
Table 12. DC ELECTRICAL CHARACTERISTICS
Symbol
Definition
Core Digital Voltage
I/O Digital Voltage
Analog Voltage
Condition
Min
1.7
Typ
1.8
1.8/2.8
2.8
2.8
2.8
0.4
–
Max
1.95
1.9/3.1
3.1
Unit
V
V
DD
V
DD
_IO
1.7/2.5
2.5
V
V
AA
V
V
_PIX
_PLL
Pixel Supply Voltage
PLL Supply Voltage
HiSPi Supply Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
2.5
3.1
V
AA
V
DD
2.5
3.1
V
V
DD
_SLVS
0.3
0.6
V
V
IH
V
DD
_IO * 0.7
–
V
V
IL
–
–
V
_IO * 0.3
–
V
DD
I
IN
No Pull-up Resistor;
20
–
mA
V
IN
= V _IO or D
DD GND
V
Output HIGH Voltage
Output LOW Voltage
Output HIGH Current
Output LOW Current
V
DD
_IO – 0.3
–
–
–
–
–
0.4
–
V
V
OH
V
V
_IO = 2.8 V
–
–22
–
OL
DD
I
At Specified V
At Specified V
mA
mA
OH
OH
OL
I
OL
22
CAUTION: Stresses greater than those listed in Table 13 may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied.
Table 13. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Power Supply Voltage (All Supplies)
Total Power Supply Current
Total Ground Current
Minimum
–0.3
–
Maximum
4.5
Unit
V
V
SUPPLY
SUPPLY
I
200
mA
mA
V
I
–
200
GND
V
IN
DC Input Voltage
–0.3
–0.3
–40
V
V
_IO + 0.3
_IO + 0.3
+85
DD
V
OUT
T
STG
DC Output Voltage
V
DD
Storage Temperature (Note 1)
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 14. OPERATING CURRENT CONSUMPTION FOR PARALLEL OUTPUT
(V = V _PIX = V _IO = V _PLL = 2.8 V; V = 1.8 V; PLL Enabled and PIXCLK = 74.25 MHz; T = 25°C; C = 10 pF)
AA
AA
DD
DD
DD
A
LOAD
Symbol
Parameter
Condition
Min
−
Typ
Max
Unit
mA
mA
I
Digital Operating Current
Parallel, Streaming, Full Resolution 45 fps
Parallel, Streaming, Full Resolution 45 fps
45
55
–
DD
I
_IO
I/O Digital Operating Current
−
50
DD
(Note 1)
I
Analog Operating Current
Pixel Supply Current
PLL Supply Current
Parallel, Streaming, Full Resolution 45 fps
Parallel, Streaming, Full Resolution 45 fps
Parallel, Streaming, Full Resolution 45 fps
−
−
−
45
6
50
10
8
mA
mA
mA
AA
I
_PIX
AA
_PLL
DD
I
6
1. I _IO operating current is specified with image at 1/2 saturation level.
DD
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14
MT9M021, MT9M031
Table 15. STANDBY CURRENT CONSUMPTION
(Analog − V + V _PIX + V _PLL; Digital − V + V _IO; T = 25°C)
AA
AA
DD
DD
DD
A
Definition
Condition
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
Analog, 2.8 V
Digital, 1.8 V
Min
–
Typ
3
Max
10
Unit
mA
Hard Standby (Clock Off, Driven Low)
Hard Standby (Clock On, EXTCLK = 20 MHz)
Soft Standby (Clock Off, Driven Low)
–
8
75
mA
–
12
0.87
3
20
mA
–
1.3
10
mA
mA
–
–
8
75
mA
Soft Standby (Clock On, EXTCLK = 20 MHz)
–
12
0.87
20
mA
–
1.3
mA
HiSPi Electrical Specifications
The ON Semiconductor MT9M021/MT9M031 sensor
supports SLVS mode only, and does not have a DLL for
timing adjustments. Refer to the High-Speed Serial Pixel
(HiSPi) Interface Physical Layer Specification v2.00.00 for
electrical definitions, specifications, and timing
information. The V _SLVS supply in this data sheet
DD
corresponds to V _TX in the HiSPi Physical Layer
DD
Specification. Similarly, V is equivalent to V _HiSPi
DD
DD
as referenced in the specification. The HiSPi transmitter
electrical specifications are listed at 700 MHz.
Table 16. INPUT VOLTAGE AND CURRENT (HiSPi POWER SUPPLY 0.4 V)
(Measurement Conditions: Max Freq. 700 MHz)
Symbol
_SLVS
Parameter
) (Driving 100 W Load)
HiSPi
Min
Typ
Max
Unit
mA
V
I
Supply Current (PWR
–
10
15
DD
V
CMD
HiSPi Common Mode Voltage (Driving 100 W Load)
V
_SLVS x
0.45
V
V
_SLVS/2
V
V
_SLVS x
DD
0.55
DD
DD
|V
|
HiSPi Differential Output Voltage (Driving 100 W Load)
V
_SLVS x
0.36
_SLVS/2
_SLVS x
DD
0.64
V
OD
DD
DD
DV
Change in V
between Logic 1 and 0
−
−
–
−
−
−
−
−
−
−
−
−
25
25
mV
mV
%
CM
CM
|V
|
Change in |V | between Logic 1 and 0
OD
OD
NM
V
OD
Noise Margin
30
|DV
|DV
|
Difference in V
between any Two Channels
50
mV
mV
mV
CM
CM
|
Difference in V between any Two Channels
100
50
OD
OD
DV _ac
Common-mode AC Voltage (pk) without V
Cap
CM
CM
Termination
DV _ac
Common-mode AC Voltage (pk) with V
Cap Termination
−
−
−
−
−
30
mV
V
CM
CM
V
OD
_ac
Max Overshoot Peak |V
|
1.3 x |V
2.6 x |V
−
|
|
OD
diff pk-pk
OD
V
Max Overshoot V
Eye Height
−
V
diff_pkpk
OD
V
eye
1.4 x V
−
OD
R
Single-ended Output Impedance
Output Impedance Mismatch
35
−
50
−
70
W
o
DR
20
%
o
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15
MT9M021, MT9M031
V
DIFFmax
V
DIFFmin
0 V (Diff)
Output Signal
is ‘Cp − Cn’ or
‘Dp − Dn’
Figure 8. Differential Output Voltage for Clock and Data Pairs
Table 17. RISE AND FALL TIMES
(Measurement Conditions: HiSPi Power Supply 0.4 V, Max Freq. 700 MHz)
Symbol
1/UI
Parameter
Min
280
0.3
0.3
–
Typ
Max
700
–
Unit
Mb/s
UI
Data Rate
–
TxPRE
TxPost
RISE
Max Setup Time from Transmitter (Note 1)
Max Hold Time from Transmitter
Rise Time (20−80%)
–
–
–
UI
0.25 UI
–
FALL
Fall Time (20−80%)
150 ps
45
0.25 UI
–
PLL_DUTY
Clock Duty
50
−
55
3.57
−
%
ns
UI
UI
ps
ps
UI
UI
ps
t
pw
Bitrate Period (Note 1)
1.43
0.3
−
t
Eye Width (Notes 1, 2)
−
eye
t
Data Total Jitter (pk pk)@1e−9 (Notes 1, 2)
Clock Period Jitter (RMS) (Note 2)
Clock Cycle to Cycle Jitter (RMS) (Note 2)
Clock to Data Skew (Notes 1, 2)
PHY-to-PHY Skew (Notes 1, 5)
Mean Differential Skew (Note 6)
−
0.2
50
100
0.1
2.1
100
totaljit
t
t
−
−
ckjit
−
−
cyjit
t
−0.1
−
−
chskew
t
−
|PHYskew|
t
–100
−
DIFFSKEW
1. One UI is defined as the normalized mean time between one edge and the following edge of the clock.
2. Taken from 0 V crossing point.
3. Also defined with a maximum loading capacitance of 10 pF on any pin. The loading capacitance may also need to be less for higher bitrates
so the rise and fall times do not exceed the maximum 0.3 UI.
4. The absolute mean skew between the Clock lane and any Data Lane in the same PHY between any edges.
5. The absolute mean skew between any Clock in one PHY and any Data lane in any other PHY between any edges.
6. Differential skew is defined as the skew between complementary outputs. It is measured as the absolute time between the two
complementary edges at mean V
point.
CM
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16
MT9M021, MT9M031
RISE
80%
20%
DATA MASK
TxPre
TxPost
FALL
UI/2
UI/2
CLOCK MASK
Trigger/Reference
CLKJITTER
Figure 9. Eye Diagram for Clock and Data Signals
VCMD
t
CMPSKEW
t
CHSKEW1PHY
Figure 10. Skew within the PHY and Output Channels
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17
MT9M021, MT9M031
POWER-ON RESET AND STANDBY TIMING
Power-Up Sequence
The recommended power-up sequence for the
MT9M021/MT9M031 is shown in Figure 11. The available
5. Assert RESET_BAR for at least 1 ms.
6. Wait 150000 EXTCLKs (for internal initialization
into software standby).
power supplies (V _IO, V , V _SLVS, V _PLL,
DD
DD
DD
DD
V
, V _PIX) must have the separation specified below.
7. Configure PLL, output, and image settings to
desired values.
AA AA
1. Turn on V _PLL power supply.
DD
2. After 0−10 ms, turn on V and V _PIX power
8. Wait 1 ms for the PLL to lock.
9. Set streaming mode (R0x301a[2] = 1).
AA
AA
supply.
3. After 0−10 ms, turn on V _IO power supply.
DD
4. After the last power supply is stable, enable
EXTCLK.
V
DD
_PLL (2.8)
t
0
V
V
AA
_PIX
(2.8)
AA
t
1
V
DD
_IO (1.8/2.8)
t
2
V
DD
(1.8)
t
3
V
DD
_SLVS (0.4)
EXTCLK
t
4
RESET_BAR
t
5
t
6
t
X
Hard
Reset
Internal
Initialization
Software
Standby
PLL Lock
Streaming
Figure 11. Power Up
Table 18. POWER-UP SEQUENCE
Symbol
Definition
_PLL to V /V _PIX
Min
0
Typ
Max
Unit
ms
t
t
t
t
V
10
–
–
–
–
–
–
–
–
0
1
2
3
X
DD
AA AA
V
V
V
/V _PIX to V _IO
0
10
ms
AA AA
DD
_IO to V
0
10
ms
DD
DD
DD
to V _SLVS
0
10
ms
DD
t
Xtal Settle Time
Hard Reset
–
30 (Note 1)
ms
ms
t
4
t
5
t
6
1 (Note 2)
–
–
–
Internal Initialization
PLL Lock Time
150000
1
EXTCLKs
ms
1. Xtal settling time is component-dependent, usually taking about 10–100 ms.
2. Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
3. It is critical that V _PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
DD
others. If the case happens that V _PLL is powered after other supplies then the sensor may have functionality issues and will experience
DD
high current draw on this supply.
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18
MT9M021, MT9M031
Power-Down Sequence
The recommended power-down sequence for the
MT9M021/MT9M031 is shown in Figure 12. The available
power supplies (V _IO, V , V _SLVS, V _PLL,
DD
DD
DD
DD
V
, V _PIX) must have the separation specified below.
AA AA
1. Disable streaming if output is active by setting
standby R0x301a[2] = 0.
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended.
3. Turn off V _SLVS.
DD
4. Turn off V
.
DD
5. Turn off V _IO.
DD
6. Turn off V /V _PIX.
AA AA
7. Turn off V _PLL.
DD
V
DD
_SLVS (0.4)
t
0
V
DD
(1.8)
t
1
V
DD
_IO (1.8/2.8)
t
2
V
V
AA
_PIX
(2.8)
AA
t
3
V
DD
_PLL (2.8)
EXTCLK
t
4
Power Down until Next
Power Up Cycle
Figure 12. Power Down
Table 19. POWER-DOWN SEQUENCE
Symbol
Parameter
Min
0
Typ
–
Max
Unit
ms
t
0
t
1
t
2
t
3
t
4
V
V
V
_SLVS to V
DD
–
–
–
–
–
DD
DD
DD
to V _IO
0
–
ms
DD
_IO to V /V _PIX
0
–
ms
AA AA
V
/V _PIX to V _PLL
0
–
ms
AA AA
DD
PwrDn until Next PwrUp Time
100
–
ms
1. t is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
4
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19
MT9M021, MT9M031
80
70
60
50
40
30
20
10
0
350
400
450
500
550
600
650
700
750
800
850
900
950 1000 1050 1100
Wavelength (nm)
Figure 13. Quantum Efficiency − Monochrome Sensor
70
60
50
40
30
20
10
0
Red
Green
Blue
350
400
450
500
550
600
650
700
750
800
850
900
950
1050
1000
Wavelength (nm)
Figure 14. Quantum Efficiency − Color Sensor
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20
MT9M021, MT9M031
PACKAGE DIMENSIONS
Figure 15. 63-Ball iBGA Package Outline Drawing (Case 503AQ)
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21
MT9M021, MT9M031
PACKAGE DIMENSIONS
Figure 16. 48-Pin iLCC Package Outline Drawing (Case 847AJ)
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22
MT9M021, MT9M031
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