MTB50P03HDLG [ONSEMI]
Power MOSFET 50 Amps, 30 Volts, Logic Level P−Channel D2PAK; 功率MOSFET 50安培， 30伏特，逻辑电平P沟道D2PAK
| 型号： | MTB50P03HDLG |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET 50 Amps, 30 Volts, Logic Level P−Channel D2PAK |
| 文件： | 总9页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTB50P03HDL
Preferred Device
Power MOSFET
50 Amps, 30 Volts, Logic Level
P−Channel D2PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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50 AMPERES
30 VOLTS
RDS(on) = 25 mW
Features
P−Channel
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
D
• Diode is Characterized for Use in Bridge Circuits
G
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
• Short Heatsink Tab Manufactured − Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Pb−Free Packages are Available
S
4
2
D PAK
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
CASE 418B
STYLE 2
Rating
Drain−Source Voltage
Symbol Value Unit
2
3
1
V
30
30
Vdc
Vdc
DSS
Drain−Gate Voltage (R = 1.0 MW)
V
V
GS
DGR
MARKING DIAGRAM
& PIN ASSIGNMENT
Gate−Source Voltage
− Continuous
V
15
20
Vdc
Vpk
GS
− Non−Repetitive (t ≤ 10 ms)
p
GSM
4
Drain Current − Continuous
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (t ≤ 10 ms)
I
I
50
31
150
Adc
Apk
Drain
D
D
I
p
DM
M
TB
Total Power Dissipation
P
125
1.0
2.5
W
W/°C
W
D
Derate above 25°C
50P03HG
AYWW
Total Power Dissipation @ T = 25°C, when
C
mounted with the minimum recommended pad size
Operating and Storage Temperature Range
T , T
− 55 to
150
°C
J
stg
2
Drain
1
3
Single Pulse Drain−to−Source Avalanche
E
1250
mJ
AS
Energy − Starting T = 25°C
Gate
Source
J
(V = 25 Vdc, V = 5.0 Vdc, Peak
DD
GS
I = 50 Apk, L = 1.0 mH, R = 25 W)
L
G
MTB50P03H = Device Code
A
Y
WW
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient, when mounted with the
minimum recommended pad size
°C/W
R
R
R
1.0
62.5
50
q
JC
JA
JA
q
q
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
T
260
°C
ORDERING INFORMATION
L
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Preferred devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 6
MTB50P03HDL/D
MTB50P03HDL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V = 0 Vdc, I = 250 mAdc)
Temperature Coefficient (Positive)
(C ≥ 2.0) (Note 3)
pk
V
Vdc
(BR)DSS
30
−
−
26
−
−
GS
D
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
I
DSS
(V = 30 Vdc, V = 0 Vdc)
−
−
−
−
1.0
10
DS
GS
(V = 30 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate−Body Leakage Current
(V 15 Vdc, V = 0 Vdc)
nAdc
GSS
=
−
−
100
GS
DS
ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(C ≥ 3.0) (Note 3)
V
R
Vdc
pk
GS(th)
(V = V , I = 250 mAdc)
1.0
−
1.5
4.0
2.0
−
DS
GS
D
Threshold Temperature Coefficient (Negative)
mV/°C
mW
Static Drain−Source On−Resistance
(C ≥ 3.0) (Note 3)
pk
DS(on)
(V = 5.0 Vdc, I = 25 Adc)
−
20.9
25
GS
D
Drain−Source On−Voltage (V = 5.0 Vdc)
V
Vdc
GS
DS(on)
(I = 50 Adc)
−
−
0.83
−
1.5
1.3
D
(I = 25 Adc, T =125°C)
D
J
Forward Transconductance
(V = 5.0 Vdc, I = 25 Adc)
g
FS
mhos
15
20
−
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
3500
1550
550
4900
2170
770
pF
ns
iss
Output Capacitance
(V = 25 Vdc, V = 0 Vdc, f = 1.0 MHz)
C
oss
DS
GS
Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 2)
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
22
340
90
30
466
117
300
100
−
d(on)
Rise Time
t
r
(V = 15 Vdc, I = 50 Adc,
DD
D
V
= 5.0 Vdc, R = 2.3 W)
GS
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
218
74
f
Gate Charge (See Figure 8)
Q
Q
Q
Q
nC
T
1
2
3
13.6
44.8
35
(V = 24 Vdc, I = 50 Adc,
DS
D
V
= 5.0 Vdc)
GS
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
Vdc
ns
SD
(I = 50 Adc, V = 0 Vdc)
S
GS
−
−
2.39
1.84
3.0
−
(I = 50 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
(See Figure 15)
t
−
−
−
−
106
58
−
−
−
−
rr
t
a
(I = 50 Adc, V = 0 Vdc,
S
GS
dI /dt = 100 A/ms)
S
t
48
b
Reverse Recovery Stored Charge
Q
0.246
mC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
L
−
−
3.5
7.5
−
−
nH
nH
D
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
L
S
(Measured from the source lead 0.25″ from package to source bond pad)
1. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
2. Switching characteristics are independent of operating junction temperature.
3. Reflects typical values.
Max limit − Typ
C
pk
=
3 x SIGMA
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2
MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
100
80
100
T = −ꢀ55°C
V
≥ 5 V
T = 25°C
J
J
V
= 10 V
5 V
DS
GS
8 V
6 V
25°C
100°C
80
60
40
4 V
4.5 V
60
3.5 V
40
3 V
20
0
20
0
2.5 V
0
0.2 0.4 0.6
0.8
1.0 1.2
1.4 1.6 1.8
2.0
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.029
0.022
0.021
0.020
0.019
0.018
V
= 5 V
GS
T = 25°C
J
V
= 5 V
GS
0.027
0.025
0.023
0.021
0.019
0.017
0.015
T = 100°C
J
25°C
0.017
0.016
0.015
10 V
−ꢀ55°C
0
20
40
60
80
100
0
20
40
60
80
100
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.35
1.25
1.15
1.05
1000
100
10
V
= 0 V
GS
V
= 5 V
I = 25 A
GS
D
T = 125°C
J
0.95
0.85
100°C
−ꢀ50
−ꢀ25
0
25
50
75
100
125
150
0
5
10
15
20
25
30
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage
Current versus Voltage
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MTB50P03HDL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring which
is common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a
function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also complicates
the mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to
measure and, consequently, is not specified.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
14000
12000
10000
8000
6000
4000
2000
0
V
= 0 V
V
= 0 V
GS
DS
T = 25°C
J
C
iss
C
rss
C
iss
C
oss
rss
C
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTB50P03HDL
6
5
4
3
2
1
0
30
25
20
15
10
5
1000
V
V
= 30 V
= 10 V
I = 50 A
D
DD
GS
QT
T = 25°C
J
t
r
V
GS
t
f
Q1
Q2
t
d(off)
100
I = 50 A
D
T = 25°C
J
t
d(on)
Q3
20
V
DS
0
80
10
0
10
30
40
50
60
70
1
10
Q , TOTAL GATE CHARGE (nC)
T
R , GATE RESISTANCE (Ohms)
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
high di/dts. The diode’s negative di/dt during t is directly
controlled by the device clearing the stored charge.
a
However, the positive di/dt during t is an uncontrollable
b
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t /t serves as a good indicator of recovery
b a
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
device, therefore it has a finite reverse recovery time, t , due
rr
to the storage of minority carrier charge, Q , as shown in
RR
the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t ), have less stored charge and a softer
rr
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
like a diode with short t and low Q specifications to
rr
RR
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
50
V
= 0 V
GS
T = 25°C
J
40
30
20
10
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
2.4
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
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MTB50P03HDL
di/dt = 300 A/ms
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded, and that the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t , t ) does not exceed 10 ms. In addition the
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
r
f
total power averaged over a complete switching cycle must
not exceed (T − T )/(R ).
energy at currents below rated continuous I can safely be
D
J(MAX)
C
qJC
assumed to equal the values indicated.
A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
1000
1400
V
= 20 V
SINGLE PULSE
GS
I = 50 A
D
1200
1000
800
T = 25°C
C
100
100 ms
600
1 ms
10
1
10 ms
400
dc
R
LIMIT
DS(on)
200
0
THERMAL LIMIT
PACKAGE LIMIT
0.1
1.0
10
100
25
50
75
100
125
150
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
DS
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
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MTB50P03HDL
TYPICAL ELECTRICAL CHARACTERISTICS
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
(t) = r(t) R
q
JC
0.05
0.02
q
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
1
0.01
t
2
T
− T = P
C
R
(t)
q
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
SINGLE PULSE
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
t, TIME (s)
1.0E−01
1.0E+00
1.0E+01
Figure 14. Thermal Response
3
2.5
2.0
1.5
1
R
= 50°C/W
q
JA
Board material = 0.065 mil FR−4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
di/dt
I
S
t
rr
t
a
t
b
TIME
0.5
0.25 I
t
p
S
0
25
50
75
100
125
150
I
S
T , AMBIENT TEMPERATURE (°C)
A
Figure 15. Diode Reverse Recovery Waveform
Figure 16. D2PAK Power Derating Curve
ORDERING INFORMATION
†
Device
MTB50P03HDL
Package
Shipping
2
D PAK
2
50 Units / Rail
MTB50P03HDLG
D PAK
(Pb−Free)
2
MTB50P03HDLT4
MTB50P03HDLT4G
D PAK
800 / Tape & Reel
2
D PAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MTB50P03HDL
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE J
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
E
V
W
−B−
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
MAX
A
B
C
D
E
F
G
H
J
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
A
4.83
0.89
1.40
8.89
S
1
2
3
2.54 BSC
−T−
SEATING
PLANE
0.080
0.018 0.025
0.090 0.110
0.110
2.03
0.46
2.29
1.32
7.11
5.00 REF
2.00 REF
0.99 REF
2.79
0.64
2.79
1.83
8.13
K
W
J
K
L
G
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
M
N
P
R
S
V
H
D 3 PL
M
M
T B
0.13 (0.005)
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
VARIABLE
CONFIGURATION
ZONE
STYLE 2:
PIN 1. GATE
2. DRAIN
N
P
R
U
3. SOURCE
4. DRAIN
L
L
L
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MTB50P03HDL
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MTB50P03HDL/D
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