MTD10N10EL_06 [ONSEMI]
TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount; TMOS E- FET功率场效应晶体管DPAK封装的表面贴装
| 型号： | MTD10N10EL_06 |
| 厂家： | 
ONSEMI |
| 描述： | TMOS E−FET Power Field Effect Transistor DPAK for Surface Mount |
| 文件： | 总7页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTD10N10EL
TMOS E−FET™
Power Field Effect Transistor
DPAK for Surface Mount
N−Channel Enhancement−Mode Silicon
Gate
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This advanced TMOS E−FET is designed to withstand high energy
in the avalanche and commutation modes. The new energy efficient
design also offers a drain−to−source diode with a fast recovery time.
Designed for low voltage, high speed switching applications in power
supplies, converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
safety margin against unexpected voltage transients.
R
TYP
DS(ON)
V
I MAX
D
DSS
100 V
0.22 W
10 A
N−Channel
D
Features
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
G
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
S
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
• Pb−Free Package is Available
MARKING DIAGRAM & PIN ASSIGNMENTS
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Parameter
Drain−to−Source Voltage
Symbol Value
Unit
Vdc
Vdc
Gate 1
4
V
100
100
DSS
DGR
YWW
4
Drain−to−Gate Voltage (R = 1.0 MW)
V
GS
Drain 2
10N
Drain
2
1
10ELG
Gate−to−Source Voltage − Continuous
V
15
20
Vdc
Vpk
GS
3
Non−Repetitive (t ≤ 10 ms)
V
DPAK
CASE 369C
p
GSM
Source 3
Drain Current − Continuous
I
I
10
6.0
35
Adc
Apk
D
D
(Surface Mount)
STYLE 2
− Continuous @ 100°C
− Single Pulse (t ≤ 10 ms)
I
p
DM
Total Power Dissipation @ T = 25°C
P
40
0.32
1.75
W
W/°C
W
C
D
Derate above 25°C
10N10EL = Device Code
Total Power Dissipation @ T = 25°C (Note 2)
A
Y
WW
G
= Year
= Work Week
= Pb−Free Package
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
T , T
−55 to
150
°C
J
stg
E
mJ
AS
Energy − Starting T = 25°C
50
J
(V = 25 Vdc, V = 5.0 Vdc, I = 10 Apk,
DD
GS
L
ORDERING INFORMATION
L = 1.0 mH, R = 25 W)
G
†
Device
Package
Shipping
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
°C/W
°C
R
R
R
3.13
100
71.4
θ
θ
θ
JC
JA
JA
MTD10N10ELT4
DPAK
2500 Tape & Reel
2500 Tape & Reel
MTD10N10ELT4G
DPAK
(Pb−Free)
Maximum Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
T
260
L
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using minimum recommended pad
size.
2. When surface mounted to an FR4 board using 0.5 sq in pad size.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
June, 2006 − Rev. 3
MTD10N10EL/D
MTD10N10EL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
V
Vdc
(BR)DSS
(V = 0 Vdc, I = 0.25 mAdc)
100
−
−
115
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
I
DSS
(V = 100 Vdc, V = 0 Vdc)
−
−
−
−
10
100
DS
GS
(V = 100 Vdc, V = 0 Vdc, T = 125°C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V = 0 Vdc)
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
V
GS(th)
(V = V , I = 250 mAdc)
Threshold Temperature Coefficient (Negative)
1.0
−
1.45
4.0
2.0
−
DS
GS
D
mV/°C
W
Static Drain−to−Source On−Resistance (V = 5.0 Vdc, I = 5.0 Adc)
R
V
−
0.17
0.22
GS
D
DS(on)
Drain−to−Source On−Voltage
(V = 5.0 Vdc, I = 10 Adc)
Vdc
DS(on)
−
−
1.85
−
2.6
2.3
GS
D
(V = 5.0 Vdc, I = 5.0 Adc, T = 125°C)
GS
D
J
Forward Transconductance (V = 15 Vdc, I = 5.0 Adc)
g
FS
2.5
7.9
−
mhos
pF
DS
DYNAMIC CHARACTERISTICS
Input Capacitance
D
C
iss
−
−
−
741
175
18.9
1040
250
40
Output Capacitance
C
oss
(V = 25 Vdc, V = 0 Vdc, f = 1.0 MHz)
DS
GS
Reverse Transfer Capacitance
C
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
11
74
20
150
30
80
15
−
ns
d(on)
Rise Time
t
r
(V = 50 Vdc, I = 10 Adc,
DD
GS
D
V
= 5.0 Vdc, R = 9.1 W)
G
Turn−Off Delay Time
Fall Time
t
17
d(off)
t
38
f
Gate Charge (See Figure 8)
Q
T
Q
1
Q
2
Q
3
9.3
2.56
4.4
4.66
nC
(V = 80 Vdc, I = 10 Adc,
DS
D
V
= 5.0 Vdc)
GS
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 3)
V
Vdc
ns
SD
(I = 10 Adc, V = 0 Vdc)
S
GS
−
−
0.98
0.898
1.6
−
(I = 10 Adc, V = 0 Vdc, T = 125°C)
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
−
−
−
−
124.7
86
−
−
−
−
rr
t
a
(I = 10 Adc, V = 0 Vdc,
S
GS
dI /dt = 100 A/ms)
S
t
38.7
0.539
b
Reverse Recovery Stored Charge
Q
mC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
L
nH
nH
D
(Measured from the drain lead 0.25″ from package to center of die)
−
−
4.5
7.5
−
−
Internal Source Inductance
L
S
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
MTD10N10EL
TYPICAL ELECTRICAL CHARACTERISTICS
20
15
10
5
20
7 V
V
= 10 V
GS
T = 25°C
J
V
≥ 5 V
DS
5 V
−55°C
4.5 V
15
10
5
25°C
4 V
T = 100°C
J
3.5 V
3 V
2 V
0
0
0
1
2
3
4
5
1
2
3
4
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
DS
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.35
0.25
0.15
0.05
0.25
V
= 10 V
GS
T = 25°C
J
100°C
V
= 5 V
0.2
0.15
0.1
GS
T = 25°C
J
10 V
−55°C
0
5
10
I , DRAIN CURRENT (AMPS)
15
20
0
5
10
15
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2
100
10
1
V = 5 V
GS
I = 5 A
V
= 0 V
GS
T = 125°C
J
D
1.5
1
100°C
0.5
0
−50
−25
0
25
50
75
100
125
150
0
20
40
60
80
1
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTD10N10EL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
The capacitance (C ) is read from the capacitance curve
iss
at a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP
)
tf = Q2 x RG/VGSP
where
V
GG
= the gate drive voltage, which varies from zero to
V
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP
)
1800
1600
1400
1200
V
= 0 V
V
= 0 V
DS
GS
T = 25°C
J
C
iss
1000
800
600
400
C
iss
C
rss
C
C
oss
200
0
rss
10
5
0
5
10
15
20
25
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTD10N10EL
90
75
60
1000
12
8
T = 25°C
D
J
I = 10 A
Q
T
V
V
= 100 V
= 5 V
DS
GS
V
100
GS
t
r
t
f
45
30
15
0
t
d(off)
Q
Q
2
1
10
1
4
0
t
T = 25°C
d(on)
J
I = 10 A
D
V
DS
Q
3
1
10
R , GATE RESISTANCE (OHMS)
1
0
2
4
6
8
10
G
Q , TOTAL GATE CHARGE (nC)
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
10
V
= 0 V
GS
T = 25°C
J
8
6
4
2
0
0.5
0.6
0.7
0.8
0.9
1.0
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
− T )/(R ).
energy at currents below rated continuous I can safely be
J(MAX)
C
θJC
D
A Power MOSFET designated E−FET can be safely used
assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For
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5
MTD10N10EL
SAFE OPERATING AREA
50
100
10
V
= 20 V
SINGLE PULSE
I = 10ꢀA
D
GS
T = 25°C
C
40
10 ms
30
20
100 ms
1 ms
10 ms
1
dc
10
0
R
LIMIT
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1
10
100
25
50
75
100
125
150
T , STARTING JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.05
0.1
R
(t) = r(t) R
θ θ
JC JC
0.02
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
0.01
t
1
1
SINGLE PULSE
t
2
T
− T = P
C
R
(t)
θ
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1 2
0.01
0.00001
0.0001
0.001
0.01
0.1
1.0
10
t, TIME (ms)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
MTD10N10EL
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
NOTES:
SEATING
PLANE
−T−
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
C
2. CONTROLLING DIMENSION: INCH.
B
R
INCHES
DIM MIN MAX
MILLIMETERS
E
V
MIN
5.97
6.35
2.19
0.69
0.46
0.94
MAX
6.22
6.73
2.38
0.88
0.58
1.14
A
B
C
D
E
F
G
H
J
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.090 BSC
4
2
Z
A
K
S
1
3
4.58 BSC
U
0.87
0.46
2.60
1.01
0.58
2.89
K
L
2.29 BSC
F
J
R
S
U
V
Z
0.180 0.215
0.025 0.040
4.57
0.63
0.51
0.89
3.93
5.45
1.01
−−−
1.27
−−−
L
H
0.020
0.035 0.050
0.155 −−−
−−−
D 2 PL
M
G
0.13 (0.005)
T
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
3.0
0.244
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
E−FET is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MTD10N10EL/D
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