MTD5P06VT4G [ONSEMI]
功率 MOSFET，-60V，-5A，450mΩ，单 P 沟道，DPAK;
| 型号： | MTD5P06VT4G |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，-60V，-5A，450mΩ，单 P 沟道，DPAK 局域网 开关 脉冲 晶体管 |
| 文件： | 总8页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTD5P06V
Preferred Device
Power MOSFET
5 A, 60 V, P−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
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V
R
DS(on)
TYP
I MAX
D
(BR)DSS
60 V
340 mW
5.0 A
Features
• Avalanche Energy Specified
P−Channel
• I
and V
Specified at Elevated Temperature
DSS
DS(on)
D
• Pb−Free Packages are Available
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
G
Rating
Symbol
Value
60
Unit
Vdc
Vdc
Drain−to−Source Voltage
V
DSS
DGR
S
Drain−to−Gate Voltage (R = 1.0 MW)
V
V
60
GS
Gate−to−Source Voltage
− Continuous
MARKING
DIAGRAM
V
15
25
Vdc
Vpk
GS
− Non−repetitive (t ≤ 10 ms)
p
GSM
Drain Current − Continuous @ 25°C
− Continuous @ 100°C
I
I
5
4
18
Adc
Apk
D
D
4
Drain
4
− Single Pulse (t ≤ 10 ms)
I
p
DM
Total Power Dissipation @ 25°C
Derate above 25°C
P
40
0.27
W
W/°C
W
DPAK
CASE 369C
STYLE 2
D
2
3
1
Total Power Dissipation @ T = 25°C (Note 2)
2.1
A
Operating and Storage Temperature Range
T , T
−55 to
175
°C
J
stg
2
1
Gate
3
Drain
Source
Single Pulse Drain−to−Source Avalanche
E
125
mJ
°C/W
°C
AS
Energy − Starting T = 25°C
J
(V = 25 Vdc, V = 10 Vdc, Peak
DD
GS
I = 5 Apk, L = 10 mH, R = 25 W)
L
G
Y
WW
= Year
= Work Week
5P06V = Device Code
= Pb−Free Package
Thermal Resistance
Junction−to−Case
R
R
R
3.75
100
71.4
q
JC
JA
JA
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
q
q
G
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 seconds
T
260
L
ORDERING INFORMATION
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
†
Device
Package
Shipping
MTD5P06V
DPAK
DPAK
75 Units/Rail
MTD5P06VT4
2500/Tape & Reel
2500/Tape & Reel
MTD5P06VT4G
DPAK
2. When surface mounted to an FR−4 board using the 0.5 sq in drain pad size.
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 6
MTD5P06V/D
MTD5P06V
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
V
Vdc
(BR)DSS
(V = 0 Vdc, I = 0.25 mAdc)
60
−
−
61.2
−
−
GS
D
Temperature Coefficient (Positive)
mV/°C
mAdc
Zero Gate Voltage Drain Current
I
I
DSS
(V = 60 Vdc, V = 0 Vdc)
−
−
−
−
10
100
DS
GS
(V = 60 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
15 Vdc, V = 0 Vdc)
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
V
GS(th)
(V = V , I = 250 mAdc)
Threshold Temperature Coefficient (Negative)
2.0
−
2.8
4.7
4.0
−
DS
GS
D
mV/°C
W
Static Drain−Source On−Resistance (V = 10 Vdc, I = 2.5 Adc)
R
V
−
0.34
0.45
GS
D
DS(on)
Drain−Source On−Voltage
(V = 10 Vdc, I = 5 Adc)
Vdc
DS(on)
−
−
−
−
2.7
2.6
GS
D
(V = 10 Vdc, I = 2.5 Adc, T = 150°C)
GS
D
J
Forward Transconductance
(V = 15 Vdc, I = 2.5 Adc)
g
Mhos
pF
FS
1.5
3.6
−
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
C
−
−
−
367
140
29
510
200
60
iss
(V = 25 Vdc, V = 0 Vdc,
DS
GS
Output Capacitance
Transfer Capacitance
C
oss
f = 1.0 MHz)
C
rss
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
t
−
−
−
−
−
−
−
−
11
26
20
50
30
40
20
−
ns
d(on)
Rise Time
t
r
(V = 30 Vdc, I = 5 Adc,
DD
D
V
= 10 Vdc, R = 9.1 W)
GS
G
Turn−Off Delay Time
Fall Time
t
17
d(off)
t
19
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
12
nC
3.0
5.0
5.0
(V = 48 Vdc, I = 5 Adc, V = 10 Vdc)
DS
D
GS
−
−
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
V
Vdc
ns
SD
(I = 5 Adc, V = 0 Vdc)
S
GS
−
−
1.72
1.34
3.5
−
(I = 5 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
Reverse Recovery Time
t
−
−
−
−
97
73
−
−
−
−
rr
t
a
(I = 5 Adc, V = 0 Vdc,
S
GS
dI /dt = 100 A/ms)
S
t
24
b
Reverse Recovery Stored Charge
Q
0.42
mC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
L
nH
nH
D
(Measured from the drain lead 0.25″ from package to center of die)
−
−
4.5
7.5
−
−
Internal Source Inductance
L
S
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
MTD5P06V
TYPICAL ELECTRICAL CHARACTERISTICS
10
8
10
8 V
T = −55°C
V
= 10V
J
V
≥ 10 V
GS
DS
7 V
6 V
9 V
9
8
7
6
5
4
3
2
1
0
25°C
100°C
T = 25°C
J
6
4
5 V
2
0
4 V
8
0
1
2
3
4
5
6
7
9
2
3
4
5
6
7
8
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V , GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.6
0.4
0.35
0.3
V
= 10 V
T = 25°C
J
GS
0.55
T = 100°C
V
= 10 V
15 V
J
GS
0.5
0.45
0.4
25°C
0.35
0.3
0.25
0.2
−55°C
0.25
0.2
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
100
10
1
1.8
1.6
1.4
1.2
1
V
= 0 V
V
= 10 V
I = 2.5 A
GS
GS
D
T = 125°C
J
0.8
0.6
0.4
0.2
50
−50 −25
0
25
50
75
100 125
150 175
0
10
V
20
30
40
60
T , JUNCTION TEMPERATURE (°C)
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
J
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTD5P06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
1000
900
800
700
600
V
= 0 V
DS
T = 25°C
J
C
iss
C
rss
500
400
300
200
C
iss
C
oss
C
rss
100
0
V
= 0 V
GS
10
0
5
10
15
20
25
5
V
V
DS
GS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
MTD5P06V
10
9
60
54
48
42
36
30
100
V
T = 25°C
D
GS
J
I = 5 A
QT
8
V
V
= 30 V
= 10 V
DD
GS
t
r
7
Q2
Q1
t
d(off)
6
t
f
5
10
t
d(on)
4
24
18
12
3
2
T = 25°C
D
J
I = 5 A
Q3
V
1
0
DS
6
0
1
1
10
R , GATE RESISTANCE (OHMS)
100
0
2
4
6
8
10
12
14
Q , TOTAL GATE CHARGE (nC)
g
G
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
5
T = 25°C
GS
J
4.5
V
= 0 V
4
3.5
3
2.5
2
1.5
1
0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the
maximum simultaneous drain−to−source voltage and drain
current that a transistor can handle safely when it is forward
biased. Curves are based upon maximum peak junction
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
temperature and a case temperature (T ) of 25°C. Peak
C
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance−General
Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
energy at currents below rated continuous I can safely be
exceed (T
− T )/(R ).
D
J(MAX)
C qJC
assumed to equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
MTD5P06V
SAFE OPERATING AREA
140
120
100
80
100
10
V
= 20 V
SINGLE PULSE
GS
I = 5 A
D
T = 25°C
C
100 ms
1 ms
60
1
10 ms
40
dc
R
LIMIT
DS(on)
20
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
25
50
75
100
125
150
175
0.1
1
10
100
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
T , STARTING JUNCTION TEMPERATURE (°C)
J
DS
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
(t) = r(t) R
q
JC
q
JC
0.05
0.02
0.01
SINGLE PULSE
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t
t
1
1
t
2
T
− T = P
C
R
(t)
q
JC
J(pk)
(pk)
DUTY CYCLE, D = t /t
1
2
0.01
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
di/dt
I
S
t
rr
t
a
t
b
TIME
0.25 I
t
p
S
I
S
Figure 14. Diode Reverse Recovery Waveform
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
4
DPAK (SINGLE GAUGE)
CASE 369C
ISSUE G
2
1
DATE 31 MAY 2023
3
SCALE 1:1
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
AYWW
XXX
XXXXXG
IC
Discrete
XXXXXX = Device Code
A
= Assembly Location
L
= Wafer Lot
STYLE 1:
STYLE 2:
PIN 1. GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
Y
WW
G
= Year
= Work Week
= Pb−Free Package
PIN 1. BASE
PIN 1. ANODE
2. CATHODE
3. ANODE
PIN 1. CATHODE
2. ANODE
3. GATE
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
2. COLLECTOR
3. EMITTER
3. SOURCE
4. DRAIN
4. COLLECTOR
4. CATHODE
4. ANODE
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
PIN 1. GATE
STYLE 8:
PIN 1. N/C
STYLE 9:
PIN 1. ANODE
2. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
3. ANODE
4. CATHODE
3. RESISTOR ADJUST
4. CATHODE
3. CATHODE
4. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10527D
DPAK (SINGLE GAUGE)
PAGE 1 OF 1
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