N01L63W2AB5IT [ONSEMI]
1Mb Ultra-Low Power Asynchronous CMOS SRAM 64K × 16 bit; 1MB超低功耗异步SRAM CMOS 64K × 16位型号: | N01L63W2AB5IT |
厂家: | ONSEMI |
描述: | 1Mb Ultra-Low Power Asynchronous CMOS SRAM 64K × 16 bit |
文件: | 总10页 (文件大小:218K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
N01L63W2A
1Mb Ultra-Low Power Asynchronous CMOS SRAM
64K × 16 bit
Features
• Single Wide Power Supply Range
2.3 to 3.6 Volts
Overview
The N01L63W2A is an integrated memory device
containing a 1 Mbit Static Random Access Memory
organized as 65,536 words by 16 bits. ON
Semiconductor’s advanced CMOS technology to
provide both high-speed performance and ultra-low
power. The device operates with two chip enable
(CE1 and CE2) controls and output enable (OE) to
allow for easy memory expansion. Byte controls
(UB and LB) allow the upper and lower bytes to be
accessed independently and can also be used to
deselect the device. The N01L63W2A is optimal
for various applications where low-power is critical
such as battery backup and hand-held devices.
The device can operate over a very wide
• Very low standby current
2.0µA at 3.0V (Typical)
• Very low operating current
2.0mA at 3.0V and 1µs (Typical)
• Very low Page Mode operating current
0.8mA at 3.0V and 1µs (Typical)
• Simple memory control
Dual Chip Enables (CE1and CE2)
Byte control for independent byte operation
Output Enable (OE) for memory expansion
• Low voltage data retention
Vcc = 1.8V
• Very fast output enable access time
o
o
30ns OE access time
temperature range of -40 C to +85 C and is
available in JEDEC standard packages compatible
with other standard 64Kb x 16 SRAMs.
• Automatic power down to standby mode
• TTL compatible three-state output driver
• Compact space saving BGA package avail-
able
Product Family
Standby
Current
Power
Supply
(Vcc)
Operating
Current (Icc),
Typical
Operating
Part Number
Package Type
Speed
Temperature
(ISB), Typical
N01L63W2AB
N01L63W2AT
N01L63W2AB2
N01L63W2AT2
48 - BGA
44 - TSOP II
55ns @ 2.7V
70ns @ 2.3V
-40oC to +85oC
2.3V - 3.6V
2 µA
2 mA @ 1MHz
48 - BGA Green
44 - TSOP II Green
Pin Configuration
Pin Descriptions
1
2
3
A0
4
A1
5
A2
6
A4
1
PIN
A5
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A3
2
ONE
A6
A2
3
LB
OE
CE2
A7
A
B
C
D
E
F
Pin Name
A0-A15
WE
CE1, CE2
OE
LB
UB
I/O0-I/O15
Pin Function
A1
4
OE
A0
5
UB
I/O8
A3
A4
A6
A7
NC
I/O0
UB
CE1
CE1
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
6
Address Inputs
Write Enable Input
Chip Enable Input
LB
7
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
CE2
A8
I/O9 I/O10 A5
I/O1 I/O2
I/O3 VCC
I/O4 VSS
8
9
VSS I/O11
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
Output Enable Input
Lower Byte Enable Input
Upper Byte Enable Input
Data Inputs/Outputs
VCC I/O12
I/O14 I/O13 A14
NC
A15 I/O5 I/O6
I/O15
NC
A12
A9
A13
A10
I/O7
NC
NC
A8
WE
A11
G
H
A9
VCC
VSS
NC
Power
Ground
Not Connected
A10
A11
48 Pin BGA (top)
6 x 8 mm
NC
©2008 SCILLC. All rights reserved.
July 2008 - Rev. 9
Publication Order Number:
N01L63W2A/D
N01L63W2A
Functional Block Diagram
Word
Address
Inputs
Address
Decode
Logic
A0 - A3
Input/
Output
Mux
Page
4K Page
x 16 word
x 16 bit
Address
Inputs
Address
Decode
Logic
I/O0 - I/O7
A4 - A15
and
RAM Array
Buffers
I/O8 - I/O15
CE1
CE2
WE
OE
Control
Logic
UB
LB
Functional Description
1
CE1
CE2
WE
OE
UB
LB
MODE
POWER
I/O0 - I/O15
Standby2
Standby2
H
X
L
L
L
L
X
L
H
H
H
H
X
X
X
L
X
X
X
X3
L
X
X
H
L1
L1
L1
X
X
H
L1
L1
L1
High Z
High Z
High Z
Data In
Data Out
High Z
Standby
Standby
Standby
Active
Standby
Write3
Read
Active
H
H
Active
H
Active
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7
are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown.
2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
1
Capacitance
Item
Symbol
CIN
Test Condition
Min
Max
8
Unit
pF
VIN = 0V, f = 1 MHz, TA = 25oC
VIN = 0V, f = 1 MHz, TA = 25oC
Input Capacitance
I/O Capacitance
CI/O
8
pF
1. These parameters are verified in device characterization and are not 100% tested
Rev. 9 | Page 2 of 10 | www.onsemi.com
N01L63W2A
1
Absolute Maximum Ratings
Item
Symbol
VIN,OUT
VCC
Rating
–0.3 to VCC+0.3
–0.3 to 4.5
500
Unit
V
Voltage on any pin relative to VSS
Voltage on VCC Supply Relative to VSS
Power Dissipation
V
PD
mW
oC
oC
oC
TSTG
Storage Temperature
–40 to 125
TA
Operating Temperature
-40 to +85
260oC, 10sec
TSOLDER
Soldering Temperature and Time
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Typ1
Item
Symbol
Test Conditions
Min.
Max
Unit
VCC
VDR
VIH
VIL
Supply Voltage
Data Retention Voltage
Input High Voltage
2.3
1.8
3.0
3.6
V
V
Chip Disabled3
VCC+0.3
0.6
1.8
V
Input Low Voltage
–0.3
V
VOH
VOL
ILI
IOH = 0.2mA
IOL = -0.2mA
VCC–0.2
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
V
0.2
0.5
0.5
V
VIN = 0 to VCC
µA
µA
ILO
OE = VIH or Chip Disabled
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
ICC1
ICC2
2.0
9.5
3.0
mA
mA
@ 1 µs Cycle Time2
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
Read/Write Operating Supply Current
14.0
@ 70 ns Cycle Time2
Page Mode Operating Supply Current
@ 70ns Cycle Time2 (Refer to Power
Savings with Page Mode Operation
diagram)
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0
ICC3
4
mA
mA
VCC=3.6 V, VIN=VIH or VIL
Chip Enabled, IOUT = 0,
f = 0
Read/Write Quiescent Operating Sup-
ply Current3
ICC4
3.0
VIN = VCC or 0V
Chip Disabled
Maximum Standby Current3
ISB1
2.0
20
10
µA
µA
tA= 85oC, VCC = 3.6 V
Vcc = 1.8V, VIN = VCC or 0
Chip Disabled, tA= 85oC
Maximum Data Retention Current3
IDR
1. Typical values are measured at Vcc=Vcc Typ., TA=25°C and not 100% tested.
2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive
output capacitance expected in the actual system.
3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all
inputs must be within 0.2 volts of either VCC or VSS
Rev. 9 | Page 3 of 10 | www.onsemi.com
N01L63W2A
Power Savings with Page Mode Operation (WE = V )
IH
Page Address (A4 - A15)
Word Address (A0 - A3)
Open page
Word 16
Word 1
Word 2
CE1
CE2
OE
LB, UB
Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal
organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power
saving feature.
The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open
and 16-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant
bits and addressing the 16 words within the open page, power is reduced to the page mode value which is
considerably lower than standard operating currents for low power SRAMs.
Rev. 9 | Page 4 of 10 | www.onsemi.com
N01L63W2A
Timing Test Conditions
Item
0.1VCC to 0.9 VCC
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5ns
0.5 VCC
CL = 30pF
-40 to +85 oC
Operating Temperature
Timing
2.3 - 3.6 V
2.7 - 3.6 V
Item
Symbol
Units
Min.
Max.
Min.
Max.
tRC
tAA
tCO
tOE
Read Cycle Time
70
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
70
70
35
70
55
55
30
55
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
t
LB, tUB
tLZ
10
5
10
5
tOLZ
tLBZ, tUBZ
tHZ
10
0
10
0
20
20
20
20
20
20
tOHZ
0
0
t
LBHZ, tUBHZ
tOH
0
0
10
70
50
50
50
40
0
10
55
40
40
40
40
0
tWC
tCW
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
tAW
tLBW, tUBW
tWP
tAS
Address Setup Time
tWR
Write Recovery Time
0
0
tWHZ
tDW
Write to High-Z Output
20
20
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
40
0
35
0
tDH
tOW
5
10
ns
Rev. 9 | Page 5 of 10 | www.onsemi.com
N01L63W2A
Timing of Read Cycle (CE1 = OE = V , WE = CE2 = V )
IL
IH
t
RC
Address
t
AA
t
OH
Previous Data Valid
Data Valid
Data Out
Timing Waveform of Read Cycle (WE=V )
IH
t
RC
Address
t
AA
t
HZ
CE1
CE2
t
CO
t
LZ
t
OHZ
t
OE
OE
t
OLZ
t
t
LB, UB
LB, UB
t
t
t
t
LBLZ, UBLZ
LBHZ, UBHZ
High-Z
Data Valid
Data Out
Rev. 9 | Page 6 of 10 | www.onsemi.com
N01L63W2A
Timing Waveform of Write Cycle (WE control)
t
WC
Address
t
WR
t
AW
CE1
CE2
t
CW
t
, t
LBW UBW
LB, UB
WE
t
t
AS
WP
t
t
DH
DW
High-Z
Data Valid
Data In
t
WHZ
t
OW
High-Z
Data Out
Timing Waveform of Write Cycle (CE1 Control)
t
WC
Address
t
t
AW
WR
t
CE1
CW
(for CE2 Control, use
inverted signal)
t
AS
t
, t
LBW UBW
LB, UB
WE
t
WP
t
t
DH
DW
Data Valid
Data In
t
LZ
t
WHZ
High-Z
Data Out
Rev. 9 | Page 7 of 10 | www.onsemi.com
N01L63W2A
44-Lead TSOP II Package (T44)
18.41±0.13
11.76±0.20
10.16±0.13
0.80mm REF
0.45
0.30
SEE DETAIL B
DETAIL B
1.10±0.15
o
o
0 -8
0.20
0.00
0.80mm REF
Note:
1. All dimensions in inches (Millimeters)
2. Package dimensions exclude molding flash
Rev. 9 | Page 8 of 10 | www.onsemi.com
N01L63W2A
Ball Grid Array Package
0.28±0.05
1.24±0.10
D
A1 BALL PAD
CORNER (3)
1. 0.35±0.05 DIA.
E
2. SEATING PLANE - Z
0.15
Z
0.05
Z
TOP VIEW
SIDE VIEW
1. DIMENSION IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER.
PARALLEL TO PRIMARY Z.
A1 BALL PAD
CORNER
SD
2. PRIMARY DATUM Z AND SEATING
PLANE ARE DEFINED BY THE
SPHERICAL CROWNS OF THE
SOLDER BALLS.
e
SE
3. A1 BALL PAD CORNER I.D. TO BE
MARKED BY INK.
K TYP
J TYP
e
BOTTOM VIEW
Dimensions (mm)
e = 0.75
BALL
D
E
MATRIX
TYPE
SD
SE
J
K
6±0.10
8±0.10
0.375
0.375
1.125
1.375
FULL
Rev. 9 | Page 9 of 10 | www.onsemi.com
N01L63W2A
Ordering Information
Part Number
Package
Shipping Method
N01L63W2AT5I
N01L63W2AT25I
N01L63W2AB5I
N01L63W2AB25I
N01L63W2AT5IT
N01L63W2AT25IT
N01L63W2AB5IT
N01L63W2AB25IT
Leaded 44-TSOP II
Green 44-TSOP II (RoHS Compliant)
Leaded 48-BGA
Green 48-BGA (RoHS Compliant)
Leaded 44-TSOP II
Green 44-TSOP II (RoHS Compliant)
Leaded 48-BGA
Tray
Tray
Tray
Tray
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Green 48-BGA (RoHS Compliant)
Revision History
Revision
Date
Change Description
A
Jan 2001
Initial preliminary release
Corrected Figure 1: TSOP Pin Configuration, pins 18-22. Modified ICC3, figure 8,
other minor edits
Modified timing table, changed access time to 55 ns
B
C
Mar 2001
April 2001
Part number change from EM064J16, modified Overview and Features, Added
Page Mode Operation diagram, revised Operating Characteristics table, Func-
tional Description table and Ordering Information diagram
D
Dec. 2001
E
F
G
H
9
Nov. 2002
Oct. 2004
Nov. 2005
Replaced Isb and Icc on Product Family table with typical values
Added Pb-Free and Green Package Option
Removed Pb-Free Pkg, added Green Pkg and RoHS Compliant
September 2006 Converted to AMI Semiconductor
July 2008
Converted to ON Semiconductor and new part numbers
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer's technical
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Rev. 9 | Page 10 of 10 | www.onsemi.com
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