N01S830HA_16 [ONSEMI]
1 Mb Ultra-Low Power Serial SRAM;
| 型号： | N01S830HA_16 |
| 厂家： | 
ONSEMI |
| 描述： | 1 Mb Ultra-Low Power Serial SRAM 静态存储器 |
| 文件： | 总13页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N01S830HA, N01S830BA
1 Mb Ultra-Low Power
Serial SRAM
Standard SPI Interface and Multiplex
DUAL and QUAD Interface
www.onsemi.com
Overview
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 1 Mb serially accessed
Static Random Access Memory, internally organized as 128 K words
by 8 bits. The devices are designed and fabricated using
ON Semiconductor’s advanced CMOS technology to provide both
high-speed performance and low power. The devices operate with a
single chip select (CS) input and use a simple Serial Peripheral
Interface (SPI) protocol. In SPI mode, a single data-in (SI) and
data-out (SO) line is used along with the clock (SCK) to access data
within the device. In DUAL mode, two multiplexed data-in/data-out
(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed
data-in/data-out (SIO0-SIO3) lines are used with the clock to access
the memory. The devices can operate over a wide temperature range of
−40°C to +85°C (+125°C for E−Temp) and are available in a 8-lead
TSSOP package. The N01S830xA device has two different variations,
a HOLD version that allows communication to the device to be paused
and a battery back-up (BBU) version to be used with a battery to retain
data when power is lost.
TSSOP8 3x4.4
CASE 948BH
PACKAGE CONFIGURATION
1
2
3
4
8
7
6
5
CS
SO / SIO1
NC / SIO2
VSS
VCC
HOLD / SIO3
SCK
SI / SIO0
HOLD Version
1
2
3
4
8
7
6
5
CS
SO / SIO1
NC
VCC
VBAT
SCK
Features
• Power Supply Range: 2.5 to 5.5 V
• Very Low Typical Standby Current < 4 mA at +85°C
• Very Low Operating Current < 10 mA
VSS
SI / SIO0
BBU Version
• Simple Serial Interface
ORDERING INFORMATION
♦ Single-bit SPI Access
♦ DUAL-bit and QUAD-bit SPI-like Access
†
Device
Package
Shipping
• Flexible Operating Modes
N01S830HAT22I
N01S830BAT22I
N01S830HAT22IT
N01S830BAT22IT
N01S830HAT22E
N01S830BAT22E
N01S830HAT22ET
N01S830BAT22ET
TSSOP−8
(Pb−Free)
♦ Word Mode
100 Units / Tube
♦ Page Mode
♦ Burst Mode (Full Array)
3000 / Tape
& Reel
TSSOP−8
(Pb−Free)
• High Frequency Read and Write Operation
♦ Clock Frequency up to 20 MHz
• Functional Options
TSSOP−8
(Pb−Free)
100 Units / Tube
♦ HOLD Pin for Pausing Operation
♦ VBAT Pin for Battery−Back up
• Built-in Write Protection (CS High)
3000 / Tape
& Reel
TSSOP−8
(Pb−Free)
• High Reliability
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
♦ Unlimited Write Cycles
• Temperature Ranges Supported
♦ Industrial (I): T = −40°C to +85°C
A
♦ Automotive (E): T = −40°C to +125°C
A
• These Devices are Pb−Free and are RoHS Compliant
♦ Green TSSOP
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
February, 2016 − Rev. 2
N01S830HA/D
N01S830HA, N01S830BA
Table 1. DEVICE OPTIONS
Device / Part Number
Temperature
Range
Power Supply
Speed
Package
Function
N01S830HAT22
HV 2.5 V − 5.5 V
20 MHz for I−Temp,
16 MHz E−Temp
TSSOP−8
I, E
HOLD
N01S830BAT22
HV 2.5 V − 5.5 V
20 MHz for I−Temp,
16 MHz E−Temp
TSSOP−8
I, E
BBU − Battery Back-up
Table 2. PIN NAMES
Pin Name
Pin Function
CS
Chip Select
Serial Clock
SCK
SI / SIO0
Data Input − SPI mode
Data Input/Output 0 − DUAL and QUAD mode
SO / SIO1
NC / SIO2
HOLD / SIO3
Data Output − SPI mode
Data Input/Output 1 − DUAL and QUAD mode
No Connect − SPI and DUAL mode
Data Input/Output 2 − QUAD mode
HOLD Version
HOLD Input − SPI and DUAL mode
Data Input/Output 3 − QUAD mode
VBAT
BBU Version
Battery Supply − SPI and DUAL mode
V
V
Power
CC
Ground
SS
Decode
Logic
SCK
CS
Interface
Circuitry
Control
Logic
SRAM
Array
SI / SIO0
SO / SIO1
Data Flow
Circuitry
SIO2
HOLD / SIO3
(HOLD Version)
Battery Controls
VBAT
(BBU Version)
Figure 1. Functional Block Diagram
Table 3. CONTROL SIGNAL DESCRIPTIONS
Mode
Used
Signal
Name
Description
CS
All
Chip Select
A low level selects the device and a high level puts the device in standby mode. If CS is brought
high during a program cycle, the cycle will complete and then the device will enter standby mode.
When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence
being started.
SCK
All
Serial Clock
Synchronizes all activities between the memory and controller. All incoming addresses, data and
instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of
SCK.
SI
SPI
SPI
Serial Data In
Receives instructions, addresses and data on the rising edge of SCK.
SO
Serial Data Out Data is transferred out after the falling edge of SCK.
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N01S830HA, N01S830BA
Table 3. CONTROL SIGNAL DESCRIPTIONS
Mode
Used
Signal
Name
Description
HOLD
SPI and
DUAL
Hold
A high level is required for normal operation. Once the device is selected and a serial sequence
is started, this input may be taken low to pause serial communication without resetting the serial
sequence. The pin must be brought low while SCK is low for immediate use. If SCK is not low,
the HOLD function will not be invoked until the next SCK high to low transition. The device must
remain selected during this sequence. SO is high-Z during the Hold time and SI and SCK are
inputs are ignored. To resume operations, HOLD must be pulled high while the SCK pin is low.
Lowering the HOLD input at any time will take to SO output to High-Z.
VBAT
SPI and Battery Voltage Provides the battery power connection to retain data in battery backed mode.
DUAL
SIO0 - 1
DUAL
Serial Data
Input / Output
Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out
after the falling edge of SCK. The instruction must be set after power-up to enable the DUAL
access mode.
SIO0 - 3
QUAD
Serial Data
Input / Output
Receives instructions, addresses and data on the rising edge of SCK. Data is transferred out
after the falling edge of SCK. The instruction must be set after power-up to enable the QUAD
access mode.
Basic Operation
The 1 Mb serial SRAM is designed to interface directly
with a standard Serial Peripheral Interface (SPI) common on
many standard micro-controllers in the default state. It may
also interface with other non-SPI ports by programming
discrete I/O lines to operate the device.
The serial SRAM contains an 8-bit instruction register and
is accessed via the SI pin. The CS pin must be low and the
HOLD pin must be high for the entire operation. Data is
sampled on the first rising edge of SCK after CS goes low.
If the clock line is shared, the user can assert the HOLD input
and place the device into a Hold mode. After releasing the
HOLD pin, the operation will resume from the point where
it was held. The Hold operation is only supported in SPI and
DUAL modes.
By programming the device through a command
instruction, the dual and quad access modes may be initiated.
In these modes, multiplexed I/O lines take the place of the
SPI SI and SO pins and along with the CS and SCK control
the device in a SPI-like, two bit (DUAL) and four bit
(QUAD) wide serial manner. Once the device is put into
either the DUAL or QUAD mode, the device will remain
operating in that mode until powered down or the Reset
Mode operation is programmed.
The following table contains the possible instructions and
formats. All instructions, addresses and data are transferred
MSB first and LSB last.
Table 4. INSTRUCTION SET
Instruction
READ
Command
03h
Description
Read data from memory starting at selected address
WRITE
EQIO
02h
Write (program) data to memory starting at selected address
Enable QUAD I/O access
38h
EDIO
3Bh
Enable DUAL I/O access
RSTQIO
RDMR
WRMR
FFh
Reset from QUAD and DUAL to SPI I/O access
Read mode register
05h
01h
Write mode register
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N01S830HA, N01S830BA
DEVICE OPERATIONS
Read Operation
The serial SRAM Read operation is started by by enabling
CS low. First, the 8-bit Read instruction is transmitted to the
device through the SI (or SIO0-3) pin(s) followed by the
24-bit address with the 7 MSBs of the address being “don’t
care” bits and ignored. In SPI mode, after the READ
instruction and address bits are sent, the data stored at that
address in memory is shifted out on the SO pin after the
output valid time. Additional “dummy” clock cycles (four in
DUAL and two in QUAD) are required to follow the
instruction and address inputs prior to the data being driven
out on the SIO0-3 pins while operating in these two modes.
By continuing to provide clock cycles to the device, data
can continue to be read out of the memory array in
sequentially. The internal address pointer is automatically
incremented to the next higher address after each byte of
data is read out until the highest memory address is reached.
When the highest memory address is reached, 1FFFFh, the
address pointer wraps to the address 00000h. This allows the
read cycles to be continued indefinitely. All Read operations
are terminated by pulling CS high.
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
29 30 31 32 33 34 35 36 37 38 39
Instruction
24−bit address
23 22 21 20
SI
0
0
0
0
0
0
1
1
2
1
0
Data Out
High−Z
7
6
5
4
3
2
1
0
SO
Figure 2. SPI Read Sequence (Single Byte)
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
29 30 31 32 33 34 35 36 37 38 39
Instruction
24−bit address
SI
0
0
0
0
0
0
1
1
23 22 21 20
ADDR 1
2
1
0
Don’t Care
Data Out from ADDR 1
High−Z
7
6
5
4
3
2
1
0
SO
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Don’t Care
Data Out from ADDR 3
Data Out from ADDR 2
Data Out from ADDR n
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
...
Figure 3. SPI Read Sequence (Sequential Bytes)
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N01S830HA, N01S830BA
CS
SCK
0
1
2
3
4
5
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Instruction
24−bit address
Data out
H0 H0 L0 L0 H1 H1 L1 L1
MSB
C3 C2 C1 C0 A11 A10
A3 A2 A1 A0
X
X
X
X
SIO[1:0]
MSB
Notes:
C[3:0] = 03h
H0 = 2 high order bits of data byte 0
L0 = 2 low order bits of data byte 0
H1 = 2 high order bits of data byte 1
L1 = 2 low order bits of data byte 1
Figure 4. DUAL Read Sequence
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Instruction
24−bit address
Data out
H0 L0 H1 L1 H2 L2 H3 L3
MSB
SIO[3:0]
C1 C0 A5 A4 A3 A2 A1 A0
MSB
X
X
Notes:
C[1:0] = 03h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 5. QUAD Read Sequence
Write Operation
The serial SRAM WRITE is selected by enabling CS low.
First, the 8-bit WRITE instruction is transmitted to the
device followed by the 24-bit address with the 7 MSBs being
don’t care. After the WRITE instruction and addresses are
sent, the data to be stored in memory is shifted in on the SI
pin.
If operating in page mode, after the initial word of data is
shifted in, additional data words can be written as long as the
address requested is sequential on the same page. Simply
write the data on SI pin and continue to provide clock pulses.
The internal address pointer is automatically incremented to
the next higher address on the page after each word of data
is written in. This can be continued for the entire page length
of 32 words long. At the end of the page, the addresses
pointer will be wrapped to the 0 word address within the
page and the operation can be continuously looped over the
32 words of the same page. The new data will replace data
already stored in the memory locations.
If operating in burst mode, after the initial word of data is
shifted in, additional data words can be written to the next
sequential memory locations by continuing to provide clock
pulses. The internal address pointer is automatically
incremented to the next higher address after each word of
data is read out. This can be continued for the entire array
and when the highest address is reached, 1FFFFh, the
address counter wraps to the address 00000h. This allows
the burst write cycle to be continued indefinitely. Again, the
new data will replace data already stored in the memory
locations.
All WRITE operations are terminated by pulling CS high.
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N01S830HA, N01S830BA
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11
29 30 31 32 33 34 35 36 37 38 39
Data In to ADDR 1
Instruction
24−bit address
0
0
0
0
0
0
1
0
23 22 21 20
2
1
0
7
6
5
4
3
2
1
0
SI
ADDR 1
High−Z
SO
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data In to ADDR 2 Data In to ADDR 3
Data In to ADDR n
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
...
High−Z
Figure 6. SPI Write Sequence
CS
SCK
0
1
2
3
4
5
12 13 14 15 16 17 18 19 20 21
Instruction
24−bit address
Data in
A3 A2 A1 A0 H0 H0 L0 L0 H1 H1
MSB
C3 C2 C1 C0 A11 A10
Ln Ln
SIO1:0]
MSB
Notes:
C[3:0] = 02h
H0 = 2 high order bits of data byte 0
L0 = 2 low order bits of data byte 0
H1 = 2 high order bits of data byte 1
L1 = 2 low order bits of data byte 1
Figure 7. DUAL Write Sequence
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N01S830HA, N01S830BA
CS
SCK
0
1
2
3
4
5
6
7
8
9
10
11 12 13
Data in
Instruction
24−bit address
SIO[3:0]
C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2
MSB MSB
Hn Ln
Notes: C[1:0] = 02h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 8. QUAD Write Sequence
READ Mode Register (RDMR)
This instruction provides the ability to read the mode
register. The register may be read at any time including
during a Write operation. The Read Mode Register
operation is executed by driving CS low, then sending the
RDMR instruction to the device. Immediately after the
instruction, the device outputs data on the SO (SIO0-3)
pin(s). To complete the operation, drive CS high to terminate
the register read.
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Instruction
0
0
0
0
0
1
0
1
SI
Mode Register Data Out
High−Z
7
6
5
4
3
2
1
0
SO
Figure 9. SPI Read Mode Register Sequence (RDMR)
CS
SCK
0
1
2
3
4
5
6
7
Instruction
Mode Bits
Notes: C[3:0] = 05h
SIO[1:0]
C3 C2 C1 C0
H
H
L
L
MSB
Figure 10. DUAL Read Mode Register Sequence (RDMR)
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N01S830HA, N01S830BA
CS
SCK
0
1
2
3
Instruction Mode Bits
Notes: C[1:0] = 05h
SIO[3:0]
C1 C0
H
L
MSB
Figure 11. QUAD Read Mode Register Sequence (RDMR)
Write Mode Register (WRMR)
This instruction provides the ability to write the mode
register. The Write Mode Register operation is executed by
driving CS low, then sending the WRMR instruction to the
device. Immediately after the instruction, the data is driven
to the device on the SO (SIO0-3) pin(s). To complete the
operation, drive CS high to terminate the register write.
CS
SCK
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Instruction
Mode Register Data In
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High−Z
SO
Figure 12. SPI Write Mode Register Sequence
CS
SCK
0
1
2
3
4
5
6
7
Notes: C[3:0] = 01h
Instruction
Mode Bits
SIO[1:0]
C3 C2 C1 C0
H
H
L
L
MSB
Figure 13. DUAL Write Mode Register Sequence
CS
SCK
0
1
2
3
Instruction Mode Bits
Notes: C[1:0] = 01h
C1 C0
H
L
SIO[3:0]
MSB
Figure 14. QUAD Write Mode Register Sequence
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N01S830HA, N01S830BA
Battery Back-Up Operation
Table 5. MODE REGISTER
Bit
The Battery Back-Up function is available on the BBU
version of the serial SRAM. This version of the SRAM
cannot operate in the QUAD mode since the SIO3 input is
used for the VBAT connection. A standard coin cell battery
should be connected to the VBAT pin. On chip circuitry
Function
0
Hold Function
1 = Hold function disabled
0 = Hold function enabled (Default)
monitors the V pin and when it is determined that the main
1
2
3
4
5
6
Reserved
CC
V
CC
power supply is turning off, the device automatically
Reserved
switches the memory array to VBAT power input. When in
battery back-up mode and 3.0 to 3.4 V power supplied to the
VBAT input, memory data is retained in the SRAM array
and all existing interface and operating mode information is
retained.
Reserved
Reserved
Reserved
Operating Mode
Bit 7
Bit 6
VCC
0
1
0
1
0 = Word Mode
0 = Page Mode
1 = Burst Mode (Default)
1 = Reserved
CS
VBAT
7
SO
Serial
SRAM
NC
SCK
SI
Coin Cell Battery
3.0 to 3.4 V
Power-Up State
VSS
The serial SRAM enters a know state at power-up time.
The device is in low-power standby state with CS = 1. A low
level on CS is required to enter a active state.
Figure 15. Battery Back-Up Version Schematics
Table 6. ABSOLUTE MAXIMUM RATINGS
Item
Symbol
Rating
Units
V
Voltage on any pin relative to V
V
–0.3 to V + 0.3
SS
IN,OUT
CC
Voltage on V Supply Relative to V
V
CC
–0.3 to 5.5
500
V
CC
SS
Power Dissipation
P
D
mW
°C
Storage Temperature
T
STG
−40°C to 125°C
−40°C to +125°C
260°C, 10 sec
Ambient Temperature Under Bias
Soldering Temperature and Time
T
A
°C
T
°C
SOLDER
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 7. OPERATING CHARACTERISTICS (Industrial (I): T = −40°C to +85°C, Automotive (E): T = −40°C to +125°C)
A
A
Item
Symbol
Test Conditions
Min
2.5
1.0
Typ (Note 1)
Max
Units
V
Supply Voltage
V
5.5
CC
DR
Data Retention Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
V
V
V
IH
0.7 V
V + 0.3
CC
V
CC
V
IL
−0.3
V − 0.2
CC
0.1 V
V
CC
V
OH
I
= −0.4 mA
V
OH
V
OL
I
LI
I
OL
= 1 mA
0.2
1.0
1.0
10
V
CS = V , V = 0 to V
mA
mA
mA
CC
IN
CC
I
CS = V , V
= 0 to V
OUT CC
LO
CC
CC
I
f = 20 MHz, I
= 0, SPI / DUAL
OUT
f = 20 MHz, I
= 0, QUAD
20
OUT
Standby Current
I
SB
CS = V , V = V or V , I−Temp
4
10
mA
CC
IN
SS
CC
CS = V , V = V or V , E−Temp
20
CC
IN
SS
CC
1. Typical values are measured at V = V Typ., T = 25°C and are not 100% tested.
CC
CC
A
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N01S830HA, N01S830BA
Table 8. CAPACITANCE (Note 2)
Item
Input Capacitance
I/O Capacitance
Symbol
Test Conditions
Min
Max
7
Units
pF
C
V
V
= 0 V, f = 1 MHz, T = 25°C
IN
IN
A
C
= 0 V, f = 1 MHz, T = 25°C
7
pF
I/O
IN
A
2. These parameters are verified in device characterization and are not 100% tested.
Table 9. TIMING TEST CONDITIONS
Item
Input Pulse Level
Value
0.1 V to 0.9 V
CC
CC
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
5 ns
0.5 V
CC
CL = 30 pF
Industrial (I): −40°C to +85°C
Operating Temperature
Automotive (E): −40°C to +125°C
Table 10. TIMING
I−Temp
E−Temp
Min
Max
20
Min
Max
16
Characteristic
Clock Frequency
Symbol
Units
MHz
ns
f
CLK
Clock Rise Time
t
R
20
20
Clock Fall Time
t
F
20
20
ns
Clock High Time
t
25
25
25
25
50
25
5
32
32
32
32
50
32
5
ns
HI
Clock Low Time
t
LO
ns
Clock Delay Time
CS Setup Time
t
ns
CLD
CSS
CSH
CSD
t
ns
CS Hold Time
t
t
ns
CS Disable Time
SCK to CS
ns
t
ns
SCS
Data Setup Time
Data Hold Time
t
10
10
10
10
ns
SU
t
ns
HD
Output Valid From Clock Low
Output Hold Time
Output Disable Time
HOLD Setup Time
HOLD Hold Time
HOLD Low to Output High−Z
HOLD High to Output Valid
t
25
20
32
20
ns
V
t
0
0
ns
HO
t
ns
RDIS
t
10
10
10
10
10
10
ns
HS
t
ns
HH
t
HZ
ns
t
50
50
ns
HV
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N01S830HA, N01S830BA
tCSD
tCLD
CS
tR
tF
tCSH
tSCS
tCSS
SCK
tSU
tHD
MSB in
LSB in
SI
High−Z
SO
Figure 16. SPI Input Timing
CS
tLO tHI
tCSH
SCK
tV
MSB out
tDIS
SO
SI
LSB out
Don’t Care
Figure 17. SPI Output Timing
CS
tHS
tHH
tHS
SCK
SO
tHH
n
tHV
High−Z
n+2
n+1
tHZ
n
n−1
tSU
Don’t Care
n
n−1
SI
n+2
n+1
n
HOLD
Figure 18. SPI Hold Timing
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N01S830HA, N01S830BA
tCSD
tCLD
CS
SCK
SI0
tR
tF
tCSH
tSCS
tCSS
tSU
tHD
MSB in
LSB in
Figure 19. QUAD Input Timing
CS
tLO tHI
tCSH
SCK
SIO
tV
MSB out
tDIS
LSB out
Figure 20. QUAD Output Timing
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N01S830HA, N01S830BA
PACKAGE DIMENSIONS
TSSOP8 3x4.4 / TSSOP8 (225 mil)
CASE 948BH
ISSUE O
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