N21C21ASNDT3G_技术文档

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1 Kb 1-Wire EPROM

Add-Only Memory

N21C21A

Description

The N21C21A is a 1K−bit serial EPROM containing a factory−

programmed, unique 48−bit identification number, 8−bit CRC

generation, and the 8−bit family code (09h). A 64−bit status register

controls write protection and page redirection.

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The N21C21A 1−wire interface requires only a single connection

and a ground return. The DATA pin is also the sole power source for

the N21C21A.

6

1

The small surface−mount package options saves printed−circuit−

board space, while the low cost makes it ideal for applications such as

battery pack configuration parameters, record maintenance, asset

tracking, product−revision status, and access−code security.

SOT−23

SN SUFFIX

CASE 527AG

UDFN6

MU SUFFIX

CASE 517AP

Features

PIN DESCRIPTIONS

• 1024 Bits of One−Time Programmable (OTP) EPROM For Storage

Of User−Programmable Configuration Data

DQ

1

• Factory−Programmed Unique 64−Bit Identification Number

• Single−Wire Interface to Reduce Circuit Board Routing

3

VSS

2

• Synchronous Communication Reduces Host Interrupt Overhead

• No Standby Power Required

SOT23 (Top View)

Pin Description

• 8 byte RAM Buffer (Scratch Pad)

• Available in a 3−Pin SOT−23

• This is a Pb−Free Device

Pin Number

1

2

3

DQ − DATA Serial I/O

VSS

Applications

• Security Encoding

• Inventory Tracking

• Product−Revision Maintenance

• Battery−Pack Identification

1

DQ

VSS

UDFN6 (Top View)

Pin Description

Pin Number

1

2

3

4

5

6

Do not connect (NC)

DQ − DATA Serial I/O

Do not connect (NC)

VSS

Do not connect (NC)

ORDERING INFORMATION

See detailed ordering and shipping information on page 13 of

this data sheet.

1

Publication Order Number:

June, 2020 − Rev. 1

N21C21A/D

N21C21A

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Typ

Max

12.5

40

Units

V

DC voltage applied to data, V

–0.3

PU

Low−level output current, I

mA

°C

OL

Operating free−air temperature, T

–20

–40

70

A

Communication free−air temperature, T

85

°C

A(Comm)

Junction temperature, T

125

°C

J

Storage temperature, T

–55

°C

stg

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 2. D.C. OPERATING CHARACTERISTICS (T = −40°C to +85°C, VPU = 2.65 V to 5.5 V)

A

Symbol

Parameter

Pull−up Voltage

Test Conditions

Min

Typ

Max

5.5

20

Unit

V

PU

2.65

I

Supply current

V

PU

= 5.5 V

mA

V

DATA

V

OL

Low−level output voltage

Logic 0, V = 5.5 V, I = 4 mA, DQ pin

0.4

5.5

4

PU

OL

Logic 0, V = 2.65 V, I = 2 mA

PU

OL

V

OH

High−level output voltage

Low−level output current (sink)

Low−level input voltage

High−level input voltage

Programming voltage

Logic 1

V

PU

I

OL

V

OL

= 0.4 V, DQ pin

Logic 0

mA

V

IL

0.8

V

IH

Logic 1

2.2

V

11.5

12

V

PP

PU

R

Serial communication interface

pull−up resistance

5

kW

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. Tested initially and after a design or process change that affects this parameter

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N21C21A

Table 3. A.C. CHARACTERISTICS (T = −40°C to +85°C, VPU = 2.65 V to 5.5 V)

A

Symbol

Parameter

Min

60

1

Max

120

15

Unit

ms

t

c

Bit cycle time

t

Write start cycle

Write data setup

Write data hold

Recovery time

ms

WSTRB

t

15

ms

WDSU

WSTRB

t

60

t_c

ms

WDH

t

1

5

1

ms

rec

t

Read start cycle

13

60

ms

RSTRB

t

Output data delay

t

RSTRB

ODD

t

Output data hold

17

ODHO

t

Reset time

480

15

RST

PPD

t

Presence pulse delay

Presence pulse

60

t

60

240

PP

EPROG

t

EPROM programming time

EDN programming time

Program setup time

Program recovery time

Program rising−edge time

Program falling−edge time

2500

t

5000

EDN

t

5

PSU

t

PREC

t

5

PRE

t

PFE

t

480

RSTREC

Table 4. PIN CAPACITANCE

Symbol

Parameter

DATA Pin Capacitance

Test Conditions/Comments

T = 25°C

Min

Max

Unit

pF

C

800

IN/OUT

A

Detailed Description

Overview

read and write operations is derived from the DATA pin. An

internal capacitor stores energy while the signal line is high

and releases energy during the low times of the DATA pin,

until the pin returns high to replenish the charge on the

capacitor. A special manufacturer’s PROGRAM PROFILE

BYTE can be read to determine the programming profile

required to program the part.

The Functional Block Diagram shows the relationships

among the major control and memory sections of the

N21C21A. The N21C21A has three main data components:

a 64−bit factory−programmed ROM, including 8−bit family

code, 48−bit identification number and 8−bit CRC value,

1024−bit EPROM, and EPROM STATUS bytes. Power for

Figure 1. Functional Block Diagram

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N21C21A

Feature Description

1024−Bit EPROM

address redirection byte has some other hex value, the data

in the page corresponding to that redirection byte are invalid,

and the valid data can now be found at the ones complement

of the page address indicated by the hexadecimal value

stored in the associated page address redirection byte. A

value of FDh in the redirection byte for page 1, for example,

indicates that the updated data are now in page 2. The details

for reading and programming the EPROM status memory

portion of the N21C21A are given in the Memory/Status

Function Commands section.

Table 5 is a memory map of the 1024−bit EPROM section

of the N21C21A, configured as four pages of 32 bytes each.

The 8−byte RAM buffers are additional registers used when

programming the memory. Data are first written to the RAM

buffer and then verified by reading an 8−bit CRC from the

N21C21A that confirms proper receipt of the data. If the

buffer contents are correct, a programming command is

issued and an 8−byte segment of data is written into the

selected address in memory. This process ensures data

integrity when programming the memory. The details for

reading and programming the 1024−bit EPROM portion of

the N21C21A are in the Memory/Status Function

Commands section of this data sheet.

Table 6. EPROM STATUS BYTES

ADDRESS (HEX)

PAGE

00h

Write protection bits

BIT0 − write protect page 0

BIT1 − write protect page 1

BIT2 − write protect page 2

BIT3 − write protect page 3

BIT4 to 7−bitmap of used pages

Table 5. 1024−Bit EPROM DATA MEMORY MAP

ADDRESS(HEX)

0060−007F

PAGE

Page 3

Page 2

0040−005F

01h

02h

03h

04h

05h

06h

07h

Redirection byte for page 0

Redirection byte for page 1

Redirection byte for page 2

Redirection byte for page 3

Reserved

0020−003F

0000−001F

Page 1

Page 0

EPROM Status Memory

In addition to the programmable 1024−bits of memory are

64 bits of status information contained in the EPROM

STATUS memory. The STATUS memory is accessible with

separate commands. The STATUS bits are EPROM and are

read or programmed to indicate various conditions to the

software interrogating the N21C21A. The first byte of the

STATUS memory contains the write protect page bits, that

inhibit programming of the corresponding page in the

1024−bit main memory area if the appropriate

write−protection bit is programmed. Once a bit has been

programmed in the write protect page byte, the entire

32−byte page that corresponds to that bit can no longer be

altered but may still be read. The write protect bits may be

cleared by using the WRITE STATUS command.

Reserved

Factory programmed 00h

Error Checking

To validate the data transmitted from the N21C21A, the

host generates a CRC value from the data as they are

received. This generated value is compared to the CRC

value transmitted by the N21C21A. If the two CRC values

match, the transmission is error−free. The equivalent

8

5

4

polynomial function of this CRC is X + X + X + 1. Details

are found in the CRC Generation section of this data sheet.

Customizing the N21C21A

The next four bytes of the EPROM STATUS memory

contain the page address redirection bytes. Bits in the

EPROM status bytes can indicate to the host what page is

substituted for the page by the appropriate redirection byte.

The hardware of the N21C21A makes no decisions based on

the contents of the page address redirection bytes. This

feature allows the user’s software to make a data patch to the

EPROM by indicating that a particular page or pages should

be replaced with those indicated in the page address

redirection bytes. The ones complement of the new page

address is written into the page address redirection byte that

corresponds to the original (replaced) page. If a page address

redirection byte has an FFh value, the data in the main

memory that corresponds to that page are valid. If a page

The 64−bit ID identifies each N21C21A. The 48−bit serial

number is unique and programmed by the factory. The

default 8−bit family code is 09h; however, a different value

can be reserved on an individual customer basis. Contact

your ON Semiconductor for more information.

Bus Termination

Because the drive output of the N21C21A is an

open−drain, N−channel MOSFET, the host must provide a

source current or a 5−kW external pullup, as shown in the

typical application circuit.

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N21C21A

Device Functional Modes

The device is in active mode during communication or

while the DQ is kept at valid Vpu voltages.

for at least 480 ms. For more details, see the RESET and

PRESENCE PULSE section.

ROM Commands

Programming

READ ROM Command

Serial Communication

The READ ROM command sequence is the fastest

sequence that allows the host to read the 8−bit family code

and 48−bit identification number. The READ ROM

sequence starts with the host generating the RESET pulse of

at least 480 ms. The N21C21A responds with a PRESENCE

pulse. Next, the host continues by issuing the READ ROM

command, 33h, and then reads the ROM and CRC byte using

the READ signaling (see the READ and WRITE signals

A host reads, programs, or checks the status of the

N21C21A through the command structure of the DQ

interface.

Initialization

Initialization consists of two pulses, the RESET and the

PRESENCE pulses. The host generates the RESET pulse,

while the N21C21A responds with the PRESENCE pulse.

The host resets the N21C21A by driving the DATA bus low

section) during the data frame.

Reset and

Figure 2. READ ROM Sequence

SKIP ROM Command

whereas the READ MEMORY/Field CRC generates CRC

The SKIP ROM command, CCh, allows the host to access

the memory/status functions. The SKIP ROM command is

directly followed by a memory/status functions command.

when the end of the 1024−bit data memory is reached.

READ MEMORY/Page CRC

To read memory and generate the CRC at the 32−byte

page boundaries of the N21C21A, the SKIP ROM command

is followed by the READ MEMORY/Generate CRC

command, C3h, followed by the address low byte and then

the address high byte.

An 8−bit CRC of the command byte and address bytes is

computed by the N21C21A and read back by the host to

confirm that the correct command word and starting address

were received. If the CRC read by the host is incorrect, a

reset pulse must be issued and the entire sequence must be

repeated. If the CRC received by the host is correct, the host

issues read time slots and receives data from the N21C21A

starting at the initial address and continuing until the end of

a 32−byte page is reached. At that point, the host sends eight

additional read time slots and receive an 8−bit CRC that is

the result of shifting into the CRC generator all of the data

bytes from the initial starting byte to the last byte of the

current page. Once the 8−bit CRC has been received, data is

again read from the 1024−bit EPROM data field starting at

the next page. This sequence continues until the final page

and its accompanying CRC are read by the host. Thus each

page of data can be considered to be 33 bytes long, the 32

bytes of user−programmed EPROM data and an 8−bit CRC

that gets generated automatically at the end of each page.

Figure 3. SKIP ROM Sequence

Six memory/status function commands allow read and

modification of the 1024−bit EPROM data memory or the

64−bit EPROM status memory. There are two types of

READ MEMORY command, plus the WRITE MEMORY,

READ STATUS, and WRITE STATUS commands.

Additionally, the part responds to a PROGRAM PROFILE

byte command. The N21C21A responds to memory/status

function commands only after a part is issued a SKIP ROM

command.

READ MEMORY Commands

Two READ MEMORY commands are available on the

N21C21A. Both commands are used to read data from the

1024−bit EPROM data field. They are the READ

MEMORY/Page CRC and the READ MEMORY/Field

CRC commands. The READ MEMORY/Page CRC

generates CRC at the end any 32−byte page boundary

Table 7. READ MEMORY/PAGE CRC

Initialization and SKIP

ROM Command Sequence

READ MEMORY/

Generate CRC

Command

Address Low Byte Address High Byte

Read and

EPROM Memory and CRC

Verify CRC Byte Generated at 32−Byte

Page Boundaries

C3h

A0 A7

A8 A15

NOTE: Individual bytes of address and data are transmitted LSB first.

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5

N21C21A

READ MEMORY/Field CRC

issues read time slots and receives data from the N21C21A

starting at the initial address and continuing until the end of

the 1024−bit data field is reached or until a reset pulse is

issued. If reading occurs through the end of memory space,

the host may issue eight additional read time slots and the

N21C21A responds with an 8−bit CRC of all data bytes read

from the initial starting byte through the last byte of memory.

After the CRC is received by the host, any subsequent read

time slots appear as logical 1s until a reset pulse is issued.

Any reads ended by a reset pulse prior to reaching the end

of memory does not have the 8−bit CRC available.

To read memory without CRC generation on 32−byte

page boundaries, the SKIP ROM command is followed by

the READ MEMORY command, F0h, followed by the

address low byte and then the address high byte.

An 8−bit CRC of the command byte and address bytes is

computed by the N21C21A and read back by the host to

confirm that the correct command word and starting address

were received. If the CRC read by the host is incorrect, a

reset pulse must be issued and the entire sequence must be

repeated. If the CRC received by the host is correct, the host

Table 8. READ MEMORY/FIELD CRC

Initialization and SKIP

ROM Command

Sequence

READ MEMORY

Command

Address Low

Byte

Address High

Byte

Read and Read EPROM Memory

Verify CRC Until End of EPROM

Memory

Read and

Verify CRC

F0h

A0

A7

A8

A15

WRITE MEMORY Command

CRC is calculated and transmitted based on the 8 bytes of

data. If this CRC agrees with the CRC calculated by the host,

the host transmits the program command 5Ah and then

applies the programming voltage for at least 2500 ms or

The WRITE MEMORY command is used to program the

1024−bit EPROM memory field. The 1024−bit memory

field is programmed in 8−byte segments. Data is first written

into an 8−byte RAM buffer one byte at a time. The contents

of the RAM buffer is then ANDed with the contents of the

EPROM memory field when the programming command is

issued.

Figure 4 illustrates the sequence of events for

programming the EPROM memory field. After issuing a

SKIP ROM command, the host issues the WRITE

MEMORY command, 0Fh, followed by the low byte and

then the high byte of the starting address. The N21C21A

calculates and transmits an 8−bit CRC based on the WRITE

command and address.

t

. The contents of the RAM buffer is then logically

EPROG

ANDed with the contents of the 8−byte EPROM offset by

the starting address.

The starting address can be any integer multiple of eight

between 0000 and 007F (hex) such as 0000, 0008, and 0010

(hex).

The WRITE DATA MEMORY command sequence can

be terminated at any point by issuing a reset pulse except

during the program pulse period t

.

PROG

For both of these cases, the decision to continue

programming is made entirely by the host, because the

N21C21A is not able to determine if the 8−bit CRC

calculated by the host agrees with the 8−bit CRC calculated

by the N21C21A.

If at any time during the WRITE MEMORY process, the

CRC read by the host is incorrect, a reset pulse must be

issued, and the entire sequence must be repeated.

After the N21C21A transmits the CRC, the host then

transmits 8 bytes of data to the N21C21A. Another 8−bit

Prior to programming, bits in the 1024−bit EPROM data

field appear as logical 1s.

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6

N21C21A

Figure 4. WRITE MEMORY Command Flow

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7

N21C21A

READ STATUS Command

The READ STATUS command is used to read data from

through the final factory−programmed byte that contains the

the EPROM status data field. After issuing a SKIP ROM

command, the host issues the READ STATUS command,

AAh, followed by the address low byte and then the address

00h value.

This feature is provided because the EPROM status

information may change over time making it impossible to

program the data once and include an accompanying CRC

that is always valid. Therefore, the READ status command

supplies an 8−bit CRC that is based on (and always is

consistent with) the current data stored in the EPROM status

data field.

After the 8−bit CRC is read, the host receives logical 1s

from the N21C21A until a reset pulse is issued. The

READ STATUS command sequence can be ended at any

point by issuing a reset pulse.

high byte.

If the CRC read by the host is incorrect, a reset pulse must

be issued and the entire sequence must be repeated. If the

CRC received by the host is correct, the host issues read time

slots and receives data from the N21C21A starting at the

supplied address and continuing until the end of the EPROM

Status data field is reached. At that point, the host receives

an 8−bit CRC that is the result of shifting into the CRC

generator all of the data bytes from the initial starting byte

Table 9. READ STATUS COMMAND

Initialization and SKIP

ROM Command

Sequence

READ STATUS

Command

Address Low Byte Address High Byte Read and

Read STATUS

Verify CRC Memory Until End of Verify CRC

STATUS Memory

Read and

AAh

A0

A7

A8

A15

WRITE STATUS Command

(5Ah) is issued. After the program command is issued, then

the programming voltage, V is applied to the DATA pin

The WRITE STATUS command is used to program the

EPROM Status data field after the N21C21A has been

issued SKIP ROM command.

The flow chart in Figure 5 illustrates that the host issues

the WRITE STATUS command, 55h, followed by the

address low byte and then the address high byte the followed

by the byte of data to be programmed.

If the CRC read by the host is incorrect, a reset pulse must

be issued and the entire sequence must be repeated. If the

CRC received by the host is correct, the program command

PP

for period t . Prior to programming, the first seven bytes

PROG

of the EPROM STATUS data field appear as logical 1s. For

each bit in the data byte provided by the host that is set to a

logical 0, the corresponding bit in the selected byte of the

EPROM STATUS data field is programmed to a logical 0

after the programming pulse has been applied at the byte

location. The eighth byte of the EPROM STATUS byte data

field is factory−programmed to contain 00h.

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8

N21C21A

Figure 5. WRITE STATUS Command Flow

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9

N21C21A

After the programming pulse is applied and the data line

data byte was received correctly. If the CRC is incorrect, a

Reset Pulse must be issued and the Write Status command

sequence must be restarted. If the CRC is correct, the host

issues a programming pulse and the selected byte in memory

is programmed.

returns to V , the host issues eight read time slots to verify

PU

that the appropriate bits have been programmed. The

N21C21A responds with the data from the selected EPROM

STATUS address sent least significant bit first. This

response should be checked to verify the programmed byte.

If the programmed byte is incorrect, then the host must reset

the device and begin the write sequence again. If the

N21C21A EPROM data byte programming was successful,

the N21C21A automatically increments its address counter

to select the next byte in the STATUS MEMORY data field.

The least significant byte of the new two−byte address is also

loaded into the 8−bit CRC generator as a starting value. The

host issues the next byte of data using eight write time slots.

As the N21C21A receives this byte of data into the RAM

buffer, it also shifts the data into the CRC generator that has

been preloaded with the LSB of the current address and the

result is an 8−bit CRC of the new data byte and the LSB of

the new address. After supplying the data byte, the host reads

this 8−bit CRC from the N21C21A with eight read time slots

to confirm that the address incremented properly and the

For both of these cases, the decision to continue

programming the EPROM Status registers is made entirely

by the host, because the N21C21A is not able to determine

if the 8−bit CRC calculated by the host agrees with the 8−bit

CRC calculated by the N21C21A. If an incorrect CRC is

ignored and a program pulse is applied by the host, incorrect

programming could occur within the N21C21A. Also note

that the N21C21A always increments its internal address

counter after the receipt of the eight read time slots used to

confirm the programming of the selected EPROM byte. The

decision to continue is again made entirely by the host,

therefore if the EPROM data byte does not match the

supplied data byte but the master continues with the WRITE

STATUS command, incorrect programming could occur

within the N21C21A. The WRITE STATUS command

sequence can be ended at any point by issuing a reset pulse.

Table 10. COMMAND CODE SUMMARY

COMMAND (HEX)

DESCRIPTION

Read Serialization ROM and CRC

Skip Serialization ROM

Read Memory/Field CRC

Read EPROM Status

Read Memory/Page CRC

Write Memory


型号：	N21C21ASNDT3G
厂家：	ONSEMI
描述：	1K−bit serial EPROM containing a factory−programmed, unique 48−bit identification number with a 1-wire interface. 可编程只读存储器电动程控只读存储器
文件：	总16页 (文件大小：453K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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