N57M5114_18 [ONSEMI]
32âtap Digital Potentiometer;
| 型号： | N57M5114_18 |
| 厂家： | 
ONSEMI |
| 描述： | 32âtap Digital Potentiometer |
| 文件： | 总13页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
N57M5114
32‐tap Digital
Potentiometer (POT)
Description
The N57M5114 is a single digital POT designed as an electronic
replacement for mechanical potentiometers and trim pots. Ideal for
automated adjustments on high volume production lines, they are also
well suited for applications where equipment requiring periodic
adjustment is either difficult to access or located in a hazardous or
remote environment.
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The N57M5114 contains a 32-tap series resistor array connected
SOIC−8
V SUFFIX
CASE 751BD
MSOP−8
Z SUFFIX
CASE 846AD
between two terminals R and R . An up/down counter and decoder
that are controlled by three input pins, determines which tap is
H
L
connected to the wiper, R . The wiper setting, stored in nonvolatile
W
memory, is not lost when the device is powered down and is
automatically reinstated when power is returned. The wiper can be
adjusted to test new system values without affecting the stored setting.
Wiper-control of the N57M5114 is accomplished with three input
control pins, CS, U/D, and INC. The INC input increments the wiper
in the direction which is determined by the logic state of the U/D input.
The CS input is used to select the device and also store the wiper
position prior to power down.
TDFN−8
VP2 SUFFIX
CASE 511AK
TSSOP−8
Y SUFFIX
CASE 948AL
The digital POT can be used as a three-terminal resistive divider or
as a two-terminal variable resistor. Digital POTs bring variability and
programmability to a wide variety of applications including control,
parameter adjustments, and signal processing.
PIN CONFIGURATIONS
1
V
CS
INC
U/D
CC
Features
R
R
L
H
R
• 32-position Linear Taper Potentiometer
• Non-volatile EEPROM Wiper Storage
• Low Standby Current
GND
W
SOIC (V), MSOP (Z)
1
• Single Supply Operation: 2.5 V − 6.0 V
• Increment Up/Down Serial Interface
• Resistance Values: 10 kW, 50 kW and 100 kW
R
R
GND
CS
L
V
CC
W
INC
U/D
R
H
• Available in SOIC, TSSOP, MSOP and Space Saving
TSSOP (Y)
2 × 3 mm TDFN Packages
1
INC
U/D
V
CC
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
CS
R
R
R
H
L
Applications
GND
W
• Automated Product Calibration
• Remote Control Adjustments
• Offset, Gain and Zero Control
• Tamper-proof Calibrations
TDFN (VP2)
(Top Views)
• Contrast, Brightness and Volume Controls
• Motor Controls and Feedback Systems
• Programmable Analog Functions
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
June, 2018 − Rev. 4
N57M5114/D
N57M5114
DEVICE MARKING INFORMATION
MSOP
SOIC
TSSOP
A4RL
4YMXXX
RL4B
CAT5114VI
YMXXXX
ABMS
YMP
A4 = Device Code
R = Resistance
ABMS = 10 kW
2 = 10 kW
R = Resistance
ABMT = 50 kW
ABTH = 100 kW
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
P = Product Revision
4 = 50 kW
5 = 100 kW
2 = 10 kW
4 = 50 kW
5 = 100 kW
L = Assembly Location
4 = Lead Finish − NiPdAu
Y = Production Year (last digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of Assembly
XXX = Lot Number
L = Assembly Location
4 = Lead Finish − NiPdAu
I = Industrial Temp Range
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
TDFN
EF = 10 kW
HF = 50 kW
GW = 100 kW
XXXX = Last Four Digits of Assembly Lot Number
EFL
XXX
YM
XXX = Last Three Digits of Assembly Lot Number
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
Functional Diagram
R /V
R /V
H
H
H
H
5−Bit
Up/Down
Counter
31
30
U/D
INC
CS
V
CC
R /V
29
28
H
H
U/D
5−Bit
Nonvolatile
Memory
Control
and
Memory
32−
R /V
W W
Transfer Resistor
Gates Array
INC
CS
R /V
W
W
Position
Decoder
Power On
Recall
2
R /V
Store and
Recall
Control
Circuitry
L
L
1
0
V
CC
GND
GND
R /V
L L
R /V
R /V
L
L
W
W
Figure 1. General
Figure 2. Detailed
Figure 3. Electronic
Potentiometer
Implementation
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N57M5114
than the R terminal. Voltage applied to the R terminal
H
L
Table 1. PIN DESCRIPTIONS
Name
cannot exceed the supply voltage, V or go below ground,
CC
Function
GND. R and R are electrically interchangeable.
L
H
INC
U/D
Increment Control
Up/Down Control
CS: Chip Select
The chip select input is used to activate the control input of
the N57M5114 and is active low. When in a high state,
activity on the INC and U/D inputs will not affect or change
the position of the wiper.
R
Potentiometer High Terminal
Ground
H
GND
R
W
Wiper Terminal
R
Potentiometer Low Terminal
Chip Select
Device Operation
The N57M5114 operates like a digitally controlled
L
CS
potentiometer with R and R equivalent to the high and low
H
L
V
CC
Supply Voltage
terminals and
R
W
equivalent to the mechanical
potentiometer’s wiper. There are 32 available tap positions
including the resistor end points, R and R . There are 31
Pin Function
H
L
resistor elements connected in series between the R and R
INC: Increment Control Input
H
L
terminals. The wiper terminal is connected to one of the 32
The INC input moves the wiper in the up or down direction
determined by the condition of the U/D input.
taps and controlled by three inputs, INC, U/D and CS. These
inputs control a seven-bit up/down counter whose output is
decoded to select the wiper position. The selected wiper
position can be stored in nonvolatile memory using the INC
and CS inputs.
U/D: Up/Down Control Input
The U/D input controls the direction of the wiper movement.
When in a high state and CS is low, any high-to-low
transition on INC will cause the wiper to move one
With CS set LOW the N57M5114 is selected and will
respond to the U/D and INC inputs. HIGH to LOW
transitions on INC will increment or decrement the wiper
(depending on the state of the U/D input and seven−bit
counter). The wiper, when at either fixed terminal, acts like
its mechanical equivalent and does not move beyond the last
position. The value of the counter is stored in nonvolatile
memory whenever CS transitions HIGH while the INC input
is also HIGH. When the N57M5114 is powered-down, the
last stored wiper counter position is maintained in the
nonvolatile memory. When power is restored, the contents
of the memory are recalled and the counter is set to the value
stored.
increment toward the R terminal. When in a low state and
H
CS is low, any high-to-low transition on INC will cause the
wiper to move one increment towards the R terminal.
L
R : High End Potentiometer Terminal
H
R
H
is the high end terminal of the potentiometer. It is not
required that this terminal be connected to a potential greater
than the R terminal. Voltage applied to the R terminal
L
H
cannot exceed the supply voltage, V or go below ground,
CC
GND.
R : Wiper Potentiometer Terminal
W
R
W
is the wiper terminal of the potentiometer. Its position on
the resistor array is controlled by the control inputs, INC,
U/D and CS. Voltage applied to the R terminal cannot
With INC set low, the N57M5114 may be de-selected and
powered down without storing the current wiper position in
nonvolatile memory. This allows the system to always
power up to a preset value stored in nonvolatile memory.
W
exceed the supply voltage, V or go below ground, GND.
CC
R : Low End Potentiometer Terminal
L
R is the low end terminal of the potentiometer. It is not
L
required that this terminal be connected to a potential less
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3
N57M5114
Table 2. OPERATION MODES
INC
High to Low
High to Low
High
CS
Low
U/D
High
Low
X
Operation
Wiper toward H
Low
Wiper toward L
Low to High
Low to High
High
Store Wiper Position
No Store, Return to Standby
Standby
Low
X
X
X
R
H
C
H
R
WI
R
W
C
W
C
L
R
L
Figure 4. Potentiometer Equivalent Circuit
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Supply Voltage
V
V
CC
to GND
−0.5 to +7
Inputs
V
CS to GND
INC to GND
U/D to GND
H to GND
−0.5 to V +0.5
CC
−0.5 to V +0.5
V
V
CC
−0.5 to V +0.5
CC
−0.5 to V +0.5
V
CC
L to GND
−0.5 to V +0.5
V
CC
W to GND
−0.5 to V +0.5
V
CC
Operating Ambient Temperature
Industrial (‘I’ suffix)
°C
−40 to +85
+150
Junction Temperature
Storage Temperature
Lead Soldering (10 s max)
°C
°C
°C
−65 to 150
+300
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 4. RELIABILITY CHARACTERISTICS
Symbol
(Note 1)
Parameter
ESD Susceptibility
Latch-up
Test Method
Min
2000
Typ
Max
Units
V
V
MIL−STD−883, Test Method 3015
JEDEC Standard 17
ZAP
I
(Notes 1, 2)
100
mA
LTH
T
Data Retention
Endurance
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 1033
100
Years
Stores
DR
N
1,000,000
END
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V.
CC
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4
N57M5114
Table 5. DC ELECTRICAL CHARACTERISTICS (V = +2.5 V to +6 V unless otherwise specified)
CC
Symbol
Parameter
Conditions
Min
Typ
Max
Units
POWER SUPPLY
V
I
Operating Voltage Range
Supply Current (Increment)
2.5
–
–
–
–
–
–
−
6.0
100
50
V
CC
V
V
= 6 V, f = 1 MHz, I = 0
mA
mA
mA
mA
mA
CC1
CC2
CC
W
= 6 V, f = 250 kHz, I = 0
–
CC
W
I
Supply Current (Write)
Programming, V = 6 V
–
1000
500
1
CC
V
CC
= 3 V
–
I
(Note 4)
Supply Current (Standby)
CS = V − 0.3 V
–
SB1
CC
U/D, INC = V − 0.3 V or GND
CC
LOGIC INPUTS
I
Input Leakage Current
V
V
= V
CC
–
–
–
–
–
–
10
mA
mA
V
IH
IN
I
Input Leakage Current
= 0 V
−10
IL
IN
V
IH2
CMOS High Level Input Voltage
CMOS Low Level Input Voltage
2.5 V ≤ V ≤ 6 V
V
CC
x 0.7
V
+ 0.3
CC
CC
V
−0.3
V
x 0.2
V
IL2
CC
POTENTIOMETER CHARACTERISTICS
R
Potentiometer Resistance
−10 Device
−50 Device
−00 Device
10
50
kW
POT
100
Pot. Resistance Tolerance
20
%
V
V
RH
Voltage on R pin
0
0
V
H
CC
CC
V
RL
Voltage on R pin
V
V
L
Resolution
3.2
%
INL
Integral Linearity Error
Differential Linearity Error
Wiper Resistance
0.5
LSB
LSB
W
DNL
0.25
200
400
4.4
R
WI
V
V
= 5 V, I = 1 mA
70
CC
W
= 2.5 V, I = 1 mA
150
W
CC
W
I
W
Wiper Current
−4.4
mA
TC
TC of Pot Resistance
Ratiometric TC
300
ppm/°C
ppm/°C
nV/√Hz
pF
RPOT
TC
20
RATIO
V
Noise
100 kHz / 1 kHz
8/24
8/8/25
1.7
N
C /C /C
H
Potentiometer Capacitances
Frequency Response
L
W
fc
Passive Attenuator, 10 kW
MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to V + 1 V.
CC
5. I = source or sink.
W
6. These parameters are periodically sampled and are not 100% tested.
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N57M5114
Table 6. AC TEST CONDITIONS
V
CC
Range
2.5 V ≤ V ≤ 6 V
CC
Input Pulse Levels
0.2 x V to 0.7 x V
CC
CC
Input Rise and Fall Times
Input Reference Levels
10 ns
0.5 x V
CC
Table 7. AC OPERATING CHARACTERISTICS (V = +2.5 V to +6.0 V, V = V , V = 0 V, unless otherwise specified)
CC
H
CC
L
Symbol
Parameter
Min
100
50
100
250
250
1
Typ (Note 7)
Max
−
Units
ns
t
CI
t
DI
t
ID
CS to INC Setup
U/D to INC Setup
U/D to INC Hold
INC LOW Period
INC HIGH Period
−
−
−
−
−
−
−
−
1
−
−
–
5
−
ns
−
ns
t
−
ns
IL
IH
IC
t
t
−
ns
INC Inactive to CS Inactive
CS Deselect Time (NO STORE)
CS Deselect Time (STORE)
−
ms
t
t
100
10
−
−
ns
CPH
CPH
−
ms
ms
t
IW
INC to V
Change
5
OUT
t
INC Cycle Time
1
−
ms
CYC
t , t (Note 8) INC Input Rise and Fall Time
−
500
1
ms
R
F
t
(Note 8)
Power-up to Wiper Stable
Store Cycle
–
ms
ms
PU
t
–
10
WR
7. Typical values are for T = 25°C and nominal supply voltage.
A
8. This parameter is periodically sampled and not 100% tested.
9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.
CS
(store)
t
CYC
t
t
IC
CPH
t
CI
t
IL
t
IH
90%
90%
10%
INC
U/D
t
DI
t
ID
t
F
t
R
(3)
t
IW
MI
R
W
Figure 5. A.C. Timing
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N57M5114
APPLICATIONS INFORMATION
(a) resistive divider
(b) variable resistance
(c) two−port
Figure 6. Potentiometer Configuration
Applications
3
2
A
1
V (−)
+
–
1
R
R
4
3
+5 V
1
+5 V
8
R
1
2
1
7
R
R
A
6
+5 V
+5 V
4
8
pR
POT
8
7
4
R
–
+
A
9
10
2
2
1
7
3
5
3
5
4
R
(1−p)R
V
1
POT
O
3
8
R
2
11
B
555
N57M5114
4
R
2
A
2
R
–
+
R
3
4
6
N57M5114
6
5
+2.5 V
7
V (+)
2
2
1
0.01 mF
0.003 mF
1
C
0.01 mF
A = A = A = / LM6064
1
2
3
4
R = R = R = 5 kW
2
3
4
R
= 10 kW
POT
Figure 7. Programmable Instrumentation
Amplifier
Figure 8. Programmable Sq. Wave Oscillator (555)
+5 V
100 kW
8
2
N57M5114
1
7
V
OUT
V
O
(REG)
4
R
V
(UNREG)
1
IN
2952
6.8 mF
11 kW 0.1 mF
(1−p)R
pR
6
SHUTDOWN
1.23 V
1 MW
330 W
330 W
SD
FB
GND
3
R
2
5
+5 V
7
+5 V
7
1 mF
820 W
+5 V
8
2
2
3
2
3
10 k
–
+
–
+
A
A
1
2
3
V
O
1
7
6
6
R
I
S
3
4
4
5
N57M5114
10 kW
6
4
LT1097
+2.5 V
Figure 9. Programmable Voltage Regulator
Figure 10. Programmable I to V Convertor
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N57M5114
C
1
R3
0.001 mF
100 kW
C
1 mF
2
R1
+5 V
7
2
V
S
–
+
50 kW
0.001 mF
V
O
+5 V
8
6
R2
4
3
A
1
2
10 kW
1
7
+2.5 V
N57M5114
4
Figure 11. Programmable Bandpass Filter
+5 V
IC1
393
IC2
74HC132
R
V
LL
1
3
2
–
+
1
7
OSC
CLO
3
6
R
2
–
+
CHI
10 kW
R
0.1 mF
+5 V
5
V
UL
+5 V
IC3
N57M5114
+5 V
8
6
5
2
1
7
–
+
10 kW
3
V
O
2.5 ≤ V ≤ 5 V
O
AI
IC4
4
+2.5 V
V
S
0 ≤ V ≤ 2.5 V
S
Figure 12. Automatic Gain Control
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N57M5114
Table 8. ORDERING INFORMATION
Orderable Part Numbers
N57M5114WD10TG
†
Resistance Values (kW)
Package−Pin
Lead Finish
Shipping
10
50
N57M5114WD50TG
SOIC−8
NiPdAu
100 Units / Rail
N57M5114WD00TG
100
10
N57M5114VP2D10TG
N57M5114VP2D50TG
N57M5114VP2D00TG
N57M5114YD10TG
TDFN−8
2 x 3 mm
3000 / Tape &
Reel
50
NiPdAu
NiPdAu
NiPdAu
100
10
3000 / Tape &
Reel
N57M5114YD50TG
50
TSSOP−8
MSOP−8
N57M5114YD00TG
100
10
N57M5114ZD10TG
N57M5114ZD50TG
50
96 Units / Rail
N57M5114ZD00TG
100
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
10.All packages are RoHS-compliant (Pb-Free, Halogen-Free).
11. The standard lead finish is NiPdAu.
12.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office.
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N57M5114
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
SYMBOL
MIN
NOM
MAX
1.35
A
A1
b
1.75
0.25
0.51
0.25
0.10
0.33
0.19
c
E1
E
D
E
E1
e
4.80
5.80
3.80
5.00
6.20
4.00
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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N57M5114
PACKAGE DIMENSIONS
MSOP 8, 3x3
CASE 846AD
ISSUE O
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.10
0.15
0.95
0.38
0.23
3.10
5.00
3.10
0.05
0.75
0.22
0.13
2.90
4.80
2.90
0.10
0.85
c
D
3.00
4.90
E
E1
E
E1
e
3.00
0.65 BSC
0.60
L
0.40
0.80
L1
L2
θ
0.95 REF
0.25 BSC
0º
6º
TOP VIEW
D
A2
A
DETAIL A
A1
e
b
c
SIDE VIEW
END VIEW
q
L2
Notes:
L
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-187.
L1
DETAIL A
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N57M5114
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
MAX
0.80
0.05
0.65
A
A1
A2
A3
b
0.75
0.02
A2
0.55
0.20 REF
0.25
A3
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
FRONT VIEW
D2
E
1.40
3.00
E2
e
1.30
0.50 TYP
0.30
L
0.20
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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N57M5114
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
E
c
E1
D
3.00
6.40
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
0.50
0.75
0º
8º
θ
e
TOP VIEW
D
c
A2
A
q1
A1
L1
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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