NB100LVEP17DT [ONSEMI]
2.5V / 3.3V Quad Differential Driver/Receiver; 2.5V / 3.3V四路差分驱动器/接收器
| 型号： | NB100LVEP17DT |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V / 3.3V Quad Differential Driver/Receiver |
| 文件： | 总10页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB100LVEP17
2.5V / 3.3V Quad Differential
Driver/Receiver
Description
The NB100LVEP17 is a 4-bit differential line receiver. The design
incorporates two stages of gain, internal to the device, making it an
excellent choice for use in high bandwidth amplifier applications.
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MARKING
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
DIAGRAMS*
differential input is connected to V as a switching reference voltage.
BB
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V via a 0.01 ꢀ F capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
Inputs of unused gates can be left open and will not affect the
operation of the rest of the device.
N100
VP17
ALYWG
G
BB
Features
TSSOP−20
DT SUFFIX
CASE 948E
• Maximum Input Clock Frequency > 2.5 GHz Typical
• Maximum Input Data Rate > 2.5 Gb/s Typical
• 250 ps Typical Propagation Delay
• Low Profile QFN Package
24
1
N100
• PECL Mode Operating Range: V = 2.375 V to 3.8 V
CC
VP17
ALYWG
G
24
1
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
24 PIN QFN
MN SUFFIX
CASE 485L
with V = −2.375 V to −3.8 V
EE
• Q Output Will Default LOW with Inputs Open or at V
EE
• V Output
• Pb−Free Packages are Available
BB
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 7
NB100LVEP17/D
NB100LVEP17
D0
R1
D0
R1
Q0
R2
Q0
D1
R1
Q1
Q1
R2
R2
D1
R1
D2
R1
Q2
Q2
D2
R1
V
V
CC
EE
D3
R1
Q3
Q3
R2
V
D3
R1
BB
Figure 1. Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Default
State
TSSOP
QFN
Name
I/O
Description
1,20
13,18,21,
22,23
V
−
−
Positive Supply Voltage. All V Pins Must be Externally Connected
CC
CC
to Power Supply to Guarantee Proper Operation.
11
10
V
V
−
−
−
Negative Supply Voltage. All V Pins Must be Externally Con-
EE
BB
EE
nected to Power Supply to Guarantee Proper Operation.
10
9
−
ECL Reference Voltage Output.
2,4,6,8
3,5,7,9
1,3,5,7
2,4,6,8
D[0:3]
D[0:3]
ECL Input
ECL Input
Low
High
Noninverted Differential Inputs [0:3]. Internal 75 kꢁ to V
.
EE
Inverted Differential Inputs [0:3]. Internal 75 kꢁ to V and 37 kꢁ to
EE
V
.
CC
19,17,15,13
18,16,14,12
N/A
12,15,17,2
0
Q[0:3]
Q[0:3]
NC
ECL Output
−
−
−
Noninverted Differential Outputs [0:3]. Typically Terminated with
50 ꢁ to V = V − 2 V.
TT
CC
11,14,16,1
9
ECL Output
Inverted Differential Outputs [0:3]. Typically Terminated with 50 ꢁ to
= V − 2 V.
V
TT
CC
24
−
−
No Connect. The NC Pin is Electrically Connected to the Die and
“MUST BE” Left Open.
N/A
−
EP
Exposed Pad. (Note 1)
1. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive expose pad
CC
EE
on the package bottom (see case drawing) must be attached to a heat−sinking conduit.
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2
NB100LVEP17
Exposed Pad
(EP)
NC
V
V
V
CC
Q0 Q0
CC
CC
24
23
22
21
20
19
V
V
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V
EE
1
18
CC
D0
D0
D1
D1
D2
CC
20 19 18 17 16 15 14 13 12
11
2
3
4
5
17 Q1
Q1
Q2
16
15
14
13
NB100LVEP17
NB100LVEP17
Q2
V
1
2
3
4
5
6
7
8
9
10
6
D2
CC
V
D0 D0 D1 D1 D2 D2 D3 D3 V
BB
CC
7
8
9
10
11
12
D3 D3
V
V
Q3
Q3
BB
EE
Figure 3. QFN−24 Lead Pinout (Top View)
Figure 2. TSSOP−20 Lead Pinout (Top View)
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
(R1)
(R2)
75 kꢁ
37 kꢁ
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
TSSOP−20
QFN−24
Level 1
Level 1
Level 1
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
274 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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3
NB100LVEP17
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
Positive Mode Power Supply
V
V
6
CC
EE
I
EE
CC
Negative Mode Power Supply
= 0 V
−6
V
Positive Mode Input Voltage
Negative Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
EE
V w V
I
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
Sink/Source
BB
mA
°C
$0.5
−40 to +85
BB
TA
Operating Temperature Range
Storage Temperature Range
T
−65 to +150
°C
stg
ꢂ
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−3 (1S − Single Layer Test Board)
0 lfpm
500 lfpm
20 TSSOP
20 TSSOP
140
50
°C/W
°C/W
JA
ꢂ
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
24 QFN
24 QFN
37
32
°C/W
°C/W
JA
JEDEC 51−6 (2S2P Multilayer Test Board) with Filled Thermal
Vias
ꢂ
Thermal Resistance (Junction−to−Case)
Standard Board
20 TSSOP
24 QFN
23 to 41
11
°C/W
°C/W
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. DC CHARACTERISTICS, PECL V = 2.5 V; V = 0 V (Note 2)
CC
EE
−40°C
Typ
40
25°C
Typ
40
85°C
Typ
40
Min
30
Max
Min
Max
Min
Max
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
Unit
I
50
30
50
30
55
mA
EE
V
V
V
V
V
1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
OH
OL
555
1335
555
1.2
775
900
555
775
900
555
775
900
mV
Input HIGH Voltage (Single−Ended) (Note 4)
Input LOW Voltage (Single−Ended) (Note 4)
1620 1335
1620 1275
1620 mV
IH
875
2.5
555
1.2
875
2.5
555
1.2
875
2.5
mV
V
IL
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
IHCMR
I
I
Input HIGH Current (@ V
)
IH
150
150
150
ꢀ A
ꢀ A
IH
IL
Input LOW Current (@ V )
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary −0.125 V to +1.3 V.
CC
EE
3. All loading with 50 ꢁ to V = V − 2.0 V.
EE
CC
4. Do not use V at V < 3.0 V.
BB
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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NB100LVEP17
Table 5. DC CHARACTERISTICS, PECL V = 3.3 V; V = 0 V (Note 6)
CC
EE
−40°C
Typ
40
25°C
Typ
40
85°C
Typ
40
Min
30
Max
Min
Max
Min
Max
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Unit
I
50
30
50
30
55
mA
EE
V
V
V
V
V
V
2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
1355 1575 1700 1355 1575 1700 1355 1575 1700 mV
OH
OL
2135
1355
2420 2135
1675 1355
2420 2135
1675 1355
2420 mV
1675 mV
IH
IL
ECL Output Reference Voltage (Note 8)
1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
1.2
3.3
1.2
3.3
1.2
3.3
V
IHCMR
I
I
Input HIGH Current (@ V
)
IH
150
150
150
ꢀ A
ꢀ A
IH
IL
Input LOW Current (@ V )
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V . V can vary + 0.5 V to −0.3 V.
CC
EE
7. All loading with 50 ꢁ to V − 2.0 V.
CC
8. Single ended input operation is limited V ≥ 3.0 V in PECL mode.
CC
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 6. DC CHARACTERISTICS, NECL V = 0 V, V = −2.375 V to −3.8 V (Note 10)
CC
EE
−40°C
25°C
Typ
40
85°C
Typ
40
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
mA
mV
mV
mV
mV
mV
I
Negative Power Supply Current
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
30
40
50
30
50
30
55
EE
V
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1725 −1600 −1945 −1725 −1600 −1945 −1725 −1600
OH
OL
IH
V
V
V
V
Input HIGH Voltage (Single−Ended) −1165
−880 −1165
−1600 −1945
−880 −1165
−1600 −1945
−880
Input LOW Voltage (Single−Ended)
−1945
−1600
IL
ECL Output Reference Voltage
(Note 12)
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325
BB
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
V
+ 1.2
0.0
V
+ 1.2
0.0
V + 1.2
EE
0.0
V
IHCMR
EE
EE
I
I
Input HIGH Current (@ V
)
IH
150
150
150
ꢀ A
ꢀ A
IH
IL
Input LOW Current (@ V )
D
D
0.5
−150
0.5
−150
0.5
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V
.
CC
11. All loading with 50 ꢁ to V − 2.0 V.
CC
12.Single ended input operation is limited V ≤ −3.0V in NECL mode.
EE
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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NB100LVEP17
Table 7. AC CHARACTERISTICS V = 0 V; V = −2.375 V to −3.8 V or V = 2.375 V to 3.8 V; V = 0 V (Note 14)
CC
EE
CC
EE
−40°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figures 4, 5)
f
< 1 GHz 600 700
= 2 GHz 400 500
600 700
325 500
250 400
550 700
300 500
200 400
mV
OUTPP
in
in
f
f
= 2.5 GHz 300 400
in
t
t
,
Propagation Delay to Output Differential
ps
ps
PLH
PHL
D to Q, Q 200 250
325
200 250
325
225 300
350
t
Pulse Skew (Note 15)
Within Device Skew (Note 17)
Device−to−Device Skew (Note 17)
5
5
25
25
25
100
5
5
25
25
25
100
5
5
25
25
25
100
Skew
t
RMS Random Clock Jitter (Note 18)
Peak−to Peak Data Dependent Jitter
(Note 19)
f
= 2.5 GHz
= 1.5 Gb/s
= 2.5 Gb/s
0.5
5
5
1
15
15
0.5
5
5
1
15
15
0.5
5
5
1
15
15
ps
JITTER
in
f
f
in
in
V
Input Voltage Swing (Differential Configuration)
(Note 20)
150 800 1200 150 800 1200 150 800 1200 mV
INPP
t
t
Output Rise/Fall Times @ 50 MHz
(20% − 80%)
Q, Q
ps
r
f
125 175
225
140 190
240
150 200
250
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ꢁ to V − 2.0 V. Input edge rates 150 ps (20% − 80%).
CC
15.Pulse Skew = |t
− t
|
PLH
PHL
16.Worst case difference between Q0 and Q1 outputs.
17.Skew is measured between outputs under identical transitions.
18.Additive RMS jitter with 50% Duty Cycle Clock Signal at 2.5 GHz.
31
19.Peak−to−Peak jitter with input NRZ data at PRBS 2 −1 at 2.5 Gb/s with all inputs active.
20.Input voltage swing is a single−ended measurement operating in differential mode, with minimum propagation change of 50 ps.
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NB100LVEP17
850
750
650
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
Q AMP (mV)
550
450
350
250
RMS JITTER (ps)
1.5
1.0
0
0.5
1.0
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 2.5 V, Ambient Temperature
850
750
650
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
Q AMP (mV)
550
450
350
250
RMS JITTER (ps)
1.5
1.0
0
0.5
1.0
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 5. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at VCC = 3.3 V, Ambient Temperature
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 6. AC Reference Measurement
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7
NB100LVEP17
Z = 50 ꢁ
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 ꢁ
o
50 ꢁ
50 ꢁ
V
TT
V
= V − 2.0 V
TT
CC
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
Package
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
QFN−24
Shipping†
75 Units / Rail
75 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
92 Units / Rail
92 Units / Rail
NB100LVEP17DT
NB100LVEP17DTG
NB100LVEP17DTR2
NB100LVEP17DTR2G
NB100LVEP17MN
NB100LVEP17MNG
QFN−24
(Pb−Free)
NB100LVEP17MNR2
NB100LVEP17MNR2G
QFN−24
3000 Tape & Reel
3000 Tape & Reel
QFN−24
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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NB100LVEP17
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
V
0.10 (0.004)
T U
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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9
NB100LVEP17
PACKAGE DIMENSIONS
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
D
A
B
E
PIN 1
IDENTIFICATION
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.80
2X
A
A1
A2
A3
b
0.80
0.00
0.60
0.15
C
0.20 REF
2X
0.15
C
0.23
0.28
D
4.00 BSC
A2
D2
E
2.70
2.90
0.10
C
4.00 BSC
E2
e
2.70
2.90
A
0.50 BSC
0.08
C
L
0.35
0.45
A3
SEATING
PLANE
REF
A1
C
D2
e
L
7
12
6
1
13
E2
24X
b
18
24
19
e
0.10 C A B
0.05 C
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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