NB100LVEP221_06 [ONSEMI]
2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver; 2.5V / 3.3V 1:20差分HSTL / ECL / PECL时钟驱动器
| 型号： | NB100LVEP221_06 |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver |
| 文件： | 总11页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB100LVEP221
2.5V/3.3Vꢀ1:20 Differential
HSTL/ECL/PECL Clock Driver
Description
The NB100LVEP221 is a low skew 1−to−20 differential clock
driver, designed with clock distribution in mind, accepting two clock
sources into an input multiplexer. The two clock inputs are differential
ECL/PECL; CLK1/CLK1 can also receive HSTL signal levels. The
LVPECL input signals can be either differential configuration or
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MARKING
DIAGRAM*
single−ended (if the V output is used).
BB
The LVEP221 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device
and from device to device.
To ensure tightest skew, both sides of differential outputs should be
terminated identically into 50 W even if only one output is being used.
If an output pair is unused, both outputs may be left open
(unterminated) without affecting skew.
NB100
LVEP221
AWLYYWWG
LQFP−52
FA SUFFIX
CASE 848H
52
1
The NB100LVEP221, as with most other ECL devices, can be
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
operated from a positive V supply in LVPECL mode. This allows the
CC
WL
YY
WW
G
LVEP221 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power
supplies. For more information on PECL terminations, designers should
refer to Application Note AND8020/D.
*For additional marking information, refer to
Application Note AND8002/D.
The V pin, an internally generated voltage supply, is available to this
BB
device only. For single−ended LVPECL input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
V
V
may also rebias AC coupled inputs. When used, decouple V and
via a 0.01 mF capacitor and limit current sourcing or sinking to
BB
BB
CC
0.5 mA. When not used, V should be left open.
BB
Single−ended CLK input operation is limited to a V ≥ 3.0 V in
CC
LVPECL mode, or V ≤ −3.0 V in NECL mode.
EE
Features
• 15 ps Typical Output−to−Output Skew
• 40 ps Typical Device−to−Device Skew
• Jitter Less than 2 ps RMS
• Maximum Frequency > 1.0 GHz Typical
• Thermally Enhanced 52−Lead LQFP
• V Output
BB
• 540 ps Typical Propagation Delay
• LVPECL and HSTL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V = 0 V
EE
• NECL Mode Operating Range:
= 0 V with V = −2.375 V to −3.8 V
V
CC
EE
• Q Output will Default Low with Inputs Open or at V
• Pin Compatible with Motorola MC100EP221
• Pb−Free Packages are Available*
EE
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 7
NB100LVEP221/D
NB100LVEP221
39 38 37 36 35 34 33 32 31 30 29 28 27
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
V
Q12
Q12
Q13
Q13
Q14
Q14
Q15
CC0
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
NB100LVEP221
Q15
Q16
Q16
Q17
Q17
V
CC0
1
2
3
4
5
6
7
8
9
10 11 12 13
All V , V
, and V pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally
CCO EE
CC
conductive exposed pad on package bottom (see package case drawing) must be attached to a heat−sinking conduit, capable of transfer-
ring 1.2 Watts. This exposed pad is electrically connected to V internally.
EE
Figure 1. 52−Lead LQFP Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK0*, CLK0**
CLK1*, CLK1**
ECL/PECL Differential Inputs
ECL/PECL or HSTL Differential Inputs
ECL/PECL Differential Outputs
ECL/PECL Active Clock Select Input
Reference Voltage Output
Positive Supply
CLK0
CLK0
CLK1
CLK1
0
1
Q0:19, Q0:19
CLK_SEL*
20
20
Q0 − Q19
Q0 − Q19
V
BB
V
V
*
/V
CC CCO
EE***
Negative Supply
V
V
BB
Pins will default LOW when left open.
CLK_SEL
** Pins will default HIGH when left open.
***The thermally conductive exposed pad on the bottom of the
package is electrically connected to V internally.
EE
CC
Table 2. FUNCTION TABLE
V
EE
CLK_SEL
Active Input
L
H
CLK0, CLK0
CLK1, CLK1
Figure 2. Logic Diagram
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2
NB100LVEP221
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
Human Body Model
Machine Model
> 2 kV
> 200 V
> 2 kV
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Level 2
Pb−Free Pkg
Level 3
LQFP−52
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
533 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
6
CC
EE
I
EE
CC
V
V
= 0 V
−6
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ≤ V
6
−6
V
V
EE
CC
I
CC
V ≥ V
I
EE
I
Output Current
Continuous
Surge
50
100
mA
mA
out
I
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
(See Application Information)
0 lfpm
500 lfpm
52 LQFP
52 LQFP
35.6
30
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
(See Application Information)
0 lfpm
500 lfpm
52 LQFP
52 LQFP
3.2
6.4
°C/W
°C/W
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NB100LVEP221
Table 5. LVPECL DC CHARACTERISTICS V = 2.5 V; V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
130
85°C
Typ
145
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
I
100
125
150
104
156
116
174
EE
V
V
V
V
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
1355 1480 1605 1355 1480 1605 1355 1480 1605
OH
OL
555
1335
555
680
900
555
680
900
555
680
900
1620
900
Input HIGH Voltage (Single−Ended) (Note 4)
Input LOW Voltage (Single−Ended) (Note 4)
1620 1335
1620 1275
IH
900
555
900
555
IL
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
CLK0/CLK0
IHCMR
1.2
0.3
2.5
1.6
1.2
0.3
2.5
1.6
1.2
0.3
2.5
1.6
V
V
CLK1/CLK1
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
CLK
CLK
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary + 0.125 V to −1.3 V.
CC
EE
3. All outputs loaded with 50 W to V − 2.0 V.
CC
4. Do not use V at V < 3.0 V.
BB
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differen-
IHCMR
EE IHCMR
CC
IHCMR
tial input signal.
Table 6. LVPECL DC CHARACTERISTICS V = 3.3 V; V = 0 V (Note 6)
CC
EE
−40°C
25°C
Typ
130
85°C
Typ
145
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
mV
mV
mV
mV
I
100
125
150
104
156
116
174
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
2155 2280 2405 2155 2280 2405 2155 2280 2405
1355 1480 1700 1355 1480 1700 1355 1480 1700
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Reference Voltage (Note 8)
2135
1355
2420 2135
1700 1355
2420 2135
1700 1355
2420
1700
IH
IL
1775 1875 1975 1775 1875 1975 1775 1875 1975
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
CLK0/CLK0
IHCMR
1.2
0.3
3.3
1.6
1.2
0.3
3.3
1.6
1.2
0.3
3.3
1.6
V
V
CLK1/CLK1
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
CLK
CLK
0.5
−150
0.5
−150
0.5
−150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V . V can vary + 0.925 V to −0.5 V.
CC
EE
7. All outputs loaded with 50 W to V − 2.0 V.
CC
8. Single−ended input operation is limited V ≥ 3.0 V in LVPECL mode.
CC
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
NB100LVEP221
Table 7. LVNECL DC CHARACTERISTICS V = 0 V, V = −2.375 V to −3.8 V (Note 10)
CC
EE
−40°C
25°C
Typ
130
85°C
Typ
145
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
I
100
125
150
104
156
116
174
EE
V
V
V
V
V
V
Output HIGH Voltage (Note 11)
Output LOW Voltage (Note 11)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
OH
OL
−1945 −1820 −1600 −1945 −1820 −1600 −1945 −1820 −1600 mV
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Reference Voltage (Note 12)
−1165
−1945
−880 −1165
−1600 −1945
−880 −1165
−1600 −1945
−880
mV
IH
−1600 mV
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
V
V
+ 1.2
+ 0.3
0.0
V
V
+ 1.2
+ 0.3
0.0
V
V
+ 1.2
+ 0.3
0.0
−0.9
V
V
EE
EE
EE
EE
EE
EE
CLK0/CLK0
CLK1/CLK1
−0.9
−0.9
I
I
Input HIGH Current
150
150
150
mA
mA
IH
IL
Input LOW Current
CLK
0.5
0.5
−150
0.5
−150
CLK −150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V
.
CC
11. All outputs loaded with 50 W to V −2.0 V.
CC
12.Single−ended input operation is limited V ≤ −3.0V in NECL mode.
EE
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 8. HSTL DC CHARACTERISTICS V = 3.3 V; V = 0 V
CC
EE
0°C
25°C
85°C
Min
CLK1/CLK1 V +100
Typ
Max
1600
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
V
V
Input HIGH Voltage
IH
IL
X
V +100
x
1600
V +100
x
1600
mV
x
Input LOW Voltage
CLK1/CLK1
−300
V −100
x
−300
V −100
x
−300
V −100
x
mV
mV
Differential Configuration Cross
Point Voltage
680
900
680
900
680
900
I
I
Input HIGH Current
−150
150
−150
150
−150
150
mA
mA
IH
IL
Input LOW Current
CLK1
CLK1
−150
−250
−150
−250
−150
−250
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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5
NB100LVEP221
Table 9. AC CHARACTERISTICS V = 0 V; V = −2.375 to −3.8 V or V = 2.375 to 3.8 V; V = 0 V (Note 14)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Differential Output Voltage
(Figure 3)
Opp
f
< 50 MHz 550
< 0.8 GHz 550
< 1.0 GHz 500
700
700
700
600
550
500
700
700
700
600
500
400
700
700
600
mV
mV
mV
out
f
out
out
f
t
/t
Propagation Delay (Differential Configuration)
PLH PHL
CLK0−Qx
CLK1−Qx
540
590
600
640
540
590
660
710
540
590
750
800
ps
ps
t
t
Within−Device Skew (Note 15)
15
40
50
15
40
50
15
40
50
ps
ps
skew
Device−to−Device Skew (Note 16)
200
200
200
Random Clock Jitter (RMS) (Figure 3)
Input Swing (Differential Configuration)
1
2
1
2
1
2
ps
JITTER
V
PP
(Note 17) (Figure 4)
CLK0 400
CLK1 HSTL 300
800 1200 400
800 1000 300
800 1200 400
800 1000 300
800 1200 mV
800 1000 mV
DCO
t /t
Output Duty Cycle
49.5
100
50
50.5 49.5
300 100
50
50.5 49.5
300 150
50
50.5
350
%
Output Rise/Fall Time (20%−80%)
200
200
250
ps
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured with 750 mV source (LVPECL) or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to V −2 V.
CC
15.Skew is measured between outputs under identical transitions and conditions on any one device.
16.Device−to−Device skew for identical transitions, outputs and V levels.
CC
17.V is the differential configuration input voltage swing required to maintain AC characteristics.
PP
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6
NB100LVEP221
900
800
700
600
500
400
300
200
10
9
8
7
6
5
4
3
2
1
0
0.1
0.2
0.4
0.6
0.8
1.0
f
, INPUT FREQUENCY (GHz)
IN
Figure 3. Output Voltage (VOPP)/Jitter versus Input Frequency (VCC − VEE = 3.3 V @ 255C)
V
V
(LVPECL)
V
V
V
(HSTL)
CCO
CC
(DIFF)
IH
X
(DIFF)
IH
V
PP
V
V
IHCMR
PP
V (DIFF)
IL
V (DIFF)
IL
V
V
EE
EE
Figure 4. LVPECL Differential Input Levels
Figure 5. HSTL Differential Input Levels
Z = 50 W
o
Q
D
Receiver
Device
Driver
Device
Q
Z = 50 W
o
D
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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NB100LVEP221
APPLICATIONS INFORMATION
Using the thermally enhanced package of the
NB100LVEP221
supply enough solder paste to fill those vias and not starve
the solder joints. The attachment process for the exposed pad
package is equivalent to standard surface mount packages.
Figure 8, “Recommended solder mask openings”, shows a
recommended solder mask opening with respect to a 4 X 4
thermal via array. Because a large solder mask opening may
result in a poor rework release, the opening should be
subdivided as shown in Figure 8. For the nominal package
standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should
be considered.
The NB100LVEP221 uses a thermally enhanced 52−lead
LQFP package. The package is molded so that a portion of
the leadframe is exposed at the surface of the package
bottom side. This exposed metal pad will provide the low
thermal impedance that supports the power consumption of
the NB100LVEP221 high−speed bipolar integrated circuit
and will ease the power management task for the system
design. In multilayer board designs, a thermal land pattern
on the printed circuit board and thermal vias are
recommended to maximize both the removal of heat from
the package and electrical performance of the
NB100LVEP221. The size of the land pattern can be larger,
smaller, or even take on a different shape than the exposed
pad on the package. However, the solderable area should be
at least the same size and shape as the exposed pad on the
package. Direct soldering of the exposed pad to the thermal
land will provide an efficient thermal conduit. The thermal
vias will connect the exposed pad of the package to internal
copper planes of the board. The number of vias, spacing, via
diameters and land pattern design depend on the application
and the amount of heat to be removed from the package.
Maximum thermal and electrical performance is achieved
when an array of vias is incorporated in the land pattern.
The recommended thermal land design for
NB100LVEP221 applications on multi−layer boards
comprises a 4 X 4 thermal via array using a 1.2 mm pitch as
shown in Figure 7 providing an efficient heat removal path.
All Units mm
0.2
1.0
1.0
4.6
0.2
4.6
Thermal Via Array (4 X 4)
1.2 mm Pitch
Exposed Pad
Land Pattern
0.3 mm Diameter
Figure 8. Recommended Solder Mask Openings
All Units mm
Proper thermal management is critical for reliable system
operation. This is especially true for high−fanout and high
output drive capability products.
For thermal system analysis and junction temperature
calculation, the thermal resistance parameters of the
package are provided:
4.6
Table 10. Thermal Resistance *
lfpm
0
qJA 5C/W
35.6
qJC 5C/W
3.2
100
500
32.8
4.9
4.6
30.0
6.4
* Junction to ambient and Junction to board, four−conductor
layer test board (2S2P) per JESD 51−8
Thermal Via Array (4 X 4)
1.2 mm Pitch
0.3 mm Diameter
Exposed Pad
Land Pattern
These recommendations are to be used as a guideline,
only. It is therefore recommended that users employ
sufficient thermal modeling analysis to assist in applying the
general recommendations to their particular application to
assure adequate thermal performance. The exposed pad of
the NB100LVEP221 package is electrically shorted to the
Figure 7. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with
1 oz. copper via barrel plating. Solder wicking inside the via
may result in voiding during the solder process and must be
avoided. If the copper plating does not plug the vias, stencil
print solder paste onto the printed circuit pad. This will
substrate of the integrated circuit and V . The thermal land
EE
should be electrically connected to V
.
EE
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8
NB100LVEP221
ORDERING INFORMATION
Device
†
Package
Shipping
NB100LVEP221FA
NB100LVEP221FAG
LQFP−52
160 Units / Tray
160 Units / Tray
LQFP−52
(Pb−Free)
NB100LVEP221FAR2
NB100LVEP221FARG
LQFP−52
1500 / Tape & Reel
1500 / Tape & Reel
LQFP−52
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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NB100LVEP221
PACKAGE DIMENSIONS
LQFP 52 LEAD EXPOSED PAD PACKAGE
CASE 848H−01
ISSUE A
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MM.
3. DATUM PLANE ꢀE" IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING PLANE.
4. DATUM ꢀX", ꢀY" AND ꢀZ" TO BE DETERMINED AT
DATUM PLANE DATUM ꢀE".
4 PL
M
0.20 (0.008) T X−Y
Z
M/2
−Z−
AJ AJ
52
40
5. DIMENSIONS M AND L TO BE DETERMINED AT
SEATING PLANE DATUM ꢀT".
1
39
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLAND ꢀE".
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM D DIMENSION
BY MORE THAN 0.08 (0.003). DAMBAR CANNOT
BE LOCATED ON THE LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION
AND ADJACENT LEAD OR PROTRUSION 0.07
(0.003).
BASE
PLATING
METAL
AA
−X−
−Y−
L
B
J
AB
B/2
D
L/2
REF
13
27
M
0.08 (0.003)
Y
T−U
Z
MILLIMETERS
DIM MIN MAX
10.00 BSC
10.00 BSC
INCHES
MIN MAX
26
14
DETAIL AJ−AJ
A
B
0.394 BSC
0.394 BSC
A/2
C
1.30
0.22
0.45
1.50
0.40
0.75
0.051
0.009
0.018
0.059
0.016
0.030
0.20 (0.008) E X−Y
Z
D
A
F
G
0.65 BSC
1.00 REF
0.026 BSC
0.039 BSC
DETAIL AH
H
−E−
J
0.09
0.05
0.20
0.20
0.004
0.002
0.008
0.008
K
L
12.00 BSC
12.00 BSC
0.20 REF
0.472 BSC
0.472 BSC
0.008 REF
−T−
SEATING
PLANE
AG
AG
M
N
G 48 PL
0.10 (0.004) T
P
0
0
−−−
12 REF
12 REF
0.20
0.07
0.08
4.58
4.58
7
−−−
1.70
0
0
7
−−−
_
_
_
_
R
_
_
S
−−− 0.067
12 REF
12 REF
D 52 PL
V
_
_
V
M
W
AA
AB
AC
AD
AE
0.08 (0.003)
T
X−Y
Z
_
_
R
0.35
0.16
0.20
4.78
4.78
0.008
0.014
0.006
0.008
0.188
0.188
S
0.05 (0.002)
0.003
0.003
0.180
0.180
AC
AD
14
26
C
EXPOSED PAD
13
S
27
W
N
P
0.25
K
GAGE
PLANE
F
H
AE
DETAIL AH
1
39
52
40
VIEW AG−AG
http://onsemi.com
10
NB100LVEP221
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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