NB100LVEP56_06 [ONSEMI]
2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer; 2.5V / 3.3V ECL双差分2 ： 1多路复用器
| 型号： | NB100LVEP56_06 |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V / 3.3V ECL DUAL Differential 2:1 Multiplexer |
| 文件： | 总10页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB100LVEP56
2.5V / 3.3V ECL DUAL
Differential 2:1 Multiplexer
Description
The NB100LVEP56 is a dual, fully differential 2:1 multiplexer. The
differential data path makes the device ideal for multiplexing low
skew clock or differential data signals. The device features both
individual and common select inputs to address both data path and
random logic applications. Common and individual selects can accept
http://onsemi.com
MARKING
DIAGRAMS*
both LVECL and LVCMOS input voltage levels. Multiple V pins
BB
are provided.
The V pin, an internally generated voltage supply, is available to
this device only. For single−ended input operation, the unused
BB
N100
VP56
ALYWG
G
differential input is connected to V as a switching reference voltage.
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
TSSOP−20
DT SUFFIX
CASE 948E
to 0.5 mA. When not used, V should be left open.
BB
Features
• Maximum Input Clock Frequency > 2.5 GHz Typical
• Maximum Input Data Rate > 2.5 Gb/s Typical
• 525 ps Typical Propagation Delays
• Low Profile QFN Package
24
1
N100
VP56
ALYWG
G
24
1
24 PIN QFN
MN SUFFIX
CASE 485L
• PECL Mode Operating Range:
V
CC
= 2.375 V to 3.8 V with V = 0 V
EE
• NECL Mode Operating Range:
= 0 V with V = −2.375 V to −3.8 V
V
CC
EE
A
L
Y
W
G
= Assembly Location
• Separate, Common Select, and Individual Select
= Wafer Lot
= Year
(Compatible with ECL and CMOS Input Voltage Levels)
= Work Week
= Pb−Free Package
• Q Output Will Default LOW with Inputs Open or at V
EE
• Multiple V Outputs
BB
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
• Pb−Free Packages are Available
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 9
NB100LVEP56/D
NB100LVEP56
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
Default
State
TSSOP
QFN
Name
I/O
Description
14,20
3,9,18,19,
20
V
−
−
Positive Supply Voltage. All VCC Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
CC
11
3,8
1
15,24
6,12
4
V
−
−
Negative Supply Voltage. All VEE Pins must be Externally
Connected to Power Supply to Guarantee Proper Operation.
EE
V
,
−
−
ECL Reference Voltage Output
BB0
BB1
V
D0a
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Input
ECL Output
ECL Output
ECL Output
ECL Output
Low
High
Low
High
Low
High
Low
High
−
Noninverted Differential Data a Input to MUX 0. Internal 75 kW to
V
.
EE
2
5
D0a
Inverted Differential Data a Input to MUX 0. Internal 75 kW to V
EE
and 37 kW to V
.
CC
4
7
D0b
Noninverted Differential Data b Input to MUX 0. Internal 75 kW to
V
.
EE
5
8
D0b
Inverted Differential Data b Input to MUX 0. Internal 75 kW to V
EE
and 37 kW to V
.
CC
6
10
11
13
14
2
D1a
Noninverted Differential Data a Input to MUX 1. Internal 75 kW to
V
.
EE
7
D1a
Inverted Differential Data a Input to MUX 1. Internal 75 kW to V
EE
and 37 kW to V
.
CC
9
D1b
Noninverted Differential Data b Input to MUX 1. Internal 75 kW to
V
.
EE
10
19
18
13
12
17
16
15
N/A
D1b
Inverted Differential Data b Input to MUX 1. Internal 75 kW to V
EE
and 37 kW to V
.
CC
Q0
Noninverted Differential Output MUX 0. Typically Terminated with
50 W to V = V − 2.0 V.
TT
CC
1
Q0
−
Inverted Differential Output MUX 0. Typically Terminated with
50 W to V = V − 2.0 V.
TT
CC
17
16
23
22
21
−
Q1
−
Noninverted Differential Output MUX 1. Typically Terminated with
50 W to V = V − 2.0 V.
TT
CC
Q1
−
Inverted Differential Output MUX 1. Typically Terminated with
50 W to V = V − 2.0 V.
TT
CC
SEL0
COM_SEL
SEL1
EP
ECL, CMOS
Input
Low
Low
Low
Noninverted Differential Select Input to MUX 0. Internal 75 W to
V
.
EE
ECL, CMOS
Input
Noninverted Differential Common Select Input to Both MUX.
Internal 75 W to V
.
EE
ECL, CMOS
Input
Noninverted Differential Select Input to MUX 1. Internal 75 W to
V
.
EE
−
Exposed Pad. (Note 1)
1. The thermally conductive exposed pad on the package bottom (see case drawing) must be attached to a heat sinking conduit.
http://onsemi.com
2
NB100LVEP56
D0a
R
1
1
R
R
2
Q0
Q0
D0a
R
1
D0b
0
Table 2. TRUTH TABLE
R
1
SEL0
2
SEL0
SEL1
COM_SEL Q0, Q0 Q1, Q1
R
R
R
1
1
1
D0b
R
X
L
L
H
H
X
L
H
H
L
H
L
L
L
L
a
b
b
a
a
a
b
a
a
b
1
COM_SEL
SEL1
D1a
R
1
1
R
R
2
D1a
Q1
Q1
R
1
D1b
0
R
1
V
V
CC
2
EE
D1b
R
1
Exposed Pad
(EP)
COM
SEL
Figure 1. Logic Diagram
V
SEL0
SEL1 V
V
CC CC
EE
24
23
22
21
20
19
Q0
Q0
V
CC
1
18
17
20 19 18 17 16 15 14 13 12
11
Q1
2
3
4
5
6
V
16 Q1
CC
NB100LVEP56
NB100LVEP56
15
D0a
V
EE
14
13
D1b
D1b
D0a
1
2
3
4
5
6
7
8
9
10
V
BB0
7
8
9
10
11
12
Figure 2. TSSOP−20 Lead Pinout (Top View)
D0b D0b V
D1a D1a V
BB1
CC
Figure 3. QFN−24 Lead Pinout (Top View)
Table 3. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
(R1)
(R2)
75 kW
37 kW
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 150 V
> 2 kV
Moisture Sensitivity (Note 1)
Pb Pkg
Pb−Free Pkg
TSSOP−20
QFN−24
Level 1
Level 1
Level 1
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
354 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
3
NB100LVEP56
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
Positive Mode Power Supply
V
V
6
CC
EE
I
EE
CC
Negative Mode Power Supply
= 0 V
−6
V
Positive Mode Input Voltage
Negative Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
EE
V w V
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
I
V
Sink/Source
BB
"0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−3 (1S − Single Layer Test Board)
0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
140
50
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Ambient)
JEDEC 51−6 (2S2P−Multi Layer Test Board)
with Filled Thermal Vias
0 lfpm
500 lfpm
QFN−24
QFN−24
37
32
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−20
QFN−24
23 to 41
11
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. DC CHARACTERISTICS, PECL V = 2.5 V, V = 0 V (Note 2)
CC
EE
−40°C
Typ
45
25°C
Typ
45
85°C
Typ
48
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 3)
Unit
mA
mV
I
35
55
35
55
35
58
EE
V
V
V
1355 1480 1605 1355 1480 1605 1355 1480 1605
OH
OL
IH
Output LOW Voltage (Note 3)
555
775
900
555
775
900
555
775
900
mV
mV
Input HIGH Voltage (SEL0, SEL1, COM_SEL) 1335
V
1335
V
1275
V
CC
1620
CC
CC
1335
1620 1335
1620 1275
Input HIGH Voltage (D Inputs) (Note 4)
V
V
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs) (Note 4)
V
875
875
V
875
875
V
EE
875
875
mV
V
IL
EE
EE
555
555
555
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 5)
1.2
2.5
1.2
2.5
1.2
2.5
IHCMR
I
I
Input HIGH Current (@V
)
IH
150
150
150
mA
mA
IH
IL
Input LOW Current (@V )
D
D
SEL
0.5
−150
−150
0.5
−150
−150
0.5
−150
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary −0.125 V to +1.3 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. Do not use V at V < 3.0 V.
BB
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
4
NB100LVEP56
Table 6. DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 6)
CC
EE
−40°C
Typ
45
25°C
Typ
45
85°C
Typ
Min
Max
Min
Max
Min
Max
58
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
Unit
mA
mV
mV
mV
I
35
55
35
55
35
48
EE
V
V
V
2155 2280 2405 2155 2280 2405 2155
1355 1575 1700 1355 1575 1700 1355
2280
1575
2405
1700
OH
OL
IH
Input HIGH Voltage (SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
2135
2135
V
2135
V
2135
V
CC
2420
CC
CC
2420 2135
2420 2135
V
Input LOW Voltage (SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
V
1675
V
1675
V
1675
1675
mV
IL
EE
EE
EE
1355
1675 1355
1675 1355
V
V
Output Reference Voltage (Note 8)
1775 1875 1975 1775 1875 1975 1775
1875
1975
3.3
mV
V
BB
Input HIGH Voltage Common Mode Range
(Differential Configuration) (Note 9)
1.2
3.3
1.2
3.3
1.2
IHCMR
I
I
Input HIGH Current (@V
)
IH
150
150
150
mA
mA
IH
IL
Input LOW Current (@V )
D
D
SEL
0.5
−150
−150
0.5
−150
−150
0.5
−150
−150
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Input and output parameters vary 1:1 with V . V can vary +0.5 V to −0.3 V.
CC
EE
7. All loading with 50 W to V − 2.0 V.
CC
8. Single−Ended input operation is limited to V w 3.0 V in PECL mode.
CC
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 7. DC CHARACTERISTICS, NECL V = 0 V, V = −3.8 V to −2.375 V (Note 10)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
mA
mV
I
Negative Power Supply Current
Output HIGH Voltage (Note 11)
35
45
55
35
45
55
35
48
58
EE
V
V
V
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
OH
OL
IH
Output LOW Voltage (Note 11)
−1945 −1725 −1600 −1945 −1725 −1600 −1945 −1725 −1600 mV
Input HIGH Voltage
(SEL0, SEL1, COM_SEL)
Input HIGH Voltage (D Inputs)
mV
−1165
−1165
V
−1165
V
−1165
V
CC
−880
CC
CC
−880 −1165
−880 −1165
V
Input LOW Voltage
(SEL0, SEL1, COM_SEL)
Input LOW Voltage (D Inputs)
mV
IL
V
−1600
V
−1600
V
−1600
−1600
EE
EE
EE
−1945
−1600 −1945
−1600 −1945
V
V
Output Reference Voltage (Note 12)
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
V
+1.2
EE
0.0
V
+1.2
EE
0.0
V
+1.2
EE
0.0
V
IHCMR
I
I
Input HIGH Current (@V
)
IH
150
150
150
mA
mA
IH
IL
Input LOW Current (@V )
D
D
0.5
−150
0.5
−150
−150
0.5
−150
−150
IL
SEL −150
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Input and output parameters vary 1:1 with V
.
CC
11. All loading with 50 W to V − 2.0 V.
CC
12.Single−Ended input operation is limited to V from −3.0 V to −5.5 V in NECL mode.
EE
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
http://onsemi.com
5
NB100LVEP56
Table 8. AC CHARACTERISTICS V = 0 V; V = −2.375 V to −3.8 V or V = 2.375 V to 3.8 V; V = 0 V (Note 14)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
v 1 GHz 525
in
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figure 4)
f
700
600
500
550
500
350
700
600
450
500
400
200
700
500
300
mV
OUTPP
f
= 2 GHz 500
in
f
= 2.5 GHz 400
in
t
t
,
Propagation Delay to Output Differential
ps
ps
ps
PLH
PHL
D to Q, Q 375
500
775
750
625
975
950
400
625
600
525
650
450
575
900
900
700
1100
1100
SEL to Q, Q 575
COM_SEL to Q, Q 550
825 1025 700
800 1000 700
t
t
Pulse Skew (Note 15)
10
5
15
50
50
30
50
200
10
5
15
50
10
5
15
50
50
30
50
200
Skew
Within Device Input Skew (Note 16)
Within Device Output Skew (Note 17)
Device−to−Device Skew (Note 18)
RMS Random Clock Jitter (Note 19)
JITTER
@ v1.0 GHz
0.269
0.306
0.250
0.339
0.4
0.4
0.4
0.8
0.307
0.303
0.305
0.895
0.4
0.4
0.5
2.0
0.371
0.391
0.722
2.443
0.5
0.6
1.2
7.7
@ v1.5 GHz
@ v2.0 GHz
@ v2.5 GHz
Peak−to−Peak Data Dependent Jitter (Note 20)
@ 0.5 GHz
@ 1.25 GHz
@ 2.488 GHz
4.1
32.2
30.8
16
80
66
4.6
22.6
27.2
15
63
56
4.4
22
24.4
16
53
54
V
Input Voltage Swing (Differential Configuration)
(Note 21)
150
60
800 1200 150
800 1200 150
800 1200 mV
INPP
t
t
Output Rise/Fall Times @ 50 MHz
Q, Q
ps
r
f
(20% − 80%)
110
150
60
120
170
90
140
230
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V. Input edge rates 150 ps (20% − 80%).
CC
15.Pulse Skew |t
− t
PHL
|
PLH
16.Worst case difference between D0a and D0b (or between D1a or D1b), when both output come from same input.
17.Worst case difference between Q0 and Q1 outputs.
18.Skew is measured between outputs under identical transitions.
19.Additive RMS jitter with 50% Duty Cycle Clock Signal.
31
20.Additive Peak−to−Peak jitter with input NRZ data at PRBS 2 −1.
21.Input voltage swing is a single−ended measurement operating in differential mode.
850
Q AMP (mV)
750
650
550
450
350
250
0.5
1.0
1.5
2.0
2.5
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) vs.
Input Frequency (fin) at VCC = 2.5 V, 255C
http://onsemi.com
6
NB100LVEP56
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 5. AC Reference Measurement
Z = 50 W
Q
Q
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
D
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
http://onsemi.com
7
NB100LVEP56
ORDERING INFORMATION
Device
Package
TSSOP−20*
TSSOP−20*
TSSOP−20*
TSSOP−20*
QFN−24
Shipping†
75 Units / Rail
75 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
92 Units / Rail
92 Units / Rail
NB100LVEP56DT
NB100LVEP56DTG
NB100LVEP56DTR2
NB100LVEP56DTR2G
NB100LVEP56MN
NB100LVEP56MNG
QFN−24
(Pb−Free)
NB100LVEP56MNR2
NB100LVEP56MNR2G
QFN−24
3000 Tape & Reel
3000 Tape & Reel
QFN−24
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
*This package is inherently Pb−Free.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
8
NB100LVEP56
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
V
0.10 (0.004)
T U
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MIN
MAX
0.260
0.177
F
A
B
6.40
4.30
−−−
0.252
0.169
DETAIL E
C
−−− 0.047
0.006
0.030
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
9
NB100LVEP56
PACKAGE DIMENSIONS
QFN 24
MN SUFFIX
24 PIN QFN, 4x4
CASE 485L−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
D
A
B
E
PIN 1
IDENTIFICATION
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN
MAX
1.00
0.05
0.80
2X
A
A1
A2
A3
b
0.80
0.00
0.60
0.15
C
0.20 REF
2X
0.15
C
0.23
0.28
D
4.00 BSC
A2
D2
E
2.70
2.90
0.10
C
4.00 BSC
E2
e
2.70
2.90
A
0.50 BSC
0.08
C
L
0.35
0.45
A3
SEATING
PLANE
REF
A1
C
D2
e
L
7
12
6
1
13
E2
24X
b
18
24
19
e
0.10 C A B
0.05 C
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NB100LVEP56/D
相关型号：
NB100LVEP91-D
2.5V / 3.3V AnyLevel? Positive Input to -2.5V / -3.3V / -5V NECL Output Translator
ONSEMI
NB100LVEP91DW
2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator
ONSEMI
NB100LVEP91DWG
2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator
ONSEMI
NB100LVEP91DWR2
2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator
ONSEMI
NB100LVEP91DWR2G
2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator
ONSEMI
NB100LVEP91MN
2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator
ONSEMI
NB100LVEP91MNG
2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator
ONSEMI
NB100LVEP91MNR2
2.5V / 3.3V Any Level Positive Input to -2.5V -3.3V / -5V NECL Output Translator
ONSEMI
NB100LVEP91MNR2G
2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator
ONSEMI
NB100LVEP91_06
2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator
ONSEMI
©2020 ICPDF网 联系我们和版权申明