NB2308AI3 [ONSEMI]
3.3 V Zero Delay Clock Buffer;
| 型号： | NB2308AI3 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V Zero Delay Clock Buffer |
| 文件： | 总12页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB2308A
3.3 V Zero Delay
Clock Buffer
The NB2308A is a versatile, 3.3 V zero delay buffer designed to
distribute high--speed clocks. It is available in a 16 pin package. The
part has an on--chip PLL which locks to an input clock presented on
the REF pin. The PLL feedback is required to be driven to FBK pin,
and can be obtained from one of the outputs. The input--to--output
propagation delay is guaranteed to be less than 250 ps, and the
output--to--output skew is guaranteed to be less than 200 ps.
The NB2308A has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input Decoding
Table. If all the output clocks are not required, Bank B can be
three--stated. The select input also allows the input clock to be directly
applied to the outputs for chip and system testing purposes.
Multiple NB2308A devices can accept the same input clock and
distribute it. In this case the skew between the outputs of the two
devices is guaranteed to be less than 700 ps.
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MARKING
DIAGRAMS*
16
1
16
XXXXXXXXXG
AWLYWW
1
SOIC--16
D SUFFIX
CASE 751B
The NB2308A is available in five different configurations (Refer to
NB2308A Configurations Table). The NB2308AI1 is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2308AI1H is the high--drive version of
the --1 and the rise and fall times on this device are much faster.
The NB2308AI2 allows the user to obtain 2X and 1X frequencies on
each output bank. The exact configuration and output frequencies
depends on which output drives the feedback pin. The NB2308AI3
allows the user to obtain 4X and 2X frequencies on the outputs.
The NB2308AI4 enables the user to obtain 2X clocks on all outputs.
Thus, the part is extremely versatile, and can be used in a variety of
applications.
16
XXXX
XXXX
ALYWG
G
16
1
TSSOP--16
DT SUFFIX
CASE 948F
1
XXXX = Device Code
= Assembly Location
WL, L = Wafer Lot
= Year
A
Y
The NB2308AI5H is a high--drive version with REF/2 on both
banks.
WW, W = Work Week
G or G = Pb--Free Package
(Note: Microdot may be in either location)
Features
Zero Input -- Output Propagation Delay, Adjustable by Capacitive
Load on FBK Input
*For additional marking information, refer to
Application Note AND8002/D.
Multiple Configurations -- Refer to NB2308A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low--Skew Outputs
ORDERING INFORMATION
Seedetailedorderingandshippinginformationinthepackage
dimensions section on page 9 of this data sheet.
Output--Output Skew Less than 200 ps
Device--Device Skew Less than 700 ps
Two banks of four outputs, three--stateable by two select inputs
Less than 200 ps Cycle--to--Cycle Jitter
Available in 16--pin SOIC and TSSOP Packages
3.3 V Operation
Guaranteed Across Commercial and Industrial Temperature Ranges
Advanced 0.35 m CMOS Technology
These are Pb--Free Devices
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
October, 2010 -- Rev. 8
NB2308A/D
NB2308A
FBK
÷2
PLL
REF
÷2
CLKA1
Extra Divider (--3, --4)
MUX
CLKA2
CLKA3
CLKA4
Extra Divider (--5H)
S2
S1
SELECT INPUT
DECODING
÷2
CLKB1
CLKB2
CLKB3
CLKB4
Extra Divider (--2, --3)
Figure 1. Block Diagram
(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)
Table 1. CONFIGURATIONS
Device
NB2308AI1
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank A Frequency
Reference
Bank B Frequency
Reference
Reference
NB2308AI1H
NB2308AI2
NB2308AI2
NB2308AI3
NB2308AI3
NB2308AI4
NB2308AI5H
Reference
Reference
Reference ÷2
Bank B
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference ÷2
Reference
Bank A
Reference or Reference (Note 1)
2 X Reference
Bank B
Bank A or Bank B
Bank A or Bank B
2 X Reference
Reference ÷2
1. Output phase is indeterminant (0 or 180 from input clock). If phase integrity is required, use the NB2308AI2.
Table 2. SELECT INPUT DECODING
S2
0
S1
0
Clock A1 -- A4
Three--state
Driven
Clock B1 -- B4
Three--state
Three--state
Driven
Output Source
PLL
PLL ShutDown
Y
N
Y
N
0
1
PLL
1
0
Driven (Note 2)
Driven
Reference
PLL
1
1
Driven
2. Outputs inverted on 2308--2 and 2308--3 in bypass mode, S2 = 1 and S1 = 0.
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2
NB2308A
1
2
3
4
5
6
7
8
REF
CLKA1
CLKA2
16
15
14
13
12
11
10
9
FBK
CLKA4
CLKA3
V
V
DD
DD
NB2308A
GND
GND
CLKB4
CLKB3
S1
CLKB1
CLKB2
S2
Figure 2. Pin Configuration
Table 3. PIN DESCRIPTION
Pin #
1
Pin Name
Description
Input reference frequency, 5 V tolerant input.
REF (Note 3)
CLKA1 (Note 4)
CLKA2 (Note 4)
2
Buffered clock output, Bank A.
Buffered clock output, Bank A.
3.3 V supply.
3
4
V
DD
5
GND
Ground.
6
CLKB1 (Note 4)
CLKB2 (Note 4)
S2 (Note 5)
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Select input, bit 2.
7
8
9
S1 (Note 5)
Select input, bit 1.
10
11
12
13
14
15
CLKB3 (Note 4)
CLKB4 (Note 4)
GND
Buffered clock output, Bank B.
Buffered clock output, Bank B.
Ground.
V
3.3 V supply.
DD
CLKA3 (Note 4)
CLKA4 (Note 4)
FBK
Buffered clock output, Bank A.
Buffered clock output, Bank A.
PLL feedback input.
16
3. Weak pulldown.
4. Weak pulldown on all outputs.
5. Weak pullup on these inputs.
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3
NB2308A
Table 4. MAXIMUM RATINGS
Parameter
Min
-- 0 . 5
-- 0 . 5
-- 0 . 5
-- 6 5
Max
Unit
V
Supply Voltage to Ground Potential
DC Input Voltage (Except REF)
DC Input Voltage (REF)
+7.0
V
+ 0.5
V
DD
7
V
Storage Temperature
+150
260
C
C
C
V
Maximum Soldering Temperature (10 sec)
Junction Temperature
150
Static Discharge Voltage (per MIL--STD--883, Method 3015)
>2000
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 5. OPERATING CONDITIONS
Parameter
Description
Min
Max
Unit
V
V
Supply Voltage
3.0
3.6
DD
T
A
Operating Temperature (Ambient Temperature)
Industrial
Commercial
-- 4 0
0
85
70
C
C
Load Capacitance, below 100 MHz
Load Capacitance, from 100 MHz to 133 MHz
Input Capacitance (Note 6)
30
15
7
pF
pF
pF
L
C
C
L
IN
6. Applies to both REF Clock and FBK.
Table 6. ELECTRICAL CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0 V, T = --40C to +85C
CC
A
Parameter
Description
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Test Conditions
Min
Max
Unit
V
V
0.8
IL
V
2.0
V
IH
I
I
V
V
= 0 V
50.0
100.0
0.4
mA
mA
V
IL
IH
IN
IN
= V
DD
V
I
I
= 8 mA (--1, --2, --3, --4)
= 12 mA (--1H, --5H)
OL
OL
OL
V
Output HIGH Voltage
I
I
= --8 mA (--1, --2, --3, --4)
= --12 mA (--1H, --5H)
2.4
V
OH
OH
OH
I
Supply Current (Note 7)
Unloaded outputs 100 MHz REF
-- 2 , -- 3 , -- 4
-- 1 H , -- 5 H
49
60
34
mA
mA
mA
DD
Select inputs at V or GND
DD
Unloaded outputs, 66 MHz REF
(--1, --2, --3, --4)
Unloaded outputs, 33 MHz REF
(--1, --2, --3, --4)
18
mA
7. Supply currents are measured for PLL--Bypass Mode (S2 = 1, S1 = 0).
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4
NB2308A
Table 7. SWITCHING CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0 V, T = --40C to +85C
CC
A
Parameter
Description
Output Frequency
Test Conditions
Min
Typ
Max
Unit
t
30 pF load (all devices)
15 pF load (--1H, --5H)
15 pF load (--1, --2, --3, --4)
15
15
15
100
133.3
133.3
MHz
1
t
Duty Cycle = (t / t ) * 100
%
Measured at 1.4 V, F
30 pF load
= < 66.66 MHz
40.0
50.0
50.0
60.0
55.0
2.20
1.50
1.50
2.20
1.50
1.25
200
200
200
400
250
700
200
200
100
400
400
1.0
1
2
1
OUT
(all devices)
Measured at 1.4 V, F
15 pF load
= < 50 MHz
45.0
OUT
t
t
t
Output Rise Time
(--1, --2, --3, --4)
ns
Measured between 0.8 V and 2.0 V
30 pF load
3
4
5
Measured between 0.8 V and 2.0 V
15 pF load
Output Rise Time
(--1H, --5H)
Measured between 0.8 V and 2.0 V
30 pF load
Output Fall Time
(--1, --2, --3, --4)
ns
ps
Measured between 2.0 V and 0.8 V
30 pF load
Measured between 0.8 V and 2.0 V
15 pF load
Output Fall Time
(--1H, --5H)
Measured between 2.0 V and 0.8 V
30 pF load
Output--to--Output Skew on same Bank
(--1, --2, --3, --4)
All outputs equally loaded
Output--to--Output Skew
(--1H, --5H)
All outputs equally loaded
Output Bank A--to--Output Bank B Skew All outputs equally loaded
(--1, --4, --5H)
Output Bank A--to--Output Bank B Skew All outputs equally loaded
(--2, --3)
t
t
t
Delay, REF Rising Edge to FBK
Rising Edge
Measured at V /2
0
0
ps
ps
ps
6
7
J
DD
Device--to--Device Skew
Measured at V /2 on the FBK pins of the
DD
device
Cycle--to--Cycle Jitter
(--1, --1H, --4, --5H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs
15 pF load
Cycle--to--Cycle Jitter
(--2, --3)
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 66.67 MHz, loaded outputs,
15 pF load
t
PLL Lock Time
Stable power supply, valid clock presented
on REF and FBK pins
ms
LOCK
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5
NB2308A
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero
Delay between input and output.
To close the feedback loop of the NB2308A, the FBK pin
can be driven from any of the eight available output pins.
The output driving the FBK pin will be driving a total load
of 7 pF plus any additional load that it drives. The relative
loadingofthisoutput(withrespecttotheremainingoutputs)
can adjust the input--output delay. This is shown in Figure 3.
For applications requiring zero input--output delay, all
outputs including the one providing feedback should be
equally loaded. If input--output delay adjustments are
required, use the above graph to calculate loading
differences between the feedback output and remaining
outputs. For zero output--output skew, be sure to load
outputs equally.
1500
1000
500
0
--500
--1000
--1500
-- 3 0 -- 2 5 -- 2 0 -- 1 5 -- 1 0 -- 5
0
5
1 0 1 5 2 0 2 5 3 0
OUTPUT LOAD DIFFERENCE: FBK LOAD -- CLKA/CLKB LOAD (pF)
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
SWITCHING WAVEFORMS
t
1
t
2
3.3 V
2.0 V
0.8 V
2.0 V
0.8 V
1.4 V
1.4 V
1.4 V
0 V
OUTPUT
t
t
4
3
Figure 4. Duty Cycle Timing
Figure 5. All Outputs Rise/Fall Time
VDD
2
1.4 V
OUTPUT
OUTPUT
INPUT
OUTPUT
VDD
2
1.4 V
t
t
6
5
Figure 6. Output -- Output Skew
Figure 7. Input -- Output Propagation Delay
VDD
2
FBK_Device 1
FBK_Device 2
VDD
2
t
7
Figure 8. Device -- Device Skew
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6
NB2308A
TEST CIRCUITS
V
DD
1 kΩ
1 kΩ
V
V
DD
DD
V
V
CLKOUT
C
DD
DD
OUTPUTS
OUTPUTS
0.1 mF
0.1 mF
0.1 mF
0.1 mF
LOAD
10 pF
GND GND
GND GND
Figure 9. Test Circuit #1
Figure 10. Test Circuit #2
For parameter t8 (output slew rate) on --1H devices
BLOCK DIAGRAMS
FBK
FBK
CLKA1
CLKA1
CLKA2
CLKA3
CLKA4
CLKA2
CLKA3
CLKA4
PLL
MUX
REF
PLL
MUX
REF
S2
S1
S2
S1
SELECT INPUT
DECODING
SELECT INPUT
DECODING
÷2
CLKB1
CLKB2
CLKB3
CLKB4
CLKB1
CLKB2
CLKB3
CLKB4
Figure 11. NB2308AI1 and NB2308AI1H
Figure 12. NB2308AI2
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7
NB2308A
BLOCK DIAGRAMS
FBK
FBK
÷2
CLKA1
÷2
CLKA1
CLKA2
CLKA2
CLKA3
CLKA4
MUX
PLL
REF
PLL
MUX
CLKA3
CLKA4
REF
S2
S1
S2
S1
SELECT INPUT
DECODING
SELECT INPUT
DECODING
÷2
CLKB1
CLKB2
CLKB3
CLKB4
CLKB1
CLKB2
CLKB3
CLKB4
Figure 13. NB2308AI3
Figure 14. NB2308AI4
FBK
CLKA1
CLKA2
CLKA3
CLKA4
MUX
PLL
REF
÷2
S2
S1
SELECT INPUT
DECODING
CLKB1
CLKB2
CLKB3
CLKB4
Figure 15. NB2308AI5H
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8
NB2308A
ORDERING INFORMATION
Device
†
Marking
Operating Range
Package
Shipping
Availability
NB2308AI1DG
2308AI1G
Industrial &
Commercial
SOIC--16
(Pb--Free)
48 Units / Rail
2500 Tape & Reel
48 Units / Rail
Now
NB2308AI1DR2G
NB2308AI1HDG
NB2308AI1HDR2G
NB2308AI1DTG
NB2308AI1DTR2G
NB2308AI1HDTG
NB2308AI1HDTR2G
NB2308AI2DG
2308AI1G
2308AI1HG
2308AI1HG
Industrial &
Commercial
SOIC--16
(Pb--Free)
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Industrial &
Commercial
SOIC--16
(Pb--Free)
Industrial &
Commercial
SOIC--16
(Pb--Free)
2500 Tape & Reel
96 Units / Rail
2308
AI1
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI1
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
96 Units / Rail
2308
AI1H
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI1H
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
48 Units / Rail
2308AI2G
Industrial &
Commercial
SOIC--16
(Pb--Free)
NB2308AI2DR2G
NB2308AI2DTG
NB2308AI2DTR2G
NB2308AI2HDG
NB2308AI2HDR2G
NB2308AI2HDTG
NB2308AI2HDTR2G
NB2308AI3DG
2308AI2G
Industrial &
Commercial
SOIC--16
(Pb--Free)
2500 Tape & Reel
96 Units / Rail
2308
AI2
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI2
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
48 Units / Rail
2308AI2HG
Industrial &
Commercial
SOIC--16
(Pb--Free)
2308AI2HG
Industrial &
Commercial
SOIC--16
(Pb--Free)
2500 Tape & Reel
96 Units / Rail
2308
AI2H
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI2H
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
48 Units / Rail
2308AI3G
Industrial &
Commercial
SOIC--16
(Pb--Free)
NB2308AI3DR2G
NB2308AI3DTG
NB2308AI3DTR2G
NB2308AI4DG
2308AI3G
Industrial &
Commercial
SOIC--16
(Pb--Free)
2500 Tape & Reel
96 Units / Rail
2308
AI3
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI3
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
48 Units / Rail
2308AI4G
Industrial &
Commercial
SOIC--16
(Pb--Free)
NB2308AI4DR2G
NB2308AI4DTG
NB2308AI4DTR2G
2308AI4G
Industrial &
Commercial
SOIC--16
(Pb--Free)
2500 Tape & Reel
96 Units / Rail
2308
AI4
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI4
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
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9
NB2308A
ORDERING INFORMATION
Device
†
Marking
Operating Range
Package
Shipping
Availability
NB2308AI5HDG
2308AI5HG
Industrial &
Commercial
SOIC--16
(Pb--Free)
48 Units / Rail
2500 Tape & Reel
96 Units / Rail
Now
NB2308AI5HDR2G
NB2308AI5HDTG
NB2308AI5HDTR2G
2308AI5HG
Industrial &
Commercial
SOIC--16
(Pb--Free)
Now
Now
Now
2308
AI5H
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2308
AI5H
Industrial &
Commercial
TSSOP--16
(Pb--Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-
cifications Brochure, BRD8011/D.
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10
NB2308A
PACKAGE DIMENSIONS
TSSOP--16
CASE 948F--01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T
U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
16
9
2X L/2
J1
SECTION N--N
B
-- U --
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE --W--.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
-- V --
N
A
B
4.90
4.30
-- -- --
5.10 0.193 0.200
4.50 0.169 0.177
1 . 2 0
F
C
-- -- -- 0 . 0 4 7
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
-- W --
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
SEATING
PLANE
6.40 BSC
0.252 BSC
H
DETAIL E
-- T --
M
0
8
0
8
_
_
_
_
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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11
NB2308A
PACKAGE DIMENSIONS
SOIC--16
CASE 751B--05
ISSUE K
NOTES:
-- A --
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
1
9
8
-- B --
P 8 PL
M
S
0.25 (0.010)
B
MILLIMETERS
INCHES
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
G
F
R X 45
K
_
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
7
C
0
5.80
0.25
7
0
_
_
_
_
-- T --
SEATING
PLANE
6.20
0.50
0.229
0.010
0.244
0.019
J
M
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
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