NB3H60113GH4MTR2G [ONSEMI]
3.3 V Programmable OmniClock Generator with Single Ended LVCMOS Output;
| 型号： | NB3H60113GH4MTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V Programmable OmniClock Generator with Single Ended LVCMOS Output |
| 文件： | 总13页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
3.3 Vꢀ Programmable OmniClock
Generator
with Single Ended LVCMOS Output
WDFN8
CASE 511AT
NB3H60113GH4
The NB3H60113GH4, which is a member of the OmniClock family,
is a one−time programmable (OTP), low power PLL−based clock
generator that supports output frequency of 39.6 MHz. The device
accepts fundamental mode parallel resonant crystal frequency of
19.8 MHz as input. It generates one single ended LVCMOS output.
The output signals can be modulated using the spread spectrum feature
of the PLL (programmable spread spectrum type, deviation and rate)
for applications demanding low electromagnetic interference (EMI).
The device can be powered down using the Power Down pin (PD#).
It is possible to program the internal input crystal load capacitance and
the output drive current provided by the device. The device also has
automatic gain control (crystal power limiting) circuitry which avoids
the device overdriving the external crystal.
MARKING DIAGRAM
1
H4MG
G
H4 = Specific Device Code
M
G
= Date Code
= Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Features
• Member of the OmniClock Family of Programmable Clock
Generators
• Operating Power Supply: 3.3 V 10%
• I/O Standards
♦ Inputs: Fundamental Mode Crystal
♦ Output: LVCMOS
• 1 Programmable Single Ended LVCMOS Output of 39.6 MHz
• Input Frequency Range
♦ Crystal: 19.8 MHz
• Configurable Spread Spectrum Frequency Modulation Parameters
(Type, Deviation, Rate)
• Programmable Internal Crystal Load Capacitors
• Programmable Output Drive Current for Single Ended Outputs
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
• These are Pb−Free Devices
Typical Applications
• Industrial Applications
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
March, 2022 − Rev. 0
NB3H60113GH4/D
NB3H60113GH4
BLOCK DIAGRAM
VDD
PD#
Output Control
Crystal Control
Configuration
Memory
Output
Divider
Frequency and SS
CMOS
Buffer
CLK0
NC
PLL Block
Phase
Detector
XIN
Charge
Pump
Crystal
VCO
Oscillator
Crystal
and AGC
XOUT
Feedback
Divider
NC
GND
Notes:
1. CLK0 configured to be one single−ended LVCMOS output.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
XIN
XOUT
PD#
1
8
7
6
5
NC
2
3
4
VDD
NC
NB3H60113GH4
GND
CLK0
Figure 2. Pin Connections (Top View) – WDFN8
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2
NB3H60113GH4
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
XIN
Pin Type
Input
Description
1
2
3
19.8 MHz crystal input connection
Crystal output.
XOUT
PD#
Output
Input
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set
outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal op-
eration of the chip.
4
5
GND
Ground
Power supply ground
CLK0
Single
Ended
Output
Supports 39.6 MHz Single−Ended LVCMOS signals The single ended output will be LOW
and will be complementary LOW/HIGH until the PLL has locked and the frequency has
stabilized.
6
NC
SE
Output
Not used. To be left open floating.
7
8
VDD
NC
Power
3.3 V power supply
SE
Output
Not used. To be left open floating.
TYPICAL CRYSTAL PARAMETERS
Table 2. POWER DOWN FUNCTION TABLE
Crystal: Fundamental Mode Parallel Resonant
Frequency: 19.8 MHz
PD#
0
Function
Device Powered Down
Device Powered Up
1
Table 3. MAX CRYSTAL LOAD CAPACITORS
RECOMMENDATION
Crystal Frequency Range
Max Cap Value
20 pF
12 MHz – 27 MHz
Shunt Capacitance (C0): 12 pF (Max)
Equivalent Series Resistance (ESR): 60 W (Max)
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3
NB3H60113GH4
FUNCTIONAL DESCRIPTION
The NB3H60113GH4 is a 3.3 V programmable, single
number of parameters as detailed in the following section.
The One−Time Programmable memory allows
programming and storing of one configuration in the
memory space.
ended clock generator, designed to meet the clock
requirements for industrial markets. It has a small package
size and it requires low power during operation and while in
standby. This device provides the ability to configure a
VDD (3.3 V)
0.01 mF
0.1 mF
1 mF
19.8 MHz
Crystal
XIN
CLK0
39.6 MHz Single
Ended Clock
XOUT
NB3H60113GH4
VDD
PD#
GND
Figure 3. Power Supply Noise Suppression
Power Supply
recommended maximum load capacitor values for stable
operation. There are three modes of loading the crystal –
with internal chip capacitors only, with external capacitors
only or with the both internal and external capacitors. Check
with the crystal vendor’s load capacitance specification for
setting of the internal load capacitors. The minimum value
of 4.36 pF internal load capacitor need to be considered
while selecting external capacitor value. These will be
bypassed when using an external reference clock.
Device Supply
The NB3H60113GH4 is designed to work with a 3.3 V
VDD power supply. In order to suppress power supply noise
it is recommended to connect decoupling capacitors of
0.1 mF and 0.01 mF close to the VDD pin as shown in
Figure 3.
Clock Input
Input Frequency
Automatic Gain Control (AGC)
The clock input block can be programmed to use a
fundamental mode crystal 19.8 MHz. When using output
frequency modulation for EMI reduction, for optimal
performance, it is recommended to use crystals with
frequency more than 6.75 MHz as input. Crystals with ESR
values of up to 150 W are supported. When using a crystal
input, it is important to set crystal load capacitor values
correctly to achieve good performance.
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation. It also enables
maximum compatibility with crystals from different
manufacturers, processes, quality and performance. AGC
also takes care of the power dissipation in the crystal; avoids
over driving the crystal and thus extending the crystal life.
In order to calculate the AGC gain accurately and avoid
increasing the jitter on the output clocks, the user needs to
provide crystal load capacitance as well as other crystal
parameters like ESR and shunt capacitance (C0).
Programmable Crystal Load Capacitors
The provision of internal programmable crystal load
capacitors eliminates the necessity of external load
capacitors for standard crystals. The internal load capacitor
can be programmed to any value between 4.36 pF and
20.39 pF with a step size of 0.05 pF. Refer to Table 3 for
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4
NB3H60113GH4
Programmable Clock Outputs
Spread Spectrum Frequency Modulation
Spread spectrum is a technique using frequency
modulation to achieve lower peak electromagnetic
interference (EMI). It is an elegant solution compared to
techniques of filtering and shielding. The NB3H60113GH4
modulates the output of its PLL in order to “spread” the
bandwidth of the synthesized clock, decreasing the peak
amplitude at the center frequency and at the frequency’s
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum
modulation’. Refer Figure 4.
Output Type and Frequency
The NB3H60113GH4 provides one independent single
ended LVCMOS output. The device supports any single
ended output with frequency modulation. It should be noted
that certain combinations of output frequencies and spread
spectrum configurations may not be recommended for
optimal and stable operation.
Programmable Output Drive
The drive strength or output current of the LVCMOS
clock output is programmable. For V
distinct levels of LVCMOS output drive strengths can be
selected and here max drive is selected.
of 3.3 V four
DD
Figure 4. Frequency Modulation or Spread Spectrum Clock for EMI Reduction
The outputs of the NB3H60113GH4 is programmed to
have center spread of "1%. Additionally, the frequency
modulation rate is also programmable. Frequency
modulation of 30 kHz is selected. Spread spectrum, when
on, applies to all the outputs of the device. There exists a
tradeoff between the input clock frequency and the desired
spread spectrum profile. For certain combinations of input
frequency and modulation rate, the device operation could
be unstable and should be avoided. For spread spectrum
applications, the following limits are recommended:
For any input frequency selected, above limits must be
observed for a good spread spectrum profile.
Control Inputs
Power Down
Power saving mode can be activated through the power
down PD# input pin. This input is an LVCMOS active Low
Master Reset that disables the device and sets outputs Low.
By default it has an internal pull−down resistor. The chip
functions are disabled by default and when PD# pin is pulled
high the chip functions are activated.
Fin (Min) = 6.75 MHz
Fmod (range) = 30 kHz to 130 kHz
Fmod (Max) = Fin / 225
Configuration Space
NB3H60113GH4 has one Configuration. Table 4 shows
the example of device configuration.
Table 4. PROGRAMMED CONFIGURATION
Input Frequency
Output Frequency
VDD
SS%
SS Mod Rate
Output Enable
Output Drive
19.8 MHz
CLK0 = 39.6 MHz
3.3 V
"1%
30 kHz
CLK0 = Y
CLK0 = 16 mA
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NB3H60113GH4
Table 5. ATTRIBUTES
Characteristic
ESD Protection Human Body Model
Value
2 kV
50 kW
Internal Input Default State Pull up/ down Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating Oxygen Index: 28 to 34
MSL1
UL 94 V−0 @ 0.125 in
130 k
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
Parameter
Positive power supply with respect to Ground
Input/Output Voltage with respect to chip ground
Operating Ambient Temperature Range (Industrial Grade)
Storage temperature
Rating
−0.5 to +4.6
−0.5 to VDD + 0.5
−40 to +85
−65 to +150
265
Unit
V
VDD
V , V
V
I
O
T
A
°C
°C
°C
T
STG
SOL
T
Max. Soldering Temperature (10 sec)
q
Thermal Resistance (Junction−to−ambient)
(Note 3)
0 lfpm
500 lfpm
129
84
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−case)
35 to 40
125
°C/W
°C
JC
T
Junction temperature
J
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 sq mm, 2 oz
(0.070 mm) copper thickness.
Table 7. RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Condition
Min
Typ
Max
3.63
15
Unit
V
V
DD
Core Power Supply Voltage
3.3 V operation
2.97
3.3
CL
Clock output load capacitance for
LVCMOS clock
f
< 100 MHz
pF
out
fclkin
Crystal Input Frequency
XIN / XOUT pin stray Capacitance
Crystal Load Capacitance
Crystal ESR
Fundamental Crystal
Note 4
19.8
4.5
10
MHz
pF
C
X
C
pF
XL
ESR
60
W
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. The XIN / XOUT pin stray capacitance needs to be subtracted from crystal load capacitance (along with PCB and trace capacitance) while
selecting appropriate load for the crystal in order to get minimum ppm error.
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NB3H60113GH4
Table 8. DC ELECTRICAL CHARACTERISTICS (V = 3.3 V 10%, GND = 0 V, T = −40°C to 85°C, Notes 5, 6)
DD
A
Symbol
Parameter
Power Supply current
Condition
Min
Typ
Max
Unit
I
Configuration Dependent.
26
mA
DD_3.3 V
V
DD
= 3.3 V, T = 25°C,
A
XTAL = 19.8 MHz
CLK0 = 39.6 MHz, 16 mA
output drive
I
Power Down Supply Current
Input HIGH Voltage
PD# is Low to make all outputs OFF
20
mA
PD
V
V
Pin XIN
Pin PD#
Pin XIN
Pin PD#
0.65 V
V
DD
IH
DD
0.85 V
V
DD
DD
V
Input LOW Voltage
V
0
0
0.35 V
0.15 V
IL
DD
DD
Zo
Nominal Output Impedance
Configuration Dependent. 16 mA drive
= 3.3 V
22
50
W
R
Internal Pull up/ Pull down resistor
V
DD
kW
pF
PUP/PD
Cprog
Programmable Internal Crystal Load Configuration Dependent
Capacitance
4.36
20.39
6
Programmable Internal Crystal Load
Capacitance Resolution
0.05
4
pF
pF
Cin
Input Capacitance
Pin PD#
LVCMOS OUTPUT
V
Output HIGH Voltage
Output LOW Voltage
V
V
= 3.3 V
= 3.3 V
I
= 16 mA 0.75*V
= 16 mA
V
V
OH
DD
OH
DD
V
I
0.25*V
DD
OL
DD
OL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per-
formance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF. See Figure 6.
6. Parameter guaranteed by design verification not tested in production.
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NB3H60113GH4
Table 9. AC ELECTRICAL CHARACTERISTICS
(V = 3.3 V 10%; GND = 0 V, T = −40°C to 85°C, Notes 7, 8 and 10)
DD
A
Symbol
fout
Parameter
Conditions
Min
Typ
39.6
30
Max
Unit
MHz
kHz
%
Single Ended Output Frequency
Spread Spectrum Modulation Rate
f
fclkin ≥ 6.75 MHz
Center Spread
MOD
SS
Percent Spread Spectrum
(deviation from nominal frequency)
1
SSC
Spectral Reduction, 3rd harmonic
@SS = 1%, f = 39.6 MHz,
−10
dB
RED
out
fclkin = 19.8 MHz crystal,
RES BW at 30 kHz, LVCMOS Output
t
t
Stabilization time from Power−up
V
= 3.3 V with Frequency Modulation
3.0
3.0
ms
ms
PU
DD
Stabilization time from Power Down
Time from falling edge on PD# pin to
tri−stated outputs (Asynchronous)
PD
Eppm
Synthesis Error
Configuration Dependent
0
ppm
ps
SINGLE ENDED OUTPUTS (V = 3.3 V 10%, T = −40°C to 85°C, Notes 7, 8 and 10)
DD
A
t
Period Jitter Peak−to−Peak
Configuration Dependent. 19.8 MHz xtal
100
JITTER−3.3 V
input , f = 39.6 MHz, SS off
out
(Notes 9, 10 and 11, see Figure 8)
Cycle−Cycle Peak Jitter
Rise/Fall Time
Configuration Dependent. 19.8 MHz xtal
100
input, f = 39.6 MHz, SS off
out
(Notes 9, 10 and 11, see Figure 8)
t / t
Measured between 20% to 80% with
ns
%
r
f 3.3 V
15 pF load, f = 39.6 MHz,
DD
out
V
= 3.3 V,
Max Drive
PLL Clock
1
t
Output Clock Duty Cycle
V
DD
= 3.3 V
DC
Duty Cycle of Ref clock is 50%
45
50
55
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. Parameter guaranteed by design verification not tested in production.
8. Measurement taken from single ended clock terminated with test load capacitance of 5 pF and 15 pF. See Figures 5, 6 and 7.
9. Measurement taken from single−ended waveform
10.AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of
the output. For application specific AC performance parameters, please contact onsemi.
11. Period jitter Sampled with 10000 cycles, Cycle−cycle jitter sampled with 1000 cycles. Jitter measurement may vary. Actual jitter is
dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output
load.
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NB3H60113GH4
SCHEMATIC FOR OUTPUT TERMINATION
3.3 V
VDD
Crystal
Input
XIN
Single Ended
Clock
R
S
Z
O
= 50 W
XOUT
CLK0
Receiver
NB3H60113GH4
CL
VDD
PD#
GND
Figure 5. Typical Termination for Single−Ended Device Load
PARAMETER MEASUREMENT TEST CIRCUITS
Measurement
Equipment
CLKx
LVCMOS Clock
Hi−Z Probe
CL
Figure 6. LVCMOS Parameter Measurement
TIMING MEASUREMENT DEFINITIONS
t
2
t
= 100 * t / t
2
DC
1
t
1
80% of VDD
50% of VDD
20% of VDD
GND
LVCMOS
Clock Output
t
f
t
r
Figure 7. LVCMOS Measurement for AC Parameters
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NB3H60113GH4
t
period−jitter
50% of CLK Swing
Clock
Output
t
t
(N+1)cycle
Ncycle
50% of CLK Swing
Clock
Output
t
= t
− t
CTC−jitter
(N+1)cycle Ncycle (over 1000 cycles)
Figure 8. Period and Cycle−Cycle Jitter Measurement
Tpower-up
Tpower-down
PD#
VIH
VIL
CLK Output
Figure 9. Output Enable/ Disable and Power Down Functions
APPLICATION GUIDELINES
Crystal Input Interface
Output Interface and Terminations
Figure 10 shows the NB3H60113GH4 device crystal
oscillator interface using a typical parallel resonant
fundamental mode crystal. A parallel crystal with loading
The NB3H60113GH4 consists of a unique Multi Standard
Output Driver to support LVCMOS standards. The required
termination changes must be considered and taken care of by
the system designer.
capacitance C = 18 pF would use C1 = 32 pF and C2 =
L
32 pF as nominal values, assuming 4 pF of stray capacitance
per line.
LVCMOS Interface
LVCMOS output swings rail−to−rail up to V supply
DD
(
)
CL + C1 ) Cstray ń2; C1 + C2
and can drive up to 15 pF load at higher drive strengths.
The output buffer’s drive is programmable up to four steps,
here in this device maximum drive current setting is
choosen. (See Figure 11 and Table 10). Drive strength must
be configured high for driving higher loads. The slew rate of
the clock signal increases with higher output current drive
for the same load. The software lets the user choose the load
The frequency accuracy and duty cycle skew can be
fine−tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency. Note R1 is optional and may be 0 W.
drive current value per LVCMOS output based on the V
supply selected.
DD
Table 10. LVCMOS DRIVE LEVEL SETTINGS
Load Current Setting
Max Load Current
VDD Supply
Figure 10. Crystal Interface Loading
3.3 V
16 mA
The load current consists of the static current component
(varies with drive) and dynamic current component. For any
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10
NB3H60113GH4
supply voltage, the dynamic load current range per
the cap load posed by the receiver input pin. C
= (CL +
load
LVCMOS output can be approximated by formula –
Cpin+ Cin)
An optional series resistor Rs can be connected at the
output for impedance matching, to limit the overshoots and
ringings.
IDD + fout * Cload * VDD
C
load
includes the load capacitor connected to the output,
the pin capacitor posed by the output pin (typically 5 pF) and
VDD
Drive Strength
selection
CLKx
Drive Strength
selection
Figure 11. Simplified LVCMOS Output Structure
Recommendation for Clock Performance
frequency is independent of signal frequency, and only
depends on the trace length and the propagation delay. For
eg. On an FR4 PCB with approximately 150 ps/ inch of
propagation rate, on a 2 inch trace, the ripple frequency = 1
/ (150 ps * 2 inch * 5) = 666.6 MHz; [5 = number of times
the signal travels, 1 trip to receiver plus 2 additional round
trips]
PCB traces should be terminated when trace length tr/f /
(2* tprate); tr/f = rise/ fall time of signal, tprate =
propagation rate of trace.
Clock performance is specified in terms of Jitter in time
the domain and Phase noise in frequency domain. Details
and measurement techniques of Cycle−cycle jitter, period
jitter, TIE jitter and Phase Noise are explained in application
note AND8459/D.
In order to have a good clock signal integrity for minimum
data errors, it is necessary to reduce the signal reflections.
Reflection coefficient can be zero only when the source
impedance equals the load impedance. Reflections are based
on signal transition time (slew rate) and due to impedance
mismatch. Impedance matching with proper termination is
required to reduce the signal reflections. The amplitude of
overshoots is due to the difference in impedance and can be
minimized by adding a series resistor (Rs) near the output
pin. Greater the difference in impedance, greater is the
amplitude of the overshoots and subsequent ripples. The
ripple frequency is dependant on the signal travel time from
the receiver to the source. Shorter traces results in higher
ripple frequency, as the trace gets longer the travel time
increases, reducing the ripple frequency. The ripple
Ringing
Overshoot
(Positive)
Overshoot
(Negative)
Figure 12. Signal Reflection Components
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11
NB3H60113GH4
PCB Design Recommendation
source or the receiver. In an optimum layout all components
are on the same side of the board, minimizing vias through
other signal layers.
For a clean clock signal waveform it is necessary to have
a clean power supply for the device. The device must be
isolated from system power supply noise. A 0.1 mF and a
2.2 mF decoupling capacitor should be mounted on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin and the
ground via should be kept thicker and as short as possible.
All the VDD pins should have decoupling capacitors.
Stacked power and ground planes on the PCB should be
large. Signal traces should be on the top layer with minimum
vias and discontinuities and should not cross the reference
planes. The termination components must be placed near the
Device Applications
The NB3H60113GH4 is targeted mainly for the Industrial
market segment and can be used as per the examples below
as per Figure 13.
Clock Generator
Consumer applications require single reference clock
sources at various locations in the system. This part can
function as a clock generating IC for applications requiring
a reference clock for interface.
VDD
PD#
Output Control
Crystal Control
Configuration
Memory
LVCMOS
Output
Divider
Frequency and SS
CMOS
Buffer
CLK0
39.6 MHz
PLL Block
XIN
Phase
Detector
Charge
Pump
Crystal
Oscillator
and AGC
VCO
CRYSTAL
19.8 MHz
Output
Divider
CMOS
Buffer
XOUT
Feedback
Divider
Output
Divider
CMOS
Buffer
GND
Figure 13. Application as Clock Generator
NOTE: LVCMOS signal level cannot be translated to a higher level of LVCMOS voltage.
ORDERING INFORMATION
†
Device
Case
Package
Shipping
NB3H60113GH4MTR2G
511AT
DFN−8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
NB3H60113GH4
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT−01
ISSUE O
L
L
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
0.20 REF
2X
0.10
C
0.20
0.30
EXPOSED Cu
MOLD CMPD
TOP VIEW
2.00 BSC
2.00 BSC
0.50 BSC
D
E
e
DETAIL B
L
0.40
---
0.50
0.60
0.15
0.70
0.05
C
L1
L2
DETAIL B
A
ALTERNATE
CONSTRUCTIONS
8X
0.05
C
A1
A3
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
C
7X
0.78
PACKAGE
OUTLINE
e/2
e
DETAIL A
7X
L
4
1
L2
2.30
0.88
1
8
5
8X
b
0.50
8X
0.30
PITCH
0.10
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
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