NB3L8533DTG [ONSEMI]
2.5V/3.3V 差分，2:1 MUX - 4 LVPECL 扇出缓冲器;
| 型号： | NB3L8533DTG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V 差分，2:1 MUX - 4 LVPECL 扇出缓冲器 |
| 文件： | 总10页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3L8533
2.5V/3.3V Differential 2:1
MUX to 4 LVPECL Fanout
Buffer
Description
The NB3L8533 is a low skew 1:4 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
www.onsemi.com
MARKING
The NB3L8533 features a multiplexed input which can be driven by
either a differential or single−ended input to allow for the distribution
of a lower speed clock along with the high speed system clock.
The CLK_SEL pin will select the differential clock inputs, CLK and
CLK, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When CLK_SEL is HIGH, the Differential
PCLK and PCLK inputs are selected.
The common enable (CLK_EN) is synchronous so that the outputs
will only be enabled/disabled when they are already in the LOW state.
This avoids any chance of generating a runt clock pulse when the
device is enabled/disabled as can happen with an asynchronous
control. The internal flip flop is clocked on the falling edge of the input
clock, therefore, all associated specification limits are referenced to
the negative edge of the clock input.
DIAGRAM
NB3L
8533
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
Features
• 650 MHz Maximum Clock Output Frequency
• CLK/CLK can Accept LVPECL, LVDS, HCSL, STTL and HSTL
• PCLK/PCLK can Accept LVPECL, LVDS, CML and SSTL
• Four Differential LVPECL Clock Outputs
• 1.5 ns Maximum Propagation Delay
+
CLK_EN
D
Q
Q0
Q0
CLK
CLK
0
1
Q1
Q1
• Operating Range: V = 2.375 V to 3.630 V
CC
+
• LVCMOS Compatible Control Inputs
• Selectable Differential Clock Inputs
• Synchronous Clock Enable
Q2
Q2
PCLK
PCLK
Q3
Q3
CLK_SEL
• 30 ps Max. Skew Between Outputs
• −40°C to +85°C Ambient Operating Temperature Range
• TSSOP−20 Package
Figure 1. Simplified Logic Diagram of
NB3L8533
• These are Pb−Free Devices
Applications
• Computing and Telecom
• Routers, Servers and Switches
• Backplanes
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
December, 2014 − Rev. 1
NB3L8533/D
NB3L8533
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
Q0
EE
CLK_EN
CLK_SEL
V
CC
Q1
Q1
CLK
CLK
PCLK
PCLK
nc
Q2
Q2
V
CC
nc
Q3
Q3
V
CC
Figure 2. Pinout Diagram (Top View)
Table 1. FUNCTIONS
Inputs
Outputs
CLK_EN
CLK_SEL
Input Function
Output Function
Disabled
Qx
Qx
HIGH
0
0
1
1
0
1
0
1
CLK input selected
PCLK Inputs Selected
CLK input selected
LOW
LOW
CLK
Disabled
HIGH
Enabled
Invert of CLK
Invert of PCLK
PCLK Inputs Selected
Enabled
PCLK
1. After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as show in Figure 3.
Table 2. PIN DESCRIPTION
Open
Default
Pin Number
Name
I/O
Description
1
VEE
Power
Negative (Ground) Power Supply pin must be externally connect-
ed to power supply to guarantee proper operation.
2
3
CLK_EN
LVCMOS/LVTTL
Input
Pull-up
Synchronized Clock Enable when HIGH. When LOW, outputs are
disabled (Qx HIGH, Qx LOW)
CLK_SEL
LVCMOS/LVTTL
Input
Pull-down
Clock Input Select (HIGH selects PCLK, LOW selects CLK input)
4
5
CLK
CLK
PCLK
PCLK
NC
Input
Input
Input
Input
Pull-down
Pull-up
Non−inverted Differential Clock Input. Float open when unused.
Inverted Differential Clock Input. Float open when unused.
Non−inverted Differential Clock Input. Float open when unused.
Inverted Differential Clock Input. Float open when unused.
No Connect
6
Pull-down
Pull-up
7
8
9
NC
No Connect
10
VCC
Power
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
11
12
13
Q3
Q3
LVPECL Output
LVPECL Output
Power
Complement Differential Output
True Differential Output
VCC
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
14
15
16
17
18
Q2
Q2
LVPECL Output
LVPECL Output
LVPECL Output
LVPECL Output
Power
Complement Differential Output
True Differential Output
Q1
Complement Differential Output
True Differential Output
Q1
VCC
Positive Power Supply pins must be externally connected to power
supply to guarantee proper operation.
19
20
Q0
Q0
LVPECL Output
LVPECL Output
Complement Differential Output
True Differential Output
www.onsemi.com
2
NB3L8533
Table 3. ATTRIBUTES (Note 2)
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2 kV
> 200 V
R
R
− Pull−up Resistor
50 kW
50 kW
PU
PD
− Pull−down Resistor
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
TSSOP−20
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
289
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply Voltage
Input Voltage
Condition 1
= 0 V
Condition 2
Rating
4.6
Unit
V
V
V
V
CC
I
EE
V
= 0 V
V ≤ V
−0.5 to V +
CC
V
EE
I
CC
0.5
I
Output Current
Continuous
Surge
50
100
mA
mA
out
T
Operating Temperature Range
−40 to +85
°C
°C
A
T
Storage Temperature Range
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−20
TSSOP−20
140
50
°C/W
q
Thermal Resistance (Junction−to−Case)
Wave Solder
Standard Board
TSSOP−20
23 to 41
265
°C/W
°C
JC
T
sol
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com
3
NB3L8533
Table 5. DC CHARACTERISTICS V = 2.375 V to 3.630 V; V = 0 V; T = −40°C to +85°C (Note 3)
CC
EE
A
Symbol
Characteristic
Min
Typ
Max
Unit
POWER SUPPLY
V
Power Supply Voltage
Power Supply Current (Outputs Open)
2.375
3.630
40
V
CC
EE
I
mA
LVPECL OUTPUTS (Note 4)
V
Output HIGH Voltage
V
V
−1.4
V
V
−0.9
V
V
V
OH
CC
CC
V
Output LOW Voltage
−2.0
−1.7
OL
CC
CC
V
Output Voltage Swing, Peak−to−Peak
0.6
1.0
SWING
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 5) (Note 7)
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
Common Mode Input Voltage; (Note 8)
CLK
PCLK
0.5
1.5
V
−0.85
V
V
V
V
IHD
CC
V
CLK
PCLK
0
0.5
V
IHD
V
IHD
−0.15
−0.30
ILD
V
CMR
CLK/CLKb
PCLK/PCLKb
0.5
1.5
V
CC
–0.85
V
Differential Input Voltage (V −V )
ILD
CLK/CLKb
PCLK/PCLKb
0.15
0.3
1.3
1.0
ID
IH
IHD
I
Input HIGH Current V = V = 3.630 V
CLK, PCLK
CLKb, PCLKb
150
5
mA
mA
IN
CC
I
Input LOW Current V = 0 V, V = 3.630 V
CLK, PCLK
−5
IL
IN
CC
CLKb, PCLKb
−150
LVCMOS/LVTTL INPUTS (CLK_EN, CLK_SEL)
V
Input HIGH Voltage
Input LOW Voltage
2.0
V
+0.3
V
V
IH
CC
V
−0.3
0.8
IL
I
IH
Input HIGH Current V = V = 3.630 V
CLK_EN
CLK_SEL
5
150
mA
IN
CC
I
IL
Input Low Current V = 0 V, V = 3.630 V
CLK_EN
CLK_SEL
−150
−5
mA
IN
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and Output parameters vary 1:1 with V
.
CC
4. LVPECL outputs loaded with 50 W to V − 2 V for proper operation.
CC
5. V , V , V and V parameters must be complied with simultaneously.
IH
IL
th
ISE
6. V is applied to the complementary input when operating in single−ended mode.
th
7. V , V , V and V parameters must be complied with simultaneously.
IHD
ILD
ID
CMR
8. The common mode voltage is defined as V
.
IH
www.onsemi.com
4
NB3L8533
Table 6. AC CHARACTERISTICS, V = 2.375 V to 3.630 V, T = −40°C to +85°C (Note 9)
CC
A
Symbol
Characteristic
Min
Typ
Max
Unit
f
Maximum Input Clock Frequency: V
≥ 300 mV
650
MHz
MAX
OUTpp
F
N
Phase Noise, f = 156.25 MHz
100 Hz
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
Offset from Carrier
−124.4
−136.1
−144.2
−153.3
−156.2
−156.2
−156.4
dBc/
Hz
C
t
t
,
Propagation Delay to Differential Outputs, @ 50 MHz Note 10
(Figures 6 and 7) (V = 3.3 V) Note 11
CLK/CLK to Q/Q
PCLK/PCLK to Q/Q
1.0
1.55
ns
PLH
PHL
CC
t
Additive Phase Jitter, RMS; f = 156.25 MHz,
∫F
C
N
Integration Range: 12 kHz − 20 MHz
Output−to−output skew; (Note 12)
Part−to−Part Skew; (Note 13)
0.05
ps
ps
ps
mV
ps
%
tsk(o)
30
150
1300
600
53
tsk (pp)
V
Input Voltage Swing/Sensitivity (Differential Configuration) (Note 15)
Output rise and fall times, 20% to 80%, @ 50 MHz
Output Clock Duty Cycle
150
250
47
INpp
t /t
Q , Q
n n
r
f
ODC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
All parameters measured at f
unless noted otherwise.
MAX
The cycle−to−cycle jitter on the input will equal the jitter on the output. The part does not add jitter
9. Measured using a V source, Reference Duty Cycle = 50% duty cycle clock source. All output loading with external 50 W to V − 2 V.
INPPmin
CC
10.Measured from the differential input crossing point to the differential output crossing point.
11. Measured from V /2 input crossing point to the differential output crossing point.
CC
12.Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
13.Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the
same type of inputs on each device, the outputs are measured at the differential cross points.
14.Output voltage swing is a single−ended measurement operating in differential mode.
15.Input voltage swing is a single−ended measurement operating in differential mode.
www.onsemi.com
5
NB3L8533
Figure 3. Typical Phase Noise Plot at fcarrier = 156.25 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The RMS Phase Jitter
contributed by the device (integrated between 12 kHz and
20 MHz) is 51.76 fs.
To obtain the most accurate additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is greater than the device under test output, the source
noise will dominate the additive phase jitter calculation and
lead to an artificially low result for the additive phase noise
measurement within the integration range.
The additive phase jitter performance of the fanout buffer
is highly dependent on the phase noise of the input source.
2
2
RMS additive jitter + ǸRMS phase jitter of output * RMS phase jitter of input
2
2
51.76 fs + Ǹ100.24 fs * 85.84 fs
www.onsemi.com
6
NB3L8533
V
CC
CLK
PCLK
VID
VCMR
CLK
PCLK
V
EE
Figure 4. VCMR Diagram
V
ID
= ⎜ V
− V
⎜
IHD(IN)
ILD(IN)
IN
IN
VIHD
VILD
Figure 5. Differential Inputs Driven Differentially
IN
V
CC
/ 2
V
CC
/ 2
V
INPP
= V (IN) − V (IN)
IH IL
IN
Q
CLK_SEL
tpd
tpd
Qx
Qx
Q
t
PHL
t
PLH
Figure 7. CLK_SEL to Qx Timing
Diagram
Figure 6. AC Reference Measurement
Figure 8. Differential Input Driven Single−ended
Differential Clock Input to Accept Single−ended Input
as a bypass capacitor. Locate these components close the
Figure 8 shows how the CLK input can be driven by a
device pins. R1 and R2 must be adjusted to position V to
ref
single−ended Clock signal. C1 is connected to the V node
the center of the input swing on CLK.
ref
www.onsemi.com
7
NB3L8533
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 9. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
NB3L8533DTG
TSSOP−20
(Pb−Free)
75 Units / Rail
NB3L8533DTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−20 WB
CASE 948E
ISSUE D
DATE 17 FEB 2016
SCALE 2:1
NOTES:
20X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
K
K1
M
S
S
0.10 (0.004)
T U
V
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
0.15 (0.006) T U
J J1
20
11
2X L/2
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
B
SECTION N−N
L
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
A
−V−
N
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
0.252
0.169
---
DETAIL E
C
D
0.05
0.50
0.002
0.020
F
G
H
0.65 BSC
0.026 BSC
−W−
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
C
J
J1
K
G
D
H
K1
L
DETAIL E
6.40 BSC
0.252 BSC
0
0.100 (0.004)
−T− SEATING
M
0
8
8
_
_
_
_
PLANE
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
7.06
XXXX
XXXX
ALYWG
G
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASH70169A
TSSOP−20 WB
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
©2020 ICPDF网 联系我们和版权申明