NB3N1900K [ONSEMI]
Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe;
| 型号： | NB3N1900K |
| 厂家： | 
ONSEMI |
| 描述： | Differential 1:19 HCSL Clock ZDB/Fanout Buffer for PCIe PC |
| 文件： | 总21页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3N1900K
3.3V 100/133 MHz
Differential 1:19 HCSL
Clock ZDB/Fanout Buffer for
PCIe[
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MARKING
Description
The NB3N1900K differential clock buffers are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
DIAGRAM*
1
®
distributing the reference clocks for Intel QuickPath Interconnect
1 72
NB3N
1900K
(Intel QPI), PCIe Gen1, Gen2, Gen3. The NB3N1900K internal PLL is
optimized to support 100 MHz and 133 MHz frequency operation.
The NB3N1900K supports HCSL output levels.
QFN72
MN SUFFIX
CASE 485DK
AWLYYWWG
Features
NB3N1900K = Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Fixed Feedback Path for Lowest Input−to−Output Delay
• Eight Dedicated OE# Pins for Hardware Control of Outputs
• PLL Bypass Configurable for PLL or Fanout Operation
• Selectable PLL Bandwidth
WL
YY
WW
G
• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
ORDERING INFORMATION
• SMBus Programmable Configurations
See detailed ordering and shipping information on page 20 of
this data sheet.
• 100 MHz and 133 MHz PLL Mode to Meet the Next Generation
PCIe Gen2 / Gen 3 and Intel QPI Phase Jitter
• 2 Tri−Level Addresses Selection (Nine SMBUS Addresses)
• Cycle−to−Cycle Jitter: < 50 ps
• Output−to−Output Skew: < 65 ps
• Input−to−Output Delay: Fixed at 0 ps
• Input−to−Output Delay Variation: < 50 ps
• Phase Jitter: PCIe Gen3 < 1 ps rms
• Phase Jitter: QPI 9.6GB/s < 0.2 ps rms
• QFN 72−pin Package, 10 mm x 10 mm
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
July, 2016 − Rev. 4
NB3N1900K/D
NB3N1900K
8
OE[5:12]#
FB_OUT
FB_OUT#
DIF[18:0]
SSC Compatible
PLL
MUX
DIF[18:0]#
CLK_IN
CLK_IN#
100M_133M#
HBW_BYP_LBW#
SA_0
Control
Logic
SA_1
PWRGD/PWRDN#
SDA
SCL
IREF
NOTE: Even though the feedback is fixed FB_OUT and FB_OUT# still needs a
termination network for the part to function.
Figure 1. Simplified Block Diagram of NB3N1900K
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2
NB3N1900K
72
71 70
69
68
67
66
65
64
63 62
61
60
59 58
57
56
55
VDDA
GNDA
OE11#
DIF11#
DIF11
1
2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
IREF
3
100M_133M#
4
OE10#
DIF10#
HBW_BYP_LBW#
PWRGD/PWRDN#
5
6
DIF10
OE9#
GND
VDDR
7
8
DIF9#
DIF9
CLK_IN
CLK_IN#
9
NB3N1900K
10
VDD
GND
SA_0 11
SDA
SCL
12
13
14
15
16
17
OE8#
DIF8#
DIF8
SA_1
NC
OE7#
DIF7#
NC
DIF7
FB_OUT#
FB_OUT 18
OE6#
19
20 21
22
23
24
25
26
27
28 29
30
31
32 33
34
35
36
FB_OUT pins loaded the same as the DIF outputs.
Figure 2. Pin Configuration
(Top View)
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3
NB3N1900K
Table 1. PLL OPERATING MODE READBACK TABLE
Table 5. PLL OPERATING MODE
HBW_BYP_LBW#
Low (Low BW)
Mid (Bypass)
Byte0, bit 7
Byte 0, bit 6
HBW_BYP_LBW#
MODE
PLL Lo BW
Bypass
0
0
1
0
1
1
Low
Mid
High
High (High BW)
PLL Hi BW
NOTE: PLL is OFF in Bypass
Table 2. POWER CONNECTIONS
Pin Number
Table 6. MODE TRI−LEVEL INPUT THRESHOLD
VDD
GND
Level
Low
Mid
Voltage
Description
1
8
2
7
Analog PLL
Analog Input
< 0.8 V
1.2 < Vin < 1.8 V
21, 31, 45,
58, 68
High
Vin > 2.2 V
26, 44, 63
DIF clocks
Table 3. FUNCTIONALITY AT POWER UP (PLL MODE)
CLK_IN
(MHz)
DIF
(MHz)
100M_133M#
1
0
100.00
133.33
CLK_IN
CLK_IN
Table 4. NB3N1900K SMBus ADDRESSING
Pin
SMBus Address − 8 bit
(Rd/Wrt bit = 0)
SA_1
SA_0
0
0
0
M
1
D8
DA
DE
C2
C4
C6
CA
CC
CE
0
M
M
M
1
0
M
1
0
1
M
1
1
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NB3N1900K
Table 7. PIN DESCRIPTION
Pin #
Pin Name
VDDA
Pin Type
PWR
Description
1
2
3.3 V power for the PLL core.
Ground pin for the PLL core.
GNDA
PWR
This pin establishes the reference for the differential current−mode output pairs. It
requires a fixed precision resistor to ground. 475 W is the standard value for 100 W
differential impedance. Other impedances require different values.
See data sheet.
3
IREF
OUT
Input to select operating frequency
1 = 100.00 MHz, 0 = 133.33 MHz
4
5
100M_133M#
IN
IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
HBW_BYP_LBW#
Notifies device to sample latched inputs and start up on first high assertion, or exit
Power Down Mode on subsequent assertions. Low enters Power Down Mode.
6
7
8
PWRGD/PWRDN#
GND
IN
PWR
PWR
Ground pin.
3.3 V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
VDDR
9
CLK_IN
IN
IN
0.7 V Differential true input
10
CLK_IN#
0.7 V Differential complementary Input
SMBus address bit. This is a tri−level input that works in conjunction with the SA_1
to decode 1 of 9 SMBus Addresses.
11
SA_0
IN
12
13
SDA
SCL
I/O
IN
Data pin of SMBus circuitry, 5V tolerant
Clock pin of SMBus circuitry, 5V tolerant
SMBus address bit. This is a tri−level input that works in conjunction with the SA_0
to decode 1 of 9 SMBus Addresses.
14
SA_1
IN
15
16
NC
NC
N/A
N/A
No Connection.
No Connection.
Complementary half of differential feedback output, provides feedback signal to the
PLL for synchronization with input clock to eliminate phase error.
17
18
FB_OUT#
FB_OUT
OUT
OUT
True half of differential feedback output, provides feedback signal to the PLL for
synchronization with the input clock to eliminate phase error.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DIF0
DIF0#
VDD
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply, nominal 3.3 V
DIF1
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Ground pin.
DIF1#
DIF2
DIF2#
GND
DIF3
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply, nominal 3.3 V
DIF3#
DIF4
DIF4#
VDD
DIF5
0.7 V differential true clock output
0.7 V differential complementary clock output
DIF5#
Active low input for enabling DIF pair 5.
1 = disable outputs, 0 = enable outputs
34
OE5#
IN
35
36
DIF6
OUT
OUT
0.7 V differential true clock output
DIF6#
0.7 V differential complementary clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
37
OE6#
IN
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NB3N1900K
Table 7. PIN DESCRIPTION
Pin #
38
Pin Name
DIF7
Pin Type
OUT
Description
0.7 V differential true clock output
39
DIF7#
OUT
0.7 V differential complementary clock output
Active low input for enabling DIF pair 7.
1 = disable outputs, 0 = enable outputs
40
OE7#
IN
41
42
DIF8
OUT
OUT
0.7 V differential true clock output
DIF8#
0.7 V differential complementary clock output
Active low input for enabling DIF pair 8.
1 = disable outputs, 0 = enable outputs
43
OE8#
IN
44
45
46
47
GND
VDD
PWR
PWR
OUT
OUT
Ground pin.
Power supply, nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
DIF9
DIF9#
Active low input for enabling DIF pair 9.
1 = disable outputs, 0 = enable outputs
48
OE9#
IN
49
50
DIF10
OUT
OUT
0.7 V differential true clock output
DIF10#
0.7 V differential complementary clock output
Active low input for enabling DIF pair 10.
1 = disable outputs, 0 = enable outputs
51
OE10#
IN
52
53
DIF11
OUT
OUT
0.7 V differential true clock output
DIF11#
0.7 V differential complementary clock output
Active low input for enabling DIF pair 11.
1 = disable outputs, 0 = enable outputs
54
OE11#
IN
55
56
DIF12
OUT
OUT
0.7 V differential true clock output
DIF12#
0.7 V differential complementary clock output
Active low input for enabling DIF pair 12.
1 = disable outputs, 0 = enable outputs
57
OE12#
IN
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VDD
DIF13
DIF13#
DIF14
DIF14#
GND
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
Power supply, nominal 3.3 V
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Ground pin.
DIF15
DIF15#
DIF16
DIF16#
VDD
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
Power supply, nominal 3.3 V
DIF17
DIF17#
DIF18
DIF18#
0.7 V differential true clock output
0.7 V differential complementary clock output
0.7 V differential true clock output
0.7 V differential complementary clock output
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NB3N1900K
Table 8. ABSOLUTE MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Conditions
Min
Typ
Max
4.6
Unit
V
V
DDA
3.3 V Core Supply Voltage (Note 2)
3.3 V Logic Supply Voltage (Note 2)
V
DD
4.6
V
GND −
0.5
V
Input Low Voltage
Input High Voltage
V
V
IL
V
0.5
+
DD
V
IH
Except for SMBus interface
SMBus clock and data pins
V
Input High Voltage
5.5
150
125
130
V
°C
IHSMB
T
Storage Temperature
Junction Temperature
Case Temperature
−65
s
T
°C
J
T
°C
c
ESD
qJA
qJC
ESD protection
Human Body Model
Still air
2000
V
Thermal Resistance Junction−to−Ambient
18.1
5.0
°C/W
°C/W
Thermal Resistance Junction−to−Case
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Guaranteed by design and characterization, not tested in production.
2. Operation under these conditions is neither implied nor guaranteed.
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NB3N1900K
Table 9. ELECTRICAL CHARACTERISTICS − INPUT/SUPPLY/COMMON PARAMETERS
(V = V
= 3.3 V 5%, T = −10°C to +70°C), See Test Loads for Loading Conditions.
DD
DDA
A
Symbol
Parameter
Input High Voltage
Conditions
Min
Typ
Max
Unit
Single−ended inputs, except SMBus, low
threshold and tri−level inputs (Note 3)
V
+
DD
0.3
V
2
V
IH
Single−ended inputs, except SMBus, low
threshold and tri−level inputs (Note 3)
GND −
0.3
V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input Current
0.8
V
V
IL
V
V
0.3
+
IH_FS
(Note 4)
DD
0.7
V
GND −
0.3
IL_FS
(Note 4)
0.35
5
V
Single−ended inputs, V = GND, V = V
IN
IN
DD
I
−5
mA
IN
(Note 3)
F
V
= 3.3 V, Bypass mode (Notes 3, 5 and 6)
= 3.3 V, 100.00 MHz PLL mode (Note 5)
DD
33
99
400
101
MHz
MHz
MHz
nH
IBYP
DD
F
Input Frequency
Pin Inductance
V
100.00
IPLL
IPLL
F
V
DD
= 3.3 V, 133.33 MHz PLL mode (Notes 5) 132.33 133.33 134.33
L
(Note 3)
7
5
PIN
C
Logic Inputs, except CLK_IN (Note 3)
1.5
1.5
pF
IN
CLK_IN differential clock inputs
(Notes 3 and 7)
C
Capacitance
2.7
6
pF
pF
INDIF_IN
C
Output pin capacitance (Note 3)
OUT
From V Power−Up and after input clock
DD
stabilization or de−assertion of PD# to 1st
clock (Notes 3 and 5)
T
STAB
Clk Stabilization
1.8
ms
Allowable Frequency (Triangular Modulation)
(Note 3)
f
Input SS Modulation Frequency
OE# Latency
30
4
33
12
kHz
cycles
ms
DIF start after OE# assertion DIF stop after
OE# de−assertion (Note 3)
t
LATOE#
DIF output enable after PD# de−assertion
(Note 3)
t
Tdrive_PD#
300
DRVPD
t
Tfall
Fall time of control inputs (Notes 3 and 5)
5
5
ns
ns
V
F
t
R
Trise
Rise time of control inputs (Notes 3 and 5)
V
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCL/SDA Rise Time
SCL/SDA Fall Time
(Note 3)
(Note 3)
0.8
ILSMB
IHSMB
V
2.1
V
V
DDSMB
V
@ I
(Note 3)
0.4
V
OLSMB
PULLUP
PULLUP
I
@ V (Note 3)
4
mA
V
OL
V
3 V to 5 V 10% (Note 3)
2.7
5.5
1000
300
DDSMB
t
(Max V − 0.15) to (Min V + 0.15) (Note 3)
ns
ns
RSMB
IL
IH
t
(Min VIH + 0.15) to (Max V − 0.15) (Note 3)
FSMB
IL
Maximum SMBus operating frequency
(Notes 3 and 8)
f
SMBus Operating Frequency
100
kHz
MAXSMB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Guaranteed by design and characterization, not tested in production.
4. 100M_133M# Frequency Select (FS).
5. Control input must be monotonic from 20% to 80% of input swing.
6. Fmax measured until output violates output duty cycle specifications and output V
7. CLK_IN input
, V
Low
specification.
High
8. The differential input clock must be running for the SMBus to be active.
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NB3N1900K
Table 10. ELECTRICAL CHARACTERISTICS − CLOCK INPUT PARAMETERS
(V = V
= 3.3 V 5%, T = −10°C to +70°C), See Test Loads for Loading Conditions.
DD
DDA
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input High Voltage − CLK_IN
(Note 9)
Differential inputs (single−ended
measurement)
V
IHDIF
600
1150
mV
Input Low Voltage − CLK_IN
(Note 9)
Differential inputs (single−ended
measurement)
V
300
−
SS
V
ILDIF
300
mV
Input Common Mode Voltage −
CLK_IN (Note 9)
V
Common Mode Input Voltage
Peak to Peak value
300
300
0.4
1000
1450
8
mV
mV
COM
V
Input Amplitude − CLK_IN (Note 9)
SWING
Input Slew Rate − CLK_IN (Notes 9
and 10)
dv/dt
Measured differentially
V/ns
I
Input Leakage Current (Note 9)
Input Duty Cycle (Note 9)
V
= V V = GND
DD, IN
−5
45
0
5
mA
%
IN
IN
d
Measurement from differential waveform
Differential Measurement
55
tin
J
Input Jitter − Cycle to Cycle (Note 9)
125
ps
DIFIn
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Guaranteed by design and characterization, not tested in production.
10.Slew rate measured through 75 mV window centered around differential zero.
Table 11. ELECTRICAL CHARACTERISTICS − DIF 0.7 V CURRENT MODE DIFFERENTIAL OUTPUTS
(V = V
= 3.3 V 5%, T = −10°C to +70°C), See Test Loads for Loading Conditions
DD
DDA
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
dV/dt
Slew rate (Notes 11, 12 and 13)
Scope averaging on
1
4
V/ns
Slew rate matching
(Notes 11, 12 and 14)
DdV/dt
DTrf
Slew rate matching, Scope averaging on
Rise/fall matching, Scope averaging off
20
%
Rise/Fall Time Matching
(Notes 11, 12 and 18)
125
ps
Statistical measurement on single−ended
signal using oscilloscope math function.
(Scope averaging on)
V
Voltage High (Note 11)
Voltage Low (Note 11)
Max Voltage (Note 11)
Min Voltage (Note 11)
Vswing (Notes 11 and 12)
660
850
150
High
mV
mV
V
V
−150
Low
1150
max
Measurement on single ended signal using
Absolute value. (Scope averaging off)
V
−300
300
min
V
swing
Scope averaging off
Scope averaging off
mV
mV
Crossing Voltage (abs)
(Notes 11 and 15)
V
250
550
140
cross_abs
Crossing Voltage (var)
(Notes 11 and 16)
DV
Scope averaging off
mV
cross
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Guaranteed by design and characterization, not tested in production. I
= V /(3xR
). For R
= 475 W (1%), I
= 2.32 mA. I
REF OH
REF
DD
REF
REF
= 6 x I
and V = 0.7 V @ Z = 50 W (100 W differential impedance).
REF
OH O
12.Measured from differential waveform.
13.Slew rate is measured through the Vswing voltage range centered around differential 0 V. This results in a 150 mV window around
differential 0 V.
14.Matching applies to rising and falling edge rate of differential waveform. It is measured using a 75 mV window centered on the average cross
point where the clock rising meets clock# falling. The median cross point is used to calculate voltage thresholds that the oscilloscope uses
to calculate the slew rate. Measurement taken using a 100 W differential impedance 5” trace PCB.
15.Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
16.The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross absolute)
allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
17.Measured from single−ended waveform
18.Measured with scope averaging off, using statistics function. Variation is difference between min and max.
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NB3N1900K
Table 12. ELECTRICAL CHARACTERISTICS − CURRENT CONSUMPTION
(V = V
= 3.3 V 5%, T = −10°C to +70°C), See Test Loads for Loading Conditions
DD
DDA
A
Symbol
Parameter
Conditions
Min
Typ
Max
550
36
Unit
mA
mA
All outputs active @ 100.00 MHz,
CL = Full load
I
Operating Supply Current (Note 19)
DD3.3OP
I
Powerdown Current (Note 19)
All differential pairs tri−stated
DD3.3PDZ
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
19.Guaranteed by design and characterization, not tested in production.
Table 13. ELECTRICAL CHARACTERISTICS − SKEW AND DIFFERENTIAL JITTER PARAMETERS
(V = V
= 3.3 V 5%, T = −10°C to +70°C), See Test Loads for Loading Conditions
DD
DDA
A
Symbol
Parameter
CLK_IN, DIF[x:0]
Conditions
Min
Typ
Max
Unit
Input−to−Output Skew in PLL mode nominal
t
−100
100
ps
SPO_PLL
(Notes 20, 21, 23, 24 and 27)
value @ 25°C, 3.3 V
CLK_IN, DIF[x:0]
(Notes 20, 21, 22, 24 and 27)
Input−to−Output Skew in Bypass mode
t
2.5
4.5
|100|
250
65
ns
ps
ps
ps
dB
dB
PD_BYP
nominal value @ 25°C, 3.3 V
Input−to−Output Skew Variation in PLL mode
across voltage and temperature
CLK_IN, DIF[x:0]
(Notes 20, 21, 22, 24 and 27)
t
DSPO_PLL
CLK_IN, DIF[x:0]
(Notes 20, 21, 22, 24 and 27)
Input−to−Output Skew Variation in Bypass
mode across voltage and temperature
t
−250
DSPO_BYP
Output−to−Output Skew across all outputs
(Common to Bypass and PLL mode)
t
DIF{x:0] (Notes 20, 21, 22 and 27)
SKEW_ALL
PLL Jitter Peaking
(Notes 26 and 27)
j
HBW_BYP_LBW# = 1
0
0
2.5
2
peak−hibw
peak−lobw
PLL Jitter Peaking
(Notes 26 and 27)
j
HBW_BYP_LBW# = 0
pll
PLL Bandwidth (Notes 27 and 28)
PLL Bandwidth (Notes 27 and 28)
Duty Cycle (Notes 20 and 27)
HBW_BYP_LBW# = 1
HBW_BYP_LBW# = 0
2
4
MHz
MHz
%
HIBW
pll
LOBW
0.7
45
1.4
55
t
Measured differentially, PLL Mode
50
0
DC
Duty Cycle Distortion
(Notes 20 and 29)
Measured differentially, Bypass Mode
@ 100.00 MHz
t
−2
2
%
DCD
PLL mode
50
50
ps
ps
Jitter, Cycle to cycle
(Notes 20, 27 and 30)
t
jcyc−cyc
Additive Jitter in Bypass Mode
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
20.Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
21.Measured from differential cross−point to differential cross−point. This parameter can be tuned with external feedback path, if present.
22.All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it.
23.This parameter is deterministic for a given device.
24.Measured with scope averaging on to find mean value. CLK_IN slew rate must be matched to DIF output slew rate.
25.t is the period of the input clock.
26.Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
27.Guaranteed by design and characterization, not tested in production.
28.Measured at 3 db down or half power point.
29.Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
@ 100.00 MHz.
30.Measured from differential waveform.
www.onsemi.com
10
NB3N1900K
Table 14. ELECTRICAL CHARACTERISTICS − PHASE JITTER PARAMETERS
(V = V
= 3.3 V 5%, T = −10°C to +70°C), See Test Loads for Loading Conditions.
DD
DDA
A
Symbol
Parameter
Conditions (Notes 31 and 36)
Min
Typ
Max
Unit
t
PCIe Gen 1 (Notes 32 and 33)
36
86
ps (p−p)
jphPCIeG1
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Note 32)
ps
(rms)
3
t
jphPCIeG2
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Note 32)
ps
(rms)
3.1
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Note 32)
ps
(rms)
t
1
jphPCIeG3
Jitter, Phase
QPI & SMI
(100.00 MHz or 133.33 MHz,
4.8 Gb/s, 6.4 Gb/s 12UI) (Note 34)
ps
(rms)
0.5
0.3
QPI & SMI
(100.00 MHz, 8.0 Gb/s, 12UI) (Note 34)
ps
(rms)
t
jphQPI_SMI
QPI & SMI
(100.00 MHz, 9.6 Gb/s, 12UI) (Note 34)
ps
(rms)
0.2
10
t
PCIe Gen 1 (Notes 32 and 33)
ps (p−p)
jphPCIeG1
PCIe Gen 2 Lo Band
10 kHz < f < 1.5 MHz (Notes 32 and 35)
ps
(rms)
0.3
t
jphPCIeG2
PCIe Gen 2 High Band
1.5 MHz < f < Nyquist (50 MHz)
(Notes 32 and 35)
ps
(rms)
0.7
0.3
0.3
PCIe Gen 3
(PLL BW of 2−4 MHz, CDR = 10 MHz)
(Notes 32 and 35)
ps
(rms)
t
Additive Phase Jitter, Bypass
mode
jphPCIeG3
QPI & SMI
(100.00 MHz or 133.33 MHz, 4.8 Gb/s,
6.4 Gb/s 12UI) (Notes 34 and 35)
ps
(rms)
QPI & SMI
ps
(rms)
t
jphQPI_SMI
0.1
0.1
(100.00 MHz, 8.0 Gb/s, 12UI) (Notes 34 and 35)
QPI & SMI
ps
(rms)
(100.00 MHz, 9.6 Gb/s, 12UI) (Notes 34 and 35)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
31.Applies to all outputs.
32.See http://www.pcisig.com for complete specs
33.Sample size of at least 100K cycles. This figures extrapolates to 108 ps pk−pk @ 1M cycles for a BER of 1−12.
34.Calculated from Intel−supplied Clock Jitter Tool v 1.6.3.
35.For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) = (total jitter) - (input jitter)
2
2
2
36.Guaranteed by design and characterization, not tested in production
www.onsemi.com
11
NB3N1900K
Table 15. CLOCK PERIODS − DIFFERENTIAL OUTPUTS WITH SPREAD SPECTRUM DISABLED
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
−SSC
− ppm
Long−Term
Average
Min
+SSC
Short−Term
Average
Min
−c2c jitter
AbsPer
Min
0 ppm
Period
+ ppm Long−
Term Average
Max
+c2c jitter
AbsPer
Max
Center
Short−Term
Average Max
Nominal
Freq. MHz
Unit Notes
SSC OFF
37,
ns
100.00
133.33
9.94900
7.44925
9.99900
7.49925
10.00000
7.50000
10.00100
7.50075
10.05100
7.55075
38, 39
DIF
37,
ns
38, 40
37.Guaranteed by design and characterization, not tested in production.
38.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy
requirements ( 100 ppm). The 9ZX21901 itself does not contribute to ppm error.
39.Driven by SRC output of main clock, 100.00 MHz PLL Mode or Bypass mode
40.Driven by CPU output of main clock, 133.33 MHz PLL Mode or Bypass mode
Table 16. CLOCK PERIODS − DIFFERENTIAL OUTPUTS WITH SPREAD SPECTRUM ENABLED
Measurement Window
1 Clock
1us
0.1s
0.1s
0.1s
1us
1 Clock
−SSC
− ppm
Long−Term
Average
Min
+SSC
Short−Term
Average
Min
−c2c jitter
AbsPer
Min
0 ppm
Period
+ ppm
Long−Term
Average Max
+c2c jitter
AbsPer
Max
Center
Short−Term
Average Max
Nominal
Freq. MHz
SSC ON
Unit Notes
41,
ns
99.75
9.94906
7.44930
9.99906
7.49930
10.02406
7.51805
10.02506
7.51880
10.02607
7.51955
10.05107
7.53830
10.10107
7.58830
42, 43
DIF
41,
ns
133.00
42, 44
41.Guaranteed by design and characterization, not tested in production.
42.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+ accuracy
requirements ( 100 ppm). The 9ZX21901 itself does not contribute to ppm error.
43.Driven by SRC output of main clock, 100.00 MHz PLL Mode or Bypass mode
44.Driven by CPU output of main clock, 133.33 MHz PLL Mode or Bypass mode
Table 17. POWER MANAGEMENT TABLE
Inputs
Control Bits/Pins
DIF(5:12) /
Outputs
Other DIF/
DIF#
FB_OUT /
FB_OUT#
PLL
State
DIF(5:12)#
PWRGD/PWRDN# CLK_IN/CLK_IN# SMBus EN bit
OE# Pin
0
X
X
0
1
1
X
X
0
1
Hi−Z (Note 45) Hi−Z (Note 45)
Hi−Z (Note 45) Hi−Z (Note 45)
Hi−Z (Note 45)
Running
OFF
ON
ON
ON
Running
Running
Running
Running
1
Running
Hi−Z (Note 45)
Running
45.Due to external pull down resistors, HI−Z results in Low/Low on the True/Complement outputs
www.onsemi.com
12
NB3N1900K
10 inches
Differential Zo
Rs
Rs
2pF
2pF
Rp
Rp
HCSL Output
Buffer
Figure 3. NB3N1900K Differential Test Loads
Table 18. DIFFERENTIAL OUTPUT TERMINATION TABLE
DIF Zo (W)
100
Iref (W)
475
Rs (W)
33
Rp (W)
50
85
412
27
42.2 or 43.2
PWRGD/PWRDN#
asserted low by two consecutive rising edges of DIF#, all
differential outputs are held tri−stated on the next DIF# high
to low transition. The assertion and de-assertion of
PWRDN# is absolutely asynchronous.
PWRGD/PWRDN# is a dual function pin. PWRGD is
asserted high and de−asserted low. De−assertion of PWRGD
(pulling the signal low) is equivalent to indicating a
powerdown condition. PWRGD (assertion) is used by the
NB3N1900K to sample initial configurations such as
frequency select condition and SA selections.
After PWRGD has been asserted high for the first time,
the pin becomes a PWRDN# (Power Down) pin that can be
used to shut off all clocks cleanly and instruct the device to
invoke power savings mode. PWRDN# is a completely
asynchronous active low input. When entering power
savings mode, PWRDN# should be asserted low prior to
shutting off the input clock or power to ensure all clocks
shut down in a glitch free manner. When PWRDN# is
WARNING: Disabling of the CLK_IN input clock prior
to assertion of PWRDN# is an undefined
mode and not recommended. Operation in
this mode may result in glitches, excessive
frequency shifting, etc.
Table 19. PWRGD/PWRDN# FUNCTIONALITY
PWRGD/PWRDN#
DIF
DIF#
0
1
Tri−state
Running
Tri−state
Running
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13
NB3N1900K
Buffer Power−Up State Machine
Table 20. BUFFER POWER−UP STATE MACHINE
State
Description
0
1
2
3
3.3 V Buffer power off
After 3.3 V supply is detected to rise above 3.135 V, the buffer enters State 1 and initiates a 0.1 ms–0.3 ms delay.
Buffer waits for a valid clock on the CLK input and PWRDN# de−assertion (or PWRGD assertion low to high)
Once the PLL is locked to the CLK_IN input clock, the buffer enters state 3 and enables outputs for normal operation.
(Notes 46, 47)
46.The total power up latency from power on to all outputs active must be less than 1.8 ms (assuming a valid clock is present on CLK_IN input).
47.If power is valid and powerdown is de−asserted (PWRGD asserted) but no input clocks are present on the CLK_IN input, DIF clocks must
remain disabled. Only after valid input clocks are detected, valid power, PWRDN# de−asserted (PWRGD asserted) with the PLL
locked/stable and the DIF outputs enabled.
No input clock
State 1
State 2
Wait for input
clock and
powerdown
de−assertion
Delay
0.1 ms − 0.3 ms
Powerdown Asserted
State 3
State 0
Normal
Operation
Power Off
Figure 4. Buffer Power−Up State Diagram
Device Power−Up Sequence
3. Apply power to the device.
Follow the power−up sequence below for proper device
functionality:
4. Once the VDD pin has reached a valid VDDmin
level (3.3V −5%), the PWRGD/PWRDN# pin
must be asserted High. See Figure 5.
1. PWRGD/PWRDN# pin must be Low.
2. Assign remaining control pins to their required
state (100M_133M#, HBW_BYPASS_LBW#,
SDA, SCL)
Note: If no clock is present on the CLK_IN/CLK_IN#
pins when device is powered up, there will be no clock on
DIF/DIF# outputs.
Figure 5. PWRGD and VDD Relationship Diagram
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14
NB3N1900K
GENERAL SMBUS SERIAL INTERFACE INFORMATION FOR THE NB3N1900K
How to Write:
• Clock(device) will acknowledge
• Controller (host) sends a start bit.
• Controller (host) sends the write address XX
• Clock(device) will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address YY
(H)
(H)
• Clock(device) will acknowledge
• vclock will send the data byte count = X
• Clock(device) sends Byte N + X −1
• Controller (host) sends the beginning byte location = N
• Clock(device) will acknowledge
• Controller (host) sends the data byte count = X
• Clock(device) will acknowledge
• Clock(device) sends Byte 0 through byte X (if X was
(H)
written to byte 8).
• Controller (host) starts sending Byte N through Byte
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) sends a Stop bit
N + X − 1
• Clock(device) will acknowledge each byte one at a
time
• Controller (host) sends a Stop bit
Table 22. INDEX BLOCK READ OPERATION
Controller (Host)
Clock (Device)
Table 21. INDEX BLOCK WRITE OPERATION
T
starT bit
Controller (Host)
Clock (Device)
Slave Address XX(H)
T
starT bit
WR
WRite
Slave Address XX(H)
ACK
ACK
WR
WRite
Beginning Byte = N
ACK
ACK
ACK
Beginning Byte = N
Data Byte Count = X
Beginning Byte N
RT
Repeat starT
Slave Address YY(H)
RD
ReaD
ACK
ACK
Data Byte Count = X
ACK
ACK
O
O
O
O
O
Beginning Byte N
X Byte
O
O
O
Byte N + X - 1
O
O
O
X Byte
ACK
P
stoP bit
Note: XX is defined by SMBus address select pins
(H)
Byte N + X - 1
Not
acknowledge
How to Read:
N
P
• Controller (host) will send start bit.
• Controller (host) sends the write address XX
• Clock(device) will acknowledge
stoP bit
(H)
Note: XX is defined by SMBus address select pins
(H)
• Controller (host) sends the beginning byte location = N
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15
NB3N1900K
Table 23. SMBusTable: PLL MODE, AND FREQUENCY SELECT REGISTER
Byte 0 Pin #
Name
Control Function
PLL Operating Mode Rd back 1
PLL Operating Mode Rd back 0
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Reserved
Type
R
0
1
Default
Bit 7
Bit 6
5
5
PLL Mode 1
PLL Mode 0
DIF_18_En
DIF_17_En
DIF_16_En
Latch
See PLL Operating Mode
Readback Table
R
Latch
Bit 5 72/71
Bit 4 70/69
Bit 3 67/66
Bit 2
RW
RW
RW
Hi−Z
Hi−Z
Hi−Z
Enable
Enable
Enable
1
1
1
0
Bit 1
Reserved
0
Bit 0
4
100M_133M#
Frequency Select Readback
R
133 MHz
100 MHz
Latch
Table 24. SMBusTable: OUTPUT CONTROL REGISTER
Byte 1 Pin #
Bit 7 39/38
Bit 6 35/36
Bit 5 32/33
Bit 4 29/30
Bit 3 27/28
Bit 2 24/25
Bit 1 22/23
Bit 0 19/20
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF_7_En
DIF_6_En
DIF_5_En
DIF_4_En
DIF_3_En
DIF_2_En
DIF_1_En
DIF_0_En
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
1
1
1
1
1
1
1
1
Hi−Z
Enable
Table 25. SMBusTable: OUTPUT CONTROL REGISTER
Byte 2 Pin #
Bit 7 65/64
Bit 6 62/61
Bit 5 60/59
Bit 4 56/55
Bit 3 53/52
Bit 2 50/49
Bit 1 47/46
Bit 0 42/41
Name
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
DIF_15_En
DIF_14_En
DIF_13_En
DIF_12_En
DIF_11_En
DIF_10_En
DIF_9_En
DIF_8_En
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
Output Control overrides OE# pin
1
1
1
1
1
1
1
1
Hi−Z
Enable
Table 26. SMBusTable: OUTPUT ENABLE PIN STATUS READBACK REGISTER
Byte 3 Pin #
Name
Control Function
Type
R
0
1
Default
Real time
Real time
Real time
Real time
Real time
Real time
Real time
Real time
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
57
54
51
48
43
40
37
34
OE_RB12
OE_RB11
OE_RB10
OE_RB9
OE_RB8
OE_RB7
OE_RB6
OE_RB5
Real Time readback of OE#12
Real Time readback of OE#11
Real Time readback of OE#10
Real Time readback of OE#9
Real Time readback of OE#8
Real Time readback of OE#7
Real Time readback of OE#6
Real Time readback of OE#5
R
R
R
OE# Pin High
OE# pin Low
R
R
R
R
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16
NB3N1900K
Table 27. SMBusTable: RESERVED REGISTER
Byte 4 Pin #
Bit 7
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 28. SMBusTable: VENDOR & REVISION ID REGISTER
Byte 5 Pin #
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
−
−
−
−
−
−
−
X
X
X
X
1
1
1
1
R
REVISION ID
−
R
R
R
−
−
−
−
−
−
−
−
R
VENDOR ID
R
R
Table 29. SMBusTable: DEVICE ID
Byte 6 Pin #
Name
Control Function
Type
R
0
1
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
−
−
−
−
−
−
−
Device ID 7 (MSB)
1
1
0
1
1
0
1
1
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
R
R
R
Device ID is 120 decimal or
78 hex.
R
R
R
R
Table 30. SMBusTable: BYTE COUNT REGISTER
Byte 7 Pin #
Bit 7
Name
Control Function
Reserved
Type
0
1
Default
0
0
0
0
1
0
0
0
Bit 6
Reserved
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
−
−
−
−
−
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
Default value is 8 hex, so 9
bytes (0 to 8) will be read
back by default.
Writing to this register configures how
many bytes will be read back.
www.onsemi.com
17
NB3N1900K
Table 31. SMBusTable: RESERVED REGISTER
Byte 8 Pin #
Bit 7
Name
Control Function
Type
0
1
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIF Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
Unit
inch
inch
inch
W
L1 length, route as non−coupled 50 W trace (Figure 6)
L2 length, route as non−coupled 50 W trace (Figure 6)
L3 length, route as non−coupled 50 W trace (Figure 6)
Rs (Figure 6)
0.5 max
0.2 max
0.2 max
33
Rt (Figure 6)
49.9
W
Down Device Differential Routing
L4 length, route as coupled microstrip 100 W differential trace (Figure 6)
L4 length, route as coupled stripline 100 W differential trace (Figure 6)
2 min to 16 max
inch
inch
1.8 min to 14.4 max
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100 W differential trace (Figure 7)
L4 length, route as coupled stripline 100 W differential trace (Figure 7)
0.25 to 14 max
inch
inch
0.225 min to 12.6 max
L2
L1
Rs
Rs
L4
L4’
L2’
L1’
Rt
Rt
HCSL Output Buffer
PCI Express
Down Device
REF_CLK Input
L3’
L3
Figure 6. Down Device Routing
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18
NB3N1900K
L2
L1
Rs
Rs
L4
L4’
L2’
L1’
Rt
Rt
HCSL Output Buffer
PCI Express
Add−in Board
REF_CLK Input
L3’
L3
Figure 7. PCI Express Connector Routing
Table 32. ALTERNATIVE TERMINATION FOR LVDS AND OTHER COMMON DIFFERENTIAL SIGNALS (Figure 8)
Vdiff (V)
0.45
Vpp (V)
0.22
Vcm (V)
1.08
0.6
R1 (W)
33
R2 (W)
150
R3 (W)
100
R4 (W)
100
Note
0.58
0.28
33
78.7
174
137
100
0.60
0.3
1.2
33
140
100
Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
L2
L1
R3
R4
R1a
L4
L4’
L2’
L1’
R1b
R2a
R2b
HCSL Output Buffer
Down Device
REF_CLK Input
L3’
L3
Figure 8. Alternate Termination for LVDS
Table 33. CABLE CONNECTED AC COUPLED APPLICATION (Figure 9)
Component
R5a, R5b
R6a, R6b
Cc
Value
8.2k 5%
1k 5%
Note
0.1 mF
Vcm
0.350 V
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19
NB3N1900K
3.3 V
R5a
R6a
R5b
R6b
Cc
L4
L4’
Cc
Figure 9. Cable−Connected AC Coupled Application
POWER FILTERING EXAMPLE
Ferrite Bead Power Filtering
Recommended ferrite bead filtering equivalent to the following:
600 W impedance at 100 MHz, ≤ 0.1 W DCR max., ≥ 800 mA current rating.
V3P3
Place at pin
VDD for PLL
FB1
R1
2.2
VDDA
C7
FERRITE
C9
1 mF
0.1 mF
R2
2.2
VDDR
C8
VDD for Input Receiver
VDD
C10
1 mF
0.1 mF
F C5
C5
0.1 mF
0.1 mF
VDD
C2
C1
10 mF
C4
0.1 mF
C3
0.1 mF
C5
0.1 mF
C5
0.1 mF
0.1 mF
Figure 10. Schematic Example of the NB3N1900K Power Filtering
Table 34. ORDERING INFORMATION
†
Device
Package
Shipping
NB3N1900KMNG
QFN−72
(Pb−Free)
168 Units / Tray
1000 / Tape & Reel
1000 / Tape & Reel
NB3N1900KMNTXG
NB3N1900KMNTWG
QFN−72
(Pb−Free)
QFN−72
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Pin 1 orientation for TWG Suffix is Quadrant 1, upper left; Pin 1 orientation for TXG Suffix is Quadrant 2, upper right
www.onsemi.com
20
NB3N1900K
PACKAGE DIMENSIONS
QFN72 10x10, 0.5P
CASE 485DK
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A B
L
L
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
LOCATION
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
EXPOSED Cu
MOLD CMPD
0.18
0.30
D
D2
E
10.00 BSC
0.15
C
5.85
6.15
10.00 BSC
E2
e
L
5.85
0.50 BSC
0.30
0.00
6.15
0.15
C
TOP VIEW
DETAIL B
0.50
0.15
ALTERNATE
L1
CONSTRUCTION
DETAIL B
(A3)
0.10
C
C
RECOMMENDED
SOLDERING FOOTPRINT*
A
0.08
A1
72X
0.63
10.30
6.25
SEATING
PLANE
NOTE 4
C
SIDE VIEW
D2
M
0.10
C A B
1
DETAIL A
72X
L
19
36
M
0.10
C A B
10.30
6.25
E2
72X
0.32
PKG
OUTLINE
0.50
PITCH
1
DIMENSIONS: MILLIMETERS
55
72
72X b
e
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
M
M
0.10
C
C
A B
NOTE 3
0.05
BOTTOM VIEW
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