NB3N2304NZDTR2G [ONSEMI]
3.3V 1:4 Clock Fanout Buffer; 3.3V 1 ： 4时钟扇出缓冲器
| 型号： | NB3N2304NZDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V 1:4 Clock Fanout Buffer |
| 文件： | 总7页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3N2304NZ
3.3V 1:4 Clock Fanout
Buffer
Description
The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer,
designed for high speed clock distribution such as in PCI−X
applications. The NB3N2304NZ guarantees low output−to−output
skew. Optimal design, layout and processing minimizes skew within a
device and from device−to−device.
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MARKING
DIAGRAM*
The Output Enable (OE) pin forces the outputs LOW when LOW.
40N
YWW
AG
Features
• Input/Output Clock Frequency up to 140 MHz
• Low Skew Outputs (100 ps)
• Output Enable
TSSOP−8
DT SUFFIX
CASE 948S
• Operating Range: V = 3.0 V to 3.6 V
DD
• Ideal for PCI−X and networking clocks
• Packaged in 8−pin TSSOP, 4.4 mm x 3 mm
• Industrial Temperature Range
1
1
4
DFN8
MN SUFFIX
CASE 506AA
• These are Pb−Free Devices*
A
Y
= Assembly Location
= Year
WW = Work Week
G
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
January, 2007 − Rev. 1
NB3N2304NZ/D
NB3N2304NZ
Logic
OE
IN
Control
IN
Q4
Q3
1
2
3
4
8
7
6
5
Q1
Q2
Q3
Q4
OE
Q1
V
DD
GND
Q2
Figure 2. Block Diagram
Figure 3. NB3N2304NZ Package Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
Pin #
Type
Description
1
2
IN
LVCMOS/LVTTL Input
LVCMOS/LVTTL Input
Clock Input
OE
Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs
are forced to logic LOW when OE is forced LOW.
3
4
5
6
7
8
Q1
GND
Q2
LVCMOS/LVTTL Output
Power
Clock Output 1
Negative Supply Voltage; Connect to Ground, 0 V
Clock Output 2
(LV)CMOS/(LV)TTL Input
Power
V
DD
Positive Supply Voltage (3.0 V to 3.6 V)
Q3
Q4
(LV)CMOS/(LV)TTL Output Clock Output 3
(LV)CMOS/(LV)TTL Input Clock Output 4
Table 2. OE, OUTPUT ENABLE FUNCTION TABLE
Inputs
Outputs
IN
L
OE
L
L
L
H
L
L
H
L
H
H
H
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2
NB3N2304NZ
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 2kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−O @ 0.125 in
480 Devices
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
GND = 0 V
Condition 2
Rating
V + 0.5V
DD
Unit
V
V
DD
V
I
Input Voltage
GND – 0.5 v
V
V v V + 0.5
I
DD
T
Operating Temperature Range, Industrial
Storage Temperature Range
w −40 to v +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
°C/W
°C
JC
T
SOL
Wave Solder
Pb−Free (Note 2)
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. EDEC standard multilayer board − 2S2P (2 signal, 2 power).
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3
NB3N2304NZ
Table 5. DC CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0 V, T = −40°C to +85°C
DD
A
Symbol
Characteristic
Min
Typ
Max
Unit
mA
V
I
Power Supply Current @ 66.66 MHz, Unloaded Outputs
12
25
DD
V
OH
Output HIGH Voltage
− IOH = −24 mA
−IOH = −12 mA
2.0
2.4
V
OL
Output LOW Voltage
−IOL = 24 mA
−IOL = 12 mA
0.8
0.55
V
V
V
Input HIGH Voltage, IN and OE (Note 3)
Input LOW Voltage, IN and OE (Note 3)
2.0
V
IH
0.8
50
100
7
V
IL
I
IH
I
IL
Input HIGH Current, V = V
DD
−50
mA
mA
pF
IN
Input LOW Current, V = 0 V
−100
IN
CIN
Input Capacitance, IN, OE
5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. IN input has a threshold voltage of V /2.
DD
Table 6. AC CHARACTERISTICS V = 3.0 V to 3.6 V, GND = 0 V, T = −40°C to +85°C (Note 4) (Figure 4)
DD
A
Symbol
Characteristic
Min
DC
40
Typ
Max
140
60
Unit
MHz
%
f
t
Input Clock Frequency
in
Duty Cycle Skew = t2 ÷ t1 (Figure 4) Measured at 1.5 V
Output Rise and Fall Times; 0.8 V to 2.0 V
Propagation Delay, IN−to−Qn (Note 5)
50
0.9
3.5
DCskew
tr/tf
1.5
5
ns
t
t
t
2.5
ns
pd
Output−to−Output Skew; (Note 5)
100
50
ps
skew
pu
Powerup Time for V to Reach Minimum Specified Voltage
0.05
ms
DD
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. All outputs loaded equally with C = 25 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between
L
V
DD
and GND.
5. Measured on rising edges at V B 2; all outputs with equal loading.
DD
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4
NB3N2304NZ
t
1
Duty Cycle Timing
t
2
1.5 V
1.5 V
1.5 V
All Outputs Rise/Fall Time
2.0 V
0.8 V
3.3 V
0 V
2.0 V
0.8 V
OUTPUT
Output−Output Skew
OUTPUT
t
r
t
f
1.5 V
1.5 V
OUTPUT
t
SKEW
Input−Output Propagation Delay
V
DD
/2
INPUT
V
DD
/2
OUTPUT
t
pd
Figure 4. Switching Waveforms
ORDERING INFORMATION
†
Device
Package
Shipping
NB3N2304NZDTG
TSSOP−8
(Pb−Free)
100 Units / Rail
2500 / Tape & Reel
1000 / Tape & Reel
NB3N2304NZDTR2G
NB3N2304NZMNR4G*
TSSOP−8
(Pb−Free)
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Contact a sales representative.
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5
NB3N2304NZ
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S−01
ISSUE B
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.20 (0.008) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
0.20 (0.008) T U
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
4.50
1.10
0.15
0.70
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
−−−
0.114
0.169
−−−
−W−
C
C
0.076 (0.003)
D
0.05
0.50
0.002
0.020
F
DETAIL E
SEATING
D
−T−
G
G
J
0.65 BSC
0.026 BSC
PLANE
0.09
0.09
0.19
0.19
0.20
0.16
0.30
0.25
0.004
0.004
0.007
0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
P
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
P
0
8
8
_
_
_
_
−−−
−−−
2.20
3.20
−−−
−−−
0.087
0.126
N
P1
P1
F
DETAIL E
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6
NB3N2304NZ
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
8 X b
0.05
C
NOTE 3
BOTTOM VIEW
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NB3N2304NZ/D
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