NB4N840M_14 [ONSEMI]
3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch;
| 型号： | NB4N840M_14 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch |
| 文件： | 总9页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB4N840M
3.3V 3.2Gb/s Dual
Differential Clock/Data 2 x 2
Crosspoint Switch with
CML Output and Internal
Termination
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MARKING
Description
DIAGRAM
The NB4N840M is a high−bandwidth fully differential dual
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for
applications such as SDH/SONET, DWDM, Gigabit Ethernet and
high speed switching. Fully differential design techniques are used to
minimize jitter accumulation, crosstalk, and signal skew, which make
this device ideal for loop−through and protection channel switching
applications.
Internally terminated differential CML inputs accept AC−coupled
LVPECL (Positive ECL) or direct coupled CML signals. By providing
internal 50 W input and output termination resistor, the need for
external components is eliminated and interface reflections are
minimized. Differential 16 mA CML outputs provide matching
internal 50 W terminations, and 400 mV output swings when
1
32
1
NB4N
840M
ALYWG
QFN32
MN SUFFIX
CASE 488AM
A
= Assembly Location
= Wafer Lot
WL
YY
WW
G
= Year
= Work Week
= Pb−Free Package
DA0
DA0
QA0
CML
0
CML
1
externally terminated, 50 W to V
.
CC
QA0
ENA0
Single−ended LVCMOS/LVTTL SEL inputs control the routing of
the signals through the crosspoint switch which makes this device
configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The
device is housed in a low profile 5 x 5 mm 32−pin QFN package.
SELA0
QA1
0
CML
1
DA1
DA1
QA1
CML
CML
ENA1
SELA1
QB0
Features
DB0
DB0
0
• Plug−in compatible to the MAX3840 and SY55859L
• Maximum Input Clock Frequency 2.7 GHz
• Maximum Input Data Frequency 3.2 Gb/s
• 225 ps Typical Propagation Delay
• 80 ps Typical Rise and Fall Times
• 7 ps Channel to Channel Skew
CML
QB0
1
ENB0
SELB0
QB1
0
CML
1
DB1
DB1
QB1
CML
ENB1
SELB1
• 430 mW Power Consumption
• < 0.5 ps RMS Jitter
Figure 1. Functional Block Diagram
• 7 ps Peak−to−Peak Data Dependent Jitter
• Power Saving Feature with Disabled Outputs
• Operating Range: V = 3.0 V to 3.6 V with V = 0 V
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
CC
EE
• CML Output Level (400 mV Peak−to−Peak Output), Differential
Output
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 5
NB4N840M/D
NB4N840M
Table 1. TRUTH TABLE
SELA0/SELB0
SELA1/SELB1
ENA0/ENA1 ENB0/ENB1
QA0/QB0
QA1/QB1
DA0/DB0
DA1/DB1
DA0/DB0
DA1/DB1
Function
1:2 Fanout
L
L
L
H
L
H
H
H
H
L
H
H
H
H
L
DA0/DB0
DA0/DB0
DA1/DB1
DA1/DB1
Quad Repeater
Crosspoint Switch
1:2 Fanout
H
H
X
H
X
Disable/Power Down Disable/Power Down No output (@ V
)
CC
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
ENB1
GND
DB1
V
CC
DB1
QA0
QA0
ENB0
NB4N840M
SELB0
DB0
V
CC
19 QA1
DB0
QA1
18
17
SELB1
V
CC
9
10
11
12
13
14
15
16
Figure 2. Pin Configuration (Top View)
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2
NB4N840M
Table 2. PIN DESCRIPTION
Pin
1
Name
ENB1
DB1
I/O
Description
LVTTL
Channel B1 Output Enable. LVTTL low input powers down B1 output stage.
Channel B1 Positive Signal Input
2
CML Input
CML Input
LVTTL
3
DB1
Channel B1 Negative Signal Input
4
ENB0
SELB0
DB0
Channel B0 Output Enable. LVTTL low input powers down B0 output stage.
Channel B0 Output Select. See Table 1.
5
LVTTL
6
CML Input
CML Input
LVTTL
Channel B0 Positive Signal Input
7
DB0
Channel B0 Negative Signal Input
8
SELB1
GND
Channel B1 Output Select. See Table 1.
9,24
−
Supply Ground. All GND pins must be externally connected to power supply to guarantee
proper operation.
10, 13, 16,
17, 20, 23
V
CC
−
Positive Supply. All V pins must be externally connected to power supply to guarantee
proper operation.
CC
11
12
14
15
18
19
21
22
25
26
27
28
29
30
31
32
−
QB0
QB0
QB1
QB1
QA1
QA1
QA0
QA0
SELA1
DA0
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
CML Output
LVTTL
Channel B0 Negative Output.
Channel B0 Positive Output.
Channel B1 Negative Output.
Channel B1 Positive Output.
Channel A1 Negative Output.
Channel A1 Positive Output.
Channel A0 Negative Output.
Channel A0 Positive Output.
Channel A1 Output Select, LVTTL Input. See Table 1.
Channel A0 Positive Signal Input.
CML Input
CML Input
LVTTL
DA0
Channel A0 Negative Signal Input.
Channel A0 Output Select, LVTTL Input. See Table 1.
Channel A0 Output Enable. LVTTL low input powers down A0 output stage.
Channel A1 Positive Signal Input.
SELA0
ENA0
DA1
LVTTL
CML Input
CML Input
LVTTL
DA1
Channel A1 Negative Signal Input.
Channel A1 Output Enable. LVTTL low input powers down A1 output stage.
ENA1
EP
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see case drawing)
must be attached to a heat−sinking conduit. The exposed pad must be soldered to the
circuit board GND for proper electrical and thermal operation.
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3
NB4N840M
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
> 2000 V
> 110 V
Machine Model
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
QFN−32
Level 1
UL 94 V−0 @ 0.125 in
380
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
GND = 0 V
Condition 2
Rating
Unit
V
V
V
V
3.8
3.8
3.8
CC
I
Positive Input
GND = 0 V
GND = V = V
V
I
CC
Differential Input Voltage
|D − D|
V
INPP
I
IN
Input Current Through Internal 50 W Resistor
Static
Surge
45
80
mA
mA
I
Output Current
Continuous
Surge
25
80
mA
mA
OUT
T
Operating Temperature Range
Storage Temperature Range
QFN−32
−40 to +85
°C
°C
A
T
stg
−65 to +150
q
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
2S2P (Note 3)
QFN−32
12
°C/W
°C
JC
T
sol
Wave Solder
Pb−Free <3 sec @ 260 C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NB4N840M
Table 5. DC CHARACTERISTICS, CLOCK INPUTS, CML OUTPUTS V = 3.0 V to 3.6 V, T = −40°C to +85°C
CC
A
Symbol
Characteristic
Min
Typ
130
800
Max
170
Unit
mA
mV
mV
mV
mV
I
Power Supply Current (All outputs enabled)
CC
Vout
CML Differential Output Swing (Note 4, Figures 5 and 12)
CML Output Common Mode Voltage (Loaded 50 W to V
640
1000
diff
V
CMR
V
− 200
)
CC
CC
(Note 6)
CML Single−Ended Input Voltage Range
Differential Input Voltage (V − V
V
− 800
V
+ 400
CC
CC
V
ID
)
ILD
300
1600
IHD
LVTTL CONTROL INPUT PINS
V
V
Input HIGH Voltage (LVTTL Inputs)
Input LOW Voltage (LVTTL Inputs)
Input HIGH Current (LVTTL Inputs)
Input LOW Current (LVTTL Inputs)
CML Single−Ended Input Resistance
Differential Output Resistance
2000
mV
mV
mA
mA
W
IH
IL
800
10
I
IH
I
IL
−10
−10
42.5
85
10
R
50
57.5
115
TIN
R
100
W
TOUT
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs require 50 W receiver termination resistors to V for proper operation (Figure 10).
CC
5. Input and output parameters vary 1:1 with V
.
CC
6. V
min varies 1:1 with V , V
max varies 1:1 with V
.
CMR
EE
CMR
CC
Table 6. AC CHARACTERISTICS V = 3.0 V to 3.6 V, V = 0 V (Note 7, Figure 9)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max Min Typ Max Min Typ Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude (@ V
(See Figure 3)
)
f
f
in
≤ 2 GHz 280
≤ 3 GHz 235
365
310
220
280
235
170
365
310
220
280
235
170
365
310
220
mV
OUTPP
INPPmin
in
in
f
≤ 3.5 GHz 170
f
Maximum Operating Data Rate
3.2
3.2
3.2
Gb/s
ps
DATA
t
t
,
Propagation Delay to Output Differential
PLH
PHL
D/D to Q/Q 140
225
340
140
225
340
140
225
340
t
Duty Cycle Skew (Note 8)
Within−Device Skew (Figure 4)
Device−to−Device Skew (Note 12)
5
5
20
25
25
85
5
5
20
25
25
85
5
5
20
25
25
85
ps
ps
SKEW
t
RMS Random Clock Jitter (Note 10)
Peak−to−Peak Data Dependent Jitter f = 2.5 Gb/s
(Note 11)
f
v 3.2 GHz
= 3.2 Gb/s
0.15
7
7
0.5
20
20
0.15
7
7
0.5
20
20
0.15
7
7
0.5
20
20
JITTER
in
in
f
in
Crosstalk−Induced RMS Jitter (Note 13)
0.5
0.5
0.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 9)
150
800
150
800
150
800
mV
t
r
t
f
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q, Q
80
135
80
135
80
135
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Measured by forcing V
(20% − 80%).
(MIN) from a 50% duty cycle clock source. All loading with an external R = 50 W to V . Input edge rates 40 ps
L CC
INPP
8. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
9. V (MAX) cannot exceed 800 mV. Input voltage swing is a single−ended measurement operating in differential mode.
INPP
10.Additive RMS jitter using 50% duty cycle clock input signal.
23
11. Additive peak−to−peak data dependent jitter using input data pattern with PRBS 2 −1 and K28.5, V
12.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13.Data taken on the same device under identical condition.
= 400 mV.
INPP
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5
NB4N840M
20
18
16
14
12
10
8
450
400
350
300
250
200
150
100
50
Channel B
Channel A
6
4
2
0
0
0.05 0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−40
25
85
INPUT CLOCK FREQUENCY (GHz)
TEMPERATURE (°C)
Figure 3. Output Voltage Amplitude (VOUTPP
vs. Input Clock Frequency (fIN) at Ambient
Temperature (Typ)
)
Figure 4. Within−Device Skew vs. Temperature
at VCC = 3.3 V
900
800
700
600
500
400
300
200
100
0
170
160
150
140
130
120
110
−40
25
85
−40
25
85
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 5. CML Differential Voltage vs.
Temperature
Figure 6. Supply Current vs. Temperature
(All 4 Outputs Enabled)
DDJ = 3 ps
DDJ = 4 ps
TIME (80.4 ps/div)
TIME (62.5 ps/div)
Figure 7. Typical Output Waveform at 2.488 Gb/s
with PRBS 223−1 (Input Signal DDJ = 12 ps)
Figure 8. Typical Output Waveform at 3.2 Gb/s
with K28.5 (Input Signal DDJ = 14 ps)
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NB4N840M
Dx
V
V
= V (D ) − V (D )
IH X IL X
INPP
Dx
Qx
= V (Q ) − V (Q )
OUTPP
OH
X
OL
X
Qx
t
PHL
t
PLH
Figure 9. AC Reference Measurement
V
CC
50 W
50 W
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8173/D)
V
CC
V
CC
50 W
50 W
50 W
50 W
Q
Q
X
X
D
D
X
X
16 mA
GND
Output
GND
GND
Input
Figure 11. CML Input and Output Structure
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7
NB4N840M
640 mV
MIN
Q
Q
X
X
320 mV
MIN
(Q − Q )
X
X
Q
Q
X
1000 mV
MAX
500 mV
MAX
X
(Q − Q )
X
X
Figure 12. CML Output Levels
ORDERING INFORMATION
Device
Package
Shipping
NB4N840MMNG
QFN32
(Pb−Free)
74 Units / Rail
NB4N840MMNR4G
NB4N840MMNTWG
QFN32
(Pb−Free)
1000 / Tape & Reel
1000 / Tape & Reel
QFN32
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NB4N840M
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE A
A
B
D
NOTES:
L
L
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
L1
LOCATION
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
A
MILLIMETERS
DIM
A
A1
A3
b
MIN
0.80
−−−
0.20 REF
0.18
MAX
1.00
0.05
0.15
C
0.15
C
EXPOSED Cu
MOLD CMPD
0.30
TOP VIEW
D
5.00 BSC
D2
E
E2
2.95
5.00 BSC
2.95
3.25
3.25
DETAIL B
(A3)
A1
0.10
C
C
e
0.50 BSC
DETAIL B
K
L
L1
0.20
0.30
−−−
−−−
0.50
0.15
ALTERNATE
CONSTRUCTION
0.08
SEATING
PLANE
C
NOTE 4
SIDE VIEW
RECOMMENDED
DETAIL A
32X L
SOLDERING FOOTPRINT*
K
D2
9
5.30
32X
0.63
17
8
3.35
E2
1
32
25
3.35 5.30
32X
b
e
M
M
0.10
C A B
e/2
NOTE 3
0.05
C
BOTTOM VIEW
0.50
PITCH
32X
0.30
DIMENSION: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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NB4N840M/D
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