NB6L14_07 [ONSEMI]
2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer; 2.5 V / 3.3 V 3.0 GHz差分1 ： 4 LVPECL扇出缓冲器
| 型号： | NB6L14_07 |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer |
| 文件： | 总10页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB6L14
2.5 V/3.3 Vꢀ3.0 GHz
Differential 1:4 LVPECL
Fanout Buffer
Multi- Level Inputs with Internal Termination
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MARKING
DIAGRAM*
Description
The NB6L14 is a 3.0 GHz differential 1:4 LVPECL clock or data
ꢀ
fanout buffer. The differential inputs incorporate internal 50
16
termination resistors that are accessed through the VT pin. This feature
allows the NB6L14 to accept various logic standards, such as
LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. The
VREF_AC reference output can be used to rebias capacitor-coupled
differential or single-ended input signals. The 1:4 fanout design was
optimized for low output skew applications.
1
NB6L
14
QFN-16
MN SUFFIX
CASE 485G
ALYWG
G
A
L
= Assembly Location
= Wafer Lot
= Year
The NB6L14 is a member of the ECLinPS MAX™ family of high
performance clock and data management products.
Y
W
G
= Work Week
= Pb-Free Package
Features
•ꢀInput Clock Frequency > 3.0 GHz
•ꢀInput Data Rate > 2.5 Gb/s
•ꢀ< 20 ps Within Device Output Skew
•ꢀ350 ps Typical Propagation Delay
•ꢀ150 ps Typical Rise and Fall Times
•ꢀDifferential LVPECL Outputs, 700 mV Amplitude, Typical
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Q0
Q0
•ꢀLVPECL Mode Operating Range: V = 2.375 V to 3.63 V with
CC
GND = 0 V
Q1
Q1
•ꢀInternal 50 ꢀ Input Termination Resistors Provided
•ꢀVREF_AC Reference Output Voltage
•ꢀ-40 °C to +85°C Ambient Operating Temperature
•ꢀAvailable in 3 mm x 3 mm 16 Pin QFN
•ꢀThese are Pb-Free Devices
IN
VT
IN
Q2
Q2
D
Q
EN
Q3
Q3
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
©ꢀ Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
NB6L14/D
May, 2007 - Rev. 1
NB6L14
Q0
Q0 Q0
16 15
V
GND
13
CC
/Q0
Exposed Pad (EP)
14
Q1
Q1
1
2
3
4
12
11
10
9
IN
/Q1
IN
VT
/IN
50
50
ꢀ
ꢀ
Q1
Q2
Q2
VT
VREF_AC
IN
Q2
/Q2
D
Q
EN
5
6
7
8
CLK
Q3
VREF_AC
Q3 Q3
V
EN
CC
/Q3
Figure 2. QFN-16 Pinout
(Top View)
Figure 3. Logic Diagram
Q0:Q3
Table 1. EN TRUTH TABLE
IN
IN
EN
Q0:Q3
0
1
x
1
0
x
1
1
0
0
1
0+
1
0
1+
+ = On next negative transition of the input signal (IN).
x = Don't care.
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
Q1
LVPECL Output
Non-inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to
–2.0 V.
V
CC
2
3
Q1
Q2
LVPECL Output
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to V
– 2.0 V.
CC
Non-inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to
– 2.0 V.
V
CC
4
5
Q2
Q3
LVPECL Output
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to V
– 2.0 V.
– 2.0 V.
CC
Non-inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to
– 2.0 V.
V
CC
6
7
8
Q3
LVPECL Output
Inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to V
CC
V
CC
-
Positive Supply Voltage
EN
LVTTL/LVCMOS
Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
9
IN
LVPECL, CML,
LVDS, HSTL
Inverted Differential Clock Input. Internal 50 ꢀ Resistor to Termination Pin, VT.
10
11
12
VREF_AC
Output Voltage Reference for capacitor-coupled inputs, only.
VT
IN
Internal 100 ꢀ center-tapped Termination Pin for IN and IN.
LVPECL, CML,
LVDS, HSTL
Non-inverted Differential Clock Input. Internal 50 ꢀ Resistor to Termination Pin, VT.
13
14
15
GND
-
Negative Supply Voltage
V
CC
-
Positive Supply Voltage
Q0
LVPECL Output
Noninverted Differential Output. Typically Terminated with 50 ꢀ Resistor to
–2.0 V.
V
CC
16
-
Q0
EP
LVPECL Output
-
Inverted Differential Output. Typically Terminated with 50 ꢀ Resistor to V –2.0 V.
CC
The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat-sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN inputs, then the device will be susceptible to self-oscillation.
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2
NB6L14
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 100 V
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
QFN-16
Level 1
UL 94 V-0 @ 0.125 in
167
Oxygen Index: 28 to 34
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
GND = 0 V
Condition 2
Rating
4.0
Unit
V
V
CC
Io
V
I
Positive Input/Output
Input Current
GND = 0 V
-0.5 V v V v V + 0.5 V
4.0
V
Io
CC
"50
mA
IN
Source or Sink Current (IN/IN)
I
I
Source or Sink Current on VT Pin
Output Current
"2.0
mA
VREF_AC
Continuous
Surge
50
100
mA
mA
OUT
T
Operating Temperature Range
Storage Temperature Range
-40 to +85
°C
°C
A
T
stg
-65 to +150
ꢁ
Thermal Resistance
(Junction-to-Ambient) (Note 3)
0 lfpm
500 lfpm
QFN-16
QFN-16
42
35
°C/W
°C/W
JA
ꢁ
Thermal Resistance (Junction-to-Case) (Note 3)
Wave Solder Pb-Free
QFN-16
4
°C/W
°C
JC
T
sol
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB6L14
Table 5. DC CHARACTERISTICS, Multi-Level Inputs, LVPECL Outputs
= 2.375 V to 3.63 V, GND = 0 V, T = -40°C to +85°C
A
V
CC
Symbol
Characteristic
Min
Typ
Max
Unit
I
Power Supply Current (Inputs and Outputs Open)
35
47
65
mA
CC
LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS
V
Output HIGH Voltage (Notes 4 and 5) (Q, Q)
V
- 1145
V
V
- 1020
V - 895
CC
mV
mV
OH
CC
CC
V
CC
V
CC
= 3.3 V
= 2.5 V
2155
1355
2280
1480
2405
1605
V
OL
Output LOW Voltage (Notes 4 and 5) (Q, Q)
V
CC
- 1945
- 1875
V
CC
- 1695
CC
V
CC
V
CC
= 3.3 V
= 2.5 V
1355
555
1475
675
1605
805
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (See Figures 5 and 6)
V
V
V
V
Input Threshold Reference Voltage Range (Note 6)
Single-Ended Input High Voltage
1100
V
- 100
mV
mV
mV
mV
th
CC
V
+ 100
V
CC
IH
th
Single-Ended Input LOW Voltage
V
EE
V - 100
th
IL
Single-Ended Input Voltage Amplitude (V - V )
IH IL
200
V
CC
- GND
ISE
REFAC
V
V
Output Reference Voltage (V w 2.5 V)
CC
V
CC
- 1.525
V
CC
- 1.425
V
CC
- 1.325
mV
REFAC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (See Figures 7 and 8) (Note 7)
V
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
GND
950
V
mV
mV
mV
IHD
ILD
CC
V
- 100
IHD
Input Common Mode Range (Differential Configuration)
(Note 8)
V
– 50
CMR
CC
V
ID
Differential Input Voltage (IN-IN) (V
V
IHD- ILD
)
100
V - GND
CC
mV
I
Input HIGH Current
(VT Open)
IN/IN
IN/IN
-150
+150
ꢂ
A
IH
I
IL
Input LOW Current
(VT Open)
-150
+150
ꢂ
A
LVTTL/LVCMOS INPUT DC ELECTRICAL CHARACTERISTICS
V
V
Input HIGH Voltage
Input LOW Voltage
2.0
GND
-10
V
V
V
IH
IL
CC
0.8
50
0
I
Input HIGH Current, V = V = 3.63 V
CC IN
ꢂ A
ꢂ A
IH
IL
I
Input LOW Current, V = 3.63 V, V = 0 V
CC IN
-150
TERMINATION RESISTORS
R
R
Internal Input Termination Resistor (IN to VT)
Differential Input Resistance (IN to IN)
40
80
50
60
ꢀ
ꢀ
TIN
100
120
DIFF_IN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs loaded with 50 ꢀ to V - 2.0 V for proper operation.
.
CC
5. Input and output parameters vary 1:1 with V
CC
6. V is applied to the complementary input when operating in single-ended mode.
th
7. V , V , V and V
8. V
parameters must be complied with simultaneously.
max varies 1:1 with V . The V
IHD ILD ID
CMR
min varies 1:1 with GND, V
range is referenced to the most positive side of the differential
CMR
input signal.
CMR
CC
CMR
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NB6L14
Table 6. AC CHARACTERISTICS V = 2.375 V to 3.63 V, GND = 0 V, T = -40°C to +85°C (Note 9)
CC
A
Symbol
Characteristic
Min
Typ
Max
Unit
V
Output Voltage Amplitude (@ V
) (Note 10)
INPPmin
mV
OUTPP
f
≤ 1.25 GHz
in
550
380
250
700
500
320
IN
1.25 GHz ≤ f ≤ 2.0 GHz
2.0 GHz ≤ f ≤ 3.0 GHz
in
f
Maximum Operating Data Rate
Propagation Delay
2.5
Gb/s
ps
DATA
t
t
t
t
IN to Q
EN to IN, IN
EN to IN, IN
350
PD
S
Set-Up Time (Note 11)
Hold Time (Note 11)
300
300
ps
ps
H
Within-Device Skew (Note 12)
Device to Device Skew (Note 13)
5.0
20
ps
SKEW
150
t
RMS Random Jitter (Note 14)
ps
JITTER
f
= 2.5 GHz
= 2.5 Gb/s
1.0
IN
Peak-to-Peak Data Dependent Jitter
(Note 15)
f
14
DATA
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
100
70
V
CC
- GND
mV
ps
INPP
t ,t
r f
Output Rise/Fall Times @ Full Output Swing
(20%-80%)
150
200
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing V
INPP
rates 40 ps (20%-80%).
10.Input and output voltage swing is a single-ended measurement operating in differential mode.
(min) from a 50% duty cycle clock source. All loading with an external R = 50 ꢀ to V
L
– 2.0 V. Input edge
CC
11. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous
applications, set-up and hold times do not apply.
12.Within device skew is measured between two different outputs under identical power supply, temperature and input conditions.
13.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
14.Additive RMS jitter with 50% duty cycle clock signal.
^23
15.Additive peak-to-peak data dependent jitter with input NRZ data at PRBS 2 -1 and K28.5 at 2.5Gb/s.
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5
NB6L14
INn
50
50
ꢀ
ꢀ
VTn
INn
Figure 4. Input Structure
V
CC
V
V
IN
IHmax
V
thmax
V
IH
ILmax
V
th
IL
V
IH
V
th
V
IL
V
th
V
IN
V
V
IHmin
V
thmin
ILmin
V
th
GND
Figure 6. Vth Diagram
Figure 5. Differential Input Driven
Single-Ended
V
CC
V
V
V
IH(MAX)
IL
D
D
IH
V
V
= V
- V
IHD ILD
CMR
ID
V
IL
V
V
IH
Figure 7. Differential Inputs
Driven Differentially
IL(MIN)
GND
Figure 8. VCMR Diagram
IN
V
V
= V (IN) - V (IN)
IH IL
INPP
IN
Q
= V (Q) - V (Q)
OH OL
OUTPP
Q
t
PD
t
PD
Figure 9. AC Reference Measurement
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6
NB6L14
V
CC
V
CC
V
CC
V
CC
NB6L14
NB6L14
Zo = 50
ꢀ
Zo = 50 ꢀ
IN
IN
IN
IN
50
50
ꢀ
ꢀ
50
50
ꢀ
ꢀ
LVPECL
Driver
LVDS
Driver
VT = V
CC
Zo = 50
- 2 V
VT = Open
Zo = 50
ꢀ
ꢀ
GND
GND
GND
GND
Figure 10. LVPECL Interface
Figure 11. LVDS Interface
V
CC
V
CC
NB6L14
Zo = 50
ꢀ
IN
IN
50
50
ꢀ
ꢀ
CML
Driver
VT = V
ꢀ
CC
Zo = 50
GND
GND
Figure 12. Standard 50 W Load CML Interface
V
CC
V
CC
V
CC
V
CC
NB6L14
NB6L14
Zo = 50
ꢀ
Zo = 50
VT = V
ꢀ
IN
IN
IN
50
50
ꢀ
ꢀ
50
50
ꢀ
ꢀ
Differential
Driver
Single-Ended
Driver
VT = V
REF
Zo = 50
_AC*
_AC*
REF
ꢀ
IN (Open)
GND
GND
GND
GND
Figure 13. Capacitor-Coupled
Differential Interface
Figure 14. Capacitor-Coupled
Single-Ended Interface
(VT Connected to VREFAC)
(VT Connected to VREFAC
)
*V
REFAC
bypassed to ground with a 0.01 ꢂ F capacitor
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7
NB6L14
800
700
600
500
400
300
200
100
0
0
1
2
3
f , CLOCK OUTPUT FREQUENCY (GHz)
out
Figure 15. Output Voltage Amplitude (VOUTPP) versus Output
Frequency at Ambient Temperature (Typical)
EN
V /2
CC
V /2
CC
t
S
t
H
/IN
IN
V
INPP
t
pd
/Q
Q
V
OUTPP
Figure 16. EN Timing Diagram
Z = 50
o
ꢀ
ꢀ
Q
Q
D
D
Receiver
Device
Driver
Device
Z = 50
o
50
ꢀ
50 ꢀ
V
TT
= V
V
TT
- 2.0 V
CC
Figure 17. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
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8
NB6L14
ORDERING INFORMATION
Device
†
Package
Shipping
NB6L14MNG
QFN-16, 3x3 mm
(Pb-Free)
123 Units / Rail
NB6L14MNR2G
QFN-16, 3x3 mm
(Pb-Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB6L14
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE C
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN 1
LOCATION
E
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
0.15
C
TOP VIEW
MILLIMETERS
0.15
C
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
(A3)
0.10
0.08
C
C
A3
b
0.20 REF
0.18
0.30
D
D2 1.65
E 3.00 BSC
E2 1.65
3.00 BSC
A
1.85
SEATING
PLANE
16 X
1.85
SIDE VIEW
D2
A1
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
C
SOLDERING FOOTPRINT*
e
L
16X
EXPOSED PAD
5
8
NOTE 5
3.25
0.128
0.30
4
9
0.575
0.022
EXPOSED PAD
E2
e
0.012
K
16X
12
1
16
13
16X b
1.50
0.059
3.25
0.128
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
0.30
0.012
0.50
0.02
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
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ꢁPhone: 81-3-5773-3850
For additional information, please contact your
local Sales Representative.
NB6L14/D
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