NB7L572MNR4G [ONSEMI]
2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator; 2.5V / 3.3V的差分4 ： 1多路复用器输入至1 ： 2的LVPECL时钟/数据扇出/翻译
| 型号： | NB7L572MNR4G |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout / Translator |
| 文件： | 总9页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7L572
2.5V / 3.3V Differential 4:1
Mux Input to 1:2 LVPECL
Clock/Data Fanout /
Translator
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MARKING
Multi−Level Inputs w/ Internal Termination
The NB7L572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock/Data fanout buffer. The
INx/INx inputs includes internal 50 W termination resistors and will
accept differential LVPECL, CML, or LVDS logic levels. The
NB7L572 incorporates a pair of Select pins that will choose one of
four differential inputs and will produce two identical LVPECL output
copies of Clock or Data operating up to 7 GHz or 10 Gb/s,
respectively. As such, NB7L572 is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The NB7L572 INx/INx inputs, outputs and core logic are powered
by a 2.5 V $5% V or 3.3 V $10% power supply. The two differential
LVPECL outputs will swing 750 mV when externally terminated with
DIAGRAM*
32
1
32
1
NB7L
572
AWLYYWWG
QFN32
MN SUFFIX
CASE 488AM
A
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
a 50 W resistor to V – 2 V, and are optimized for low skew and
CC
*For additional marking information, refer to
Application Note AND8002/D.
minimal jitter.
The NB7L572 is offered in a low profile 5x5 mm 32-pin QFN
Pb-free package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB7L572 is a member of the GigaComm™ family of high
performance clock products.
IN0
50W
T0
50W
V
IN0
V
V
V
V
REFAC0
Features
0
IN1
50W
• Input Data Rate > 10.7 Gb/s Typical
• Data Dependent Jitter < 15 ps
• Maximum Input Clock Frequency > 7 GHz Typical
• Random Clock Jitter < 0.8 ps RMS
V
T1
Q0
Q0
50W
IN1
REFAC1
IN2
1
2
Q1
Q1
50W
V
T2
50W
• Low Skew 1:2 LVPECL Outputs, < 15 ps max
• 4:1 Multi−Level Mux Inputs, Accepts LVPECL, CML LVDS
• 150 ps Typical Propagation Delay
IN2
3
REFAC2
IN3
50W
T3
V
• 45 ps Typical Rise and Fall Times
50W
IN3
• Differential LVPECL Outputs, 750 mV Peak-to-Peak, Typical
REFAC3
SEL0
SEL1
• Operating Range: V = 2.375 V to 3.6 V
CC
• Internal 50 W Input Termination Resistors
• V
Reference Output
ORDERING INFORMATION
REFAC
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
December, 2008 − Rev. 1
NB7L572/D
NB7L572
Exposed Pad (EP)
GND
24
23
22
21
20
IN0
VT0
1
2
3
4
5
6
7
8
VCC
Q1
VREFAC0
Q1
IN0
IN1
NB7L572
VCC
VT1
19 NC
VREFAC1
IN1
18 SEL1
VCC
17
Figure 1. Pinout Configuration (Top View)
Table 1. INPUT SELECT FUNCTION TABLE
SEL1*
SEL0*
Clock / Data Input Selected
0
0
1
1
0
1
0
1
IN0 Input Selected
IN1 Input Selected
IN2 Input Selected
IN3 Input Selected
*Defaults HIGH when left open.
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2
NB7L572
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1, 4
5, 8
25, 28
29, 32
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
LVPECL, CML,
LVDS Input
Non−inverted, Inverted, Differential Clock or Data Inputs.
2, 6
26, 30
VT0, VT1
VT2, VT3
Internal 100 W Center−tapped Termination Pin for INx / INx
15
18
SEL0
SEL1
LVTTL/LVCMOS
Input
Input Select pins, default HIGH when left open through a 28k−W pull−up resistor. Input
logic threshold is V /2. See Select Function, Table 1.
CC
14, 19
NC
−
−
No Connect
10, 13, 16
17, 20, 23
VCC
Positive Supply Voltage. All V pins must be connected to the positive power supply
for correct DC and AC operation.
CC
11, 12
21, 22
Q0, Q0
Q1, Q1
LVPECL Output
Inverted, Non−inverted Differential Outputs.
9, 24
GND
Negative Supply Voltage, connected to Ground
3
7
27
31
VREFAC0
VREFAC1
VREFAC2
VREFAC3
−
Output Voltage Reference for Capacitor−Coupled Inputs
−
EP
−
The Exposed Pad (EP) on the QFN−32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left
open, and if no signal is applied on INx / INx input, then the device will be susceptible to self−oscillation.
2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
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3
NB7L572
Table 3. ATTRIBUTES
Characteristic
Value
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 150 V
Input Pullup Resistor (R
)
28 kW
Level 1
PU
Moisture Sensitivity (Note 3)
QFN32
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
UL 94 V−0 @ 0.125 in
205
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
−0.5 to +4.0
Unit
V
V
V
V
Positive Power Supply
Positive Input Voltage
CC
−0.5 to V +0.5
V
IN
CC
Differential Input Voltage |IN – IN|
LVPECL Output Current
1.89
V
INPP
I
Continuous
Surge
50
100
mA
mA
out
I
Input Current Through RT (50 W Resistor)
Operating Temperature Range
$40
−40 to +85
mA
°C
IN
T
A
T
stg
Storage Temperature Range
−65 to +150
°C
q
Thermal Resistance (Junction−to−Ambient) (Note 4)
0 lfpm
500 lfpm
QFN−32
QFN−32
31
27
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case) (Note 4)
QFN−32
12
°C/W
°C
JC
T
sol
Wave Solder
v 20 sec
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NB7L572
Table 5. DC CHARACTERISTICS POSITIVE LVPECL OUTPUT V = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C
CC
(Note 6)
Symbol
Characteristic
Min
Typ
Max
Unit
POWER SUPPLY
V
CC
Power Supply Voltage
V
CC
= 2.5V
= 3.3 V
2.375
3.0
2.5
3.3
2.625
3.6
V
CC
V
I
Power Supply Current for V (Inputs and Outputs Open)
90
110
mA
CC
CC
LVPECL OUTPUTS
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
V
– 1145
1355
2155
V
– 900
1600
2400
V – 825
CC
1675
2475
mV
mV
OH
OL
CC
CC
V
V
= 2.5 V
= 3.3 V
CC
CC
V
V
CC
– 2000
500
1300
V
CC
– 1700
800
1600
V
CC
– 1500
1000
1800
V
CC
V
CC
= 2.5 V
= 3.3 V
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 4 & 6) (Note 7)
V
V
V
V
Single−Ended Input HIGH Voltage
V
th
+ 100
V
CC
mV
mV
mV
mV
IH
IL
Single−Ended Input LOW Voltage
GND
1100
200
V
– 100
– 100
th
Input Threshold Reference Voltage Range (Note 8)
V
CC
th
Single−Ended Input Voltage (V – V )
1200
ISE
IH
IL
VREFAC
V
Output Reference Voltage (100 mA Load)
V
CC
– 1500
V
CC
– 1200
V – 1000
CC
mV
REF−AC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 9)
V
V
V
V
Differential Input HIGH Voltage (IN, IN)
Differential Input LOW Voltage (IN, IN)
1200
V
mV
mV
mV
mV
IHD
ILD
ID
CC
0
V
– 100
IHD
Differential Input Voltage (IN, IN) (V
– V
)
100
1200
V – 50
CC
IHD
ILD
Input Common Mode Range (Differential Configuration, Note 10)
(Figure 8)
1150
CMR
I
I
Input HIGH Current IN/IN (VT IN/VT IN Open)
Input LOW Current IN/IN (VT IN/VT IN Open)
−150
−150
150
150
mA
mA
IH
IL
CONTROL INPUT (SELx Pin)
V
V
Input HIGH Voltage for Control Pin
Input LOW Voltage for Control Pin
Input HIGH Current
2.0
V
V
V
IH
IL
CC
GND
0.8
40
0
I
IH
I
IL
mA
mA
Input LOW Current
−215
TERMINATION RESISTORS
Internal Input Termination Resistor (Measured from INx to VTx)
R
TIN
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and Output parameters vary 1:1 with V
.
CC
6. LVPECL outputs loaded with 50 W to V − 2V for proper operation.
CC
7. Vth, V , V and V parameters must be complied with simultaneously.
IH
IL,,
ISE
8. Vth is applied to the complementary input when operating in single−ended mode.
9. V , V and V parameters must be complied with simultaneously.
V
IHD
CMR
ILD, ID
CMR
10.V
min varies 1:1 with GND, V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
CMR
CC
CMR
input signal.
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5
NB7L572
Table 6. AC CHARACTERISTICS V = 2.375 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 11)
CC
Symbol
Characteristic
Min
7
Typ
8
Max
Unit
GHz
Gbps
mV
f
f
Maximum Input Clock Frequency V
w 400 mV
MAX
OUT
Maximum Operating Data Rate NRZ, (PRBS23)
10
11
DATAMAX
V
Output Voltage Amplitude (@ V
(Note 12)
) (Figure 2 & 9)
f
in
f
in
≤ 5 GHz
≤ 7 GHz
550
400
750
500
OUTPP
INPPmin
t
t
,
Propagation Delay to Differential Outputs
Measured at Differential Cross−Point
@ 1 GHz INx/INx to Qx/Qx (Figure 9)
@ 50 MHz SELx to Qx (Figure 10)
125
300
150
175
1000
ps
PLH
PHL
t
t
Differential Propagation Delay Temperature Coefficient
115
0
fs/°C
PD Tempco
skew
Output – Output skew (within device) (Note 13)
Device – Device skew (tpd max – tpd min)
10
50
ps
t
t
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
45
50
55
%
DC
Additive Random Clock Jitter, RJ(RMS) (Note 14)
Data Dependent Jitter, DDJ (Note 15)
f
f
v 7.0 GHz
v 10 Gbps
0.5
6
0.8
15
ps rms
ps pk−pk
JITTER
in
in
V
Input Voltage Swing (Differential Configuration) (Note 16)
100
25
1200
65
mV
ps
INPP
t , t
r,
Output Rise/Fall Times @ 1 GHz; (20% − 80%), V = 800 mV Q, Q
45
f
IN
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 100 mVpk−pk source, 50% duty cycle clock source. All output loading with external 50 W to V − 2 V. Input edge
CC
rates 40 ps (20% − 80%).
12.Output voltage swing is a single−ended measurement operating in differential mode.
13.Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from cross−point of the inputs to the cross−point of the outputs.
14.Additive RMS jitter with 50% duty cycle clock signal.
15.Additive Peak−to−Peak data dependent jitter with input NRZ data at K28.5.
16.Input voltage swing is a single−ended measurement operating in differential mode.
800
V
CC
750
700
INx
50 W
50 W
V
Tx
650
600
INx
0
1
2
3
4
5
6
7
8
fin, CLOCK INPUT FREQUENCY (GHz)
Figure 3. Input Structure
Figure 2. CLOCK Output Voltage Amplitude
(VOUTPP) / RMS Jitter vs. Input Frequency (fin) at
Ambient Temperature (typical)
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6
NB7L572
IN
V
IH
V
IN
IN
th
IL
V
IN
V
th
Figure 4. Differential Input Driven
Figure 5. Differential Inputs
Driven Differentially
Single−Ended
V
CC
thmax
V
V
IHmax
V
ILmax
V
ID
= |V
− V
IHD(IN) ILD(IN)|
V
IH
V
th
V
IL
IN
IN
V
th
V
IHD
IN
V
ILD
V
V
IHmin
V
thmin
ILmin
GND
Figure 6. Vth Diagram
Figure 7. Differential Inputs Driven Differentially
V
CC
V
V
IHDmax
ILDmax
IHDtyp
V
CMmax
IN
V
V
= V (IN) − V (IN)
IH IL
INPP
IN
Q
V
IN
IN
V
CMR
V
ID
= V
− V
IHD ILD
V
ILDtyp
= V (Q) − V (Q)
OUTPP
OH
OL
Q
V
V
IHDmin
V
CMmin
t
PHL
ILDmin
t
PLH
GND
Figure 8. VCMR Diagram
Figure 9. AC Reference Measurement
V
CC
/2
V
CC
/2
SELx
t
t
PLH
PHL
Qx
Qx
Figure 10. SELx to Qx Timing Diagram
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7
NB7L572
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 11. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
V
CC
V
CC
V
CC
V
CC
NB7L572
NB7L572
D
D
D
D
Z
= 50 W
Z
Z
= 50 W
O
O
50 W
50 W
50 W
50 W
LVPECL
Driver
LVDS
Driver
VT = V − 2 V
V = Open
T
CC
Z
O
= 50 W
= 50 W
O
V
EE
V
EE
V
EE
V
EE
Figure 12. LVPECL Interface
Figure 13. LVDS Interface
V
CC
V
CC
V
CC
V
CC
NB7L572
NB7L572
D
D
Z
O
= 50 W
Z
O
= 50 W
50 W
50 W
CML
Driver
50 W
50 W
Differential
Driver
V = V
T
VT = V
*
CC
REFAC
Z
O
= 50 W
Z
O
= 50 W
D
D
V
EE
V
EE
V
EE
V
EE
Figure 15. Capacitor−Coupled
Figure 14. Standard 50 W Load CML Interface
Differential Interface
(VT Connected to VREFAC
)
*V
REFAC
bypassed to ground with a 0.01 mF capacitor
ORDERING INFORMATION
Device
†
Package
Shipping
NB7L572MNG
QFN32
(Pb−Free)
79 Units / Rail
NB7L572MNR4G
QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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8
NB7L572
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM−01
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
SOLDERING FOOTPRINT*
L
5.30
EXPOSED PAD
32 X
K
16
9
32 X
3.20
17
8
32 X
0.63
E2
1
24
3.20 5.30
25
32
32 X
b
e
0.10
0.05
C
A
B
32 X
C
28 X
0.50 PITCH
0.28
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Email: orderlit@onsemi.com
For additional information, please contact your local
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NB7L572/D
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