NB7L86A [ONSEMI]
2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select;
| 型号： | NB7L86A |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select 栅 |
| 文件： | 总18页 (文件大小：395K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V SiGe Differential
Smart Gate with Output
Level Select
NB7L86A
The NB7L86A is a multi−function differential Logic Gate which
can be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1
MUX. This device is part of the GigaCommt family of high
performance Silicon Germanium products. The device is housed in
a 3 x 3 mm 16 pin QFN package.
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Differential inputs incorporate internal 50 W termination resistors
and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The Output Level Select (OLS)
input is used to program the peak−to−peak output amplitude between 0
and 800 mV in five discrete steps.
1
QFN16 3x3, 0.5P
CASE 485G
The NB7L86A employs input default circuitry so that under open
input condition (Dx, Dx, VTDx, VTDx, VTSEL) the Outputs of the
device remains stable.
MARKING DIAGRAM
1
NB7L
86A
Features
• Maximum Input Clock Frequency > 8 GHz Typical
• Maximum Input Data Rate > 8 Gb/s Typical
• 165 ps Typical Propagation Delay
• 40 ps Typical Rise and Fall Times
• Selectable Swing PECL Output with Operating Range:
ALYWG
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
V
CC
= 2.375 V to 3.465 V with V = 0 V
EE
• Selectable Swing NECL Output with NECL Inputs with Operating
Range: V = 0 V with V = −2.375 V to −3.465 V
CC
EE
(Note: Microdot may be in either location)
• Selectable Output Level
(0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak−to−Peak Output)
• 50 W Internal Input Termination Resistors
• This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
December, 2019 − Rev. 0
NB7L86A/D
NB7L86A
VTD0
16
D0
15
D0
14
VTD0
13
1
2
3
4
12
11
10
9
V
EE
OLS
SEL
Q
Q
Exposed
Pad EP
SEL
VTSEL
V
CC
7
8
6
5
VTD1
D1
D1
VTD1
Figure 1. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Description
1
2
OLS (Note 3)
SEL
Input
Input for OLS (Output Level Select) Pin. Refer Table 2
Input: LVCMOS/LVTTL,
ECL/CML/LVDS
Input for Select Logic Pin, Single Ended or Inverted Differential
3
4
5
6
7
SEL
VTSEL (Note 1)
VTD1 (Note 1)
D1
Input for Select Logic Pin, Single Ended or non−Inverted Differential
Input: LVCMOS/LVTTL,
ECL/CML/LVDS
Pin with a common internal 50 W termination from SEL/SEL Pins. Refer
Table 7 for usage with different Interface options
Pin with an internal 50 W termination from D1 Pin. Refer Table 7 for
usage with different Interface options
Input: LVCMOS/LVTTL,
ECL/CML/LVDS
Input Pin, Non−inverted Differential or Single Ended with internal 75 kW
connected to V
EE
D1
Input: LVCMOS/LVTTL,
ECL/CML/LVDS
Input Pin, Inverted Differential or Single Ended with internal 75 kW
connected to V and 36.5 kW connected to V
EE
CC
8
VTD1 (Note 1)
Pin with an internal 50 W termination from D1 Pin. Refer Table 7 for
usage with different Interface options
9
V
CC
(Note 2)
Q
Positive Supply Voltage
10
Output: Reduced Swing ECL Output Pin, non−inverted Differential Output with typical 50 W termination
to V = V − 2 V
TT
CC
11
Q
Output: Reduced Swing ECL Output Pin, inverted Differential Output with typical 50 W termination to
= V − 2 V
V
TT
CC
12
13
V
(Note 2)
Negative Supply Voltage
EE
VTD0 (Note 1)
Pin with an internal 50 W termination from D0 Pin. Refer Table 7 for
usage with different Interface options
14
15
16
D0
Input: LVCMOS/LVTTL,
ECL/CML/LVDS
Input Pin, Inverted Differential or Single Ended with internal 75 kW
connected to V and 36.5 kW connected to V
EE
CC
D0
Input: LVCMOS/LVTTL,
ECL/CML/LVDS
Input Pin, Non−inverted Differential or Single Ended with internal 75 kW
connected to V
EE
VTD0 (Note 1)
EP
Pin with an internal 50 W termination from D0 Pin. Refer Table 7 for
usage with different Interface options
Exposed Pad (EP) is thermally connected to the die for improved heat
transfer out of the package. The exposed pad can be connected
electrically to V on the PCB board
EE
1. In the differential configuration when the input termination pins (VTD0/1, VTD0/1, VTSEL) are connected to a common termination voltage,
or left open, and if no signal is applied then the device will be susceptible to self−oscillation.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation.
CC
EE
3. When an output level of 400 mV is desired and V − V > 3.0 V, 2 kW resistor should be connected from OLS pin to V .
CC
EE
EE
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2
NB7L86A
Table 2. OUTPUT LEVEL SELECT OLS
OLS
Q/Q VPP
800 mV
200 mV
600 mV
0 mV
OLS Sensitivity
OLS − 75 mV
OLS 150 mV
OLS 100 mV
OLS 75 mV
OLS 100 mV
N/A
V
CC
V
V
V
− 0.4 V
− 0.8 V
− 1.2 V
(Note 4)
Float
CC
CC
CC
V
EE
400 mV
600 mV
4. When an output level of 400 mV is desired and V − V > 3.0 V, 2 kW resistor should be connected from OLS to to V .
EE
CC
EE
50 W
VTD0
D0
R
1
R
2
D0
VTD0
Q
Q
R
1
50 W
50 W
VTD1
D1
R
1
V
V
R
CC
2
50 W 50 W
D1
EE
R
1
VTD1
50 W
VTSEL
SEL
SEL
Figure 2. Logic Diagram
50 W
VTD0
D0
D0
VT or V
BB
V
CC
Table 3. AND/NAND TRUTH TABLE (Note 5)
a
D1
0
b
SEL
0
a * b
VTD0
Q
Q
50 W
50 W
D0
0
Q
0
0
0
1
VTD1
0
0
1
D1
D1
0
1
0
0
1
1
a
5. D0, D1, SEL are inverse of D0, D1, SEL unless specified
otherwise.
50 W 50 W
VTD1
50 W
VTSEL
SEL
SEL
b
Figure 3. Configuration for AND/NAND Function
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3
NB7L86A
50 W
VTD0
D0
D0
a
Table 4. OR/NOR TRUTH TABLE (*)
a
D0
0
b
SEL
0
a or b
D1
1
Q
0
1
1
1
VTD0
VTD1
Q
Q
50 W
50 W
0
1
1
1
1
0
D1
D1
V
CC
1
1
1
*D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise.
VT or V
BB
50 W 50 W
VTD1
50 W
VTSEL
b
SEL
SEL
Figure 4. Configuration for OR/NOR Function
50 W
VTD0
D0
D0
a
Table 5. XOR/XNOR TRUTH TABLE (*)
α
β
α XOR β
Q
Q
VTD0
VTD1
D0
0
D1
1
SEL
Q
0
1
1
0
50 W
50 W
0
1
0
1
0
1
D1
D1
1
0
1
0
50 W 50 W
*D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise.
VTD1
50 W
VTSEL
b
SEL
SEL
Figure 5. Configuration for XOR/XNOR Function
50 W
VTD0
D0
Table 6. 2:1 MUX TRUTH TABLE (*)
D0
SEL
1
Q
Q
Q
VTD0
50 W
50 W
D1
D0
VTD1
D1
0
*D0, D1, SEL are inverse of D0, D1, SEL unless specified otherwise.
D1
50 W 50 W
VTD1
50 W
VTSEL
SEL
SEL
Figure 6. Configuration for 2:1 MUX Function
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4
NB7L86A
Table 7. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
Connect VTD0, VTD0, VTSEL, VTD1, VTD1 TO V
CML
LVDS
CC
Connect VTD0, VTD0, VTD1, and VTD1 together. Leave VTSEL open
AC−COUPLED
Bias VTD0, VTD0, VTSEL, VTD1, VTD1 and VTSEL inputs within the Common Mode range
(VIHCMR)
RSECL, PECL, NECL
LVTTL, LVCMOS
Standard ECL termination techniques
An external voltage should be applied to the unused complementary differential input.
Nominal voltage of 1.5 V for LVTTL and V /2 for LVCMOS inputs
CC
Table 8. ATTRIBUTES
Characteristics
Value
75 kW
Internal Input Pulldown Resistors (R )
1
Internal Input Pullup Resistor (R )
37.5 kW
2
ESD Protection:
Human Body Model
Charged Device Model
Machine Model
≥ 4 kV
≥ 2 kV
≥ 200 V
Moisture Sensitivity (Note 6), Pb−Free
Level 1
Flammability Rating, Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
6. For additional information, see Application Note AND8003/D.
Table 9. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
Condition 2
Rating
Unit
V
CC
V
= 0 V
3.6
V
EE
CC
V
EE
Negative Power Supply
Positive Input
V
= 0 V
= 0 V
−3.6
V
V
V
I
V
VI ≤ V
3.6
EE
CC
CC
Negative Input
V
= 0 V
VI ≥ V
−3.6
V
V
EE
Differential Input Voltage
|Dn − Dn|, |SEL − SEL|
V
V
− V ≥ 2.8 V
2.8
CC
EE
V
INPP
− V ≤ 2.8 V
|V − V
|
CC
EE
CC
EE
Static
45
mA
I
IN
Input Current through RT (50 W Resistor)
Surge
Continuous
Surge
80
25
50
mA
mA
mA
I
Output Current
OUT
°C
°C
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
A
Tstg
−65 to +150
0 lfpm
41.6
35.2
4
°C/W
°C/W
°C/W
°C
Thermal Resistance (Junction−to−Ambient)
qJA
(Note 7)
500 lfpm
2S2P (Note 7)
< 3 sec @ 260°C
qJC
Thermal Resistance (Junction−to−Case)
Tsol
Wave Solder
(Pb−Free)
265
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
7. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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5
NB7L86A
°
Table 10. DC CHARACTERISTICS, INPUT WITH LVPECL OUTPUT: V = 2.5 V; V = 0 V, T = −40 C to +85°C (Note 8)
CC
EE
A
−405C
255C
855C
Symbol
POWER SUPPLY CURRENT
Negative Power Supply Current
LVPECL OUTPUTS (Note 9)
Min
23
Typ
Max
39
Min
Typ
Max
Min
Typ
Max
39
Characteristic
Unit
I
EE
30
23
30
39
23
30
mA
V
Output HIGH Voltage
Output LOW Voltage
1460
1510
1570
1490
1540
1600
1515
1565
1625
mV
mV
OH
V
OL
(OLS = V
)
555
705
1295
895
855
595
1270
810
745
1330
930
895
625
1295
840
775
1355
960
925
CC
(OLS = V − 0.4 V) 1235
1385
1015
1585
1215
1420
1050
1620
1250
1445
1080
1640
1275
CC
(OLS = V − 0.8 V, OLS = FLOAT) 775
CC
(OLS = V − 1.2 V) 1455
1505
1095
1490
1040
1540
1130
1510
1065
1560
1155
CC
(OLS = V
)
)
1005
670
EE
V
mV
Output Voltage Amplitude
OUTPP
(OLS = V
800
215
615
5
660
120
505
0
795
210
610
0
655
120
500
0
790
210
605
5
CC
(OLS = V − 0.4 V) 125
CC
(OLS = V − 0.8 V, OLS = FLOAT) 510
CC
(OLS = V − 1.2 V)
0
CC
(OLS = V
)
325
415
320
410
320
410
EE
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE ENDED (Figure 11 & 13) (Note 10)
V
Input HIGH Voltage (Single−Ended):
1200
V
1200
V
1200
0
V
CC
mV
mV
IH
CC
CC
D, D, SEL, SEL
V
Input LOW Voltage (Single−Ended):
D, D, SEL, SEL
0
V
CC
150
−
0
V
CC
−
V
CC
−
IL
150
150
Vth
Input Threshold Reference Voltage
Range (Note 11)
950
150
V
950
150
V
–75
950
150
V
CC
–75
mV
mV
CC
CC
–75
V
ISE
Single−Ended Input Voltage
2600
2600
2600
(V – V )
IH
IL
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figure 12) (Note 12)
V
Differential Input HIGH Voltage
(D, D, SEL, SEL)
1200
V
1200
0
V
1200
0
V
CC
mV
mV
mV
mV
IHD
CC
CC
V
Differential Input LOW Voltage
(D, D, SEL, SEL)
0
V
CC
75
−
V
CC
75
−
V
CC
75
−
ILD
V
Differential Input Voltage
75
2600
2500
75
2600
2500
75
2600
2500
ID
(V –V ) (D, D, SEL, SEL)
IHD
ILD
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13) (Figure 15)
1200
1200
1200
IHCMR
I
Input HIGH Current (@ V
)
D, D,
SEL, SEL
D, D,
30
5
100
50
30
5
100
50
30
5
100
50
mA
mA
IH
IH
I
Input LOW Current (@ V )
20
5
100
50
20
5
100
50
20
5
100
50
IL
IL
SEL, SEL
TERMINATION RESISTORS
Internal Input Termination Resistor
R
TIN
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
8. Input and output parameters vary 1:1 with V
.
CC
9. LVPECL outputs loaded with 50 W to (V − 2 V) for proper operation.
CC
10.V , V , V and V parameters must be complied with simultaneously.
th
IH
IL,,
ISE
11. V is applied to the complementary input when operating in single−ended mode. V = (V − V ) / 2.
th
th
IH
IL
12.V , V
V
and V
parameters must be complied with simultaneously.
IHD
IHCMR
ILD, ID
CMR
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
EE IHCMR
CC
IHCMR
input signal.
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6
NB7L86A
Table 11. DC CHARACTERISTICS, INPUT WITH LVPECL OUTPUT V = 3.3 V; V = 0 V, T = −40°C to +85°C (Note 14)
CC
EE
A
−405C
255C
855C
Min
23
Typ
Max
39
Min
Typ
Max
Min
Typ
Max
39
Symbol
POWER SUPPLY CURRENT
Characteristics
Unit
Negative Power Supply Current
30
23
30
39
23
30
mA
IEE
LVPECL OUTPUTS (Note 15)
V
V
Output HIGH Voltage
Output LOW Voltage:
2260
1320
2310
2370
2290
2340
2400
2315
2365
2425
mV
mV
OH
OL
(OLS = V
)
1470
2090
1670
1620
2180
1790
1360
2065
1585
1510
2125
1705
1660
2215
1825
1390
2090
1615
1540
2150
1735
1690
2240
1855
CC
(OLS = V − 0.4 V) 2030
(OLS = V − 0.8 V, 1550
CC
CC
OLS = FLOAT)
(OLS = V − 1.2 V) 2260
2310
1875
2390
1995
2290
1820
2340
1910
2420
2030
2315
1850
2365
1940
2445
2060
CC
(OLS = V ) (Note 20) 1785
EE
Output Amplitude Voltage:
(OLS = V
V
mV
OUTPP
)
705
815
220
640
695
125
530
805
215
635
690
125
525
800
215
630
CC
(OLS = V − 0.4 V) 130
CC
(OLS = V − 0.8 V, 535
CC
OLS = FLOAT)
(OLS = V − 1.2 V)
0
0
0
0
0
0
CC
(OLS = V ) (Note 20) 345
435
340
430
335
425
EE
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figure 11 & 13) (Note 16)
V
Input HIGH Voltage
(Single−Ended)
D, D, SEL, SEL
Input LOW Voltage
(Single−Ended)
D, D, SEL, SEL
1200
V
1200
V
1200
V
CC
mV
mV
IH
CC
CC
V
V
0
V
−
0
V
−
0
V
CC
−
IL
CC
CC
150
150
150
V –75 mV
CC
Input Threshold Reference Voltage
Range (Note 17)
950
150
V
–75 950
V
–75 950
th
CC
CC
V
ISE
Single−Ended Input Voltage
2600
150
2600
150
2600
mV
(V – V )
IH
IL
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figure 12) (Note 18)
V
Differential Input HIGH Voltage
(D, D, SEL, SEL)
1200
V
1200
0
V
1200
0
V
CC
mV
mV
mV
mV
IHD
CC
CC
V
Differential Input LOW Voltage
(D, D, SEL, SEL)
0
V
CC
75
−
V
CC
75
−
V
CC
−
ILD
75
V
Differential Input Voltage
75
2600
3300
75
2600
3300
75
2600
ID
(V
IHD
– V ) (D, D, SEL, SEL)
ILD
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19) (Figure 15)
1200
1200
1200
3300
IHCMR
Input HIGH Current (@V
)
D, D
SEL, SEL
D, D
30
5
20
5
100
50
100
50
30
5
20
5
100
50
100
50
30
5
20
5
100
50
100
50
I
mA
mA
IH
IH
Input LOW Current (@V )
I
IL
IL
SEL, SEL
TERMINATION RESISTORS
Internal Input Termination Resistor
R
TIN
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
14.Input and output parameters vary 1:1 with V
.
CC
15.LVPECL outputs loaded with 50 W to (V − 2 V) for proper operation.
CC
16.V , V , V and V parameters must be complied with simultaneously.
th
IH
IL,,
ISE
17.V is applied to the complementary input when operating in single−ended mode. V = (V − V ) / 2.
th
th
IH
IL
18.V , V
V
and V
parameters must be complied with simultaneously.
IHD
IHCMR
ILD, ID
CMR
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
EE IHCMR
CC
IHCMR
input signal.
20.When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .
CC
EE
EE
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NB7L86A
Table 12. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V = −3.465 V to −2.375 V, T = −40°C to +85°C (Note 21)
EE A
−405C
255C
855C
Min
Typ
Max
Min
Typ
Max
39
Min
23
Typ
Max
39
Symbol
POWER SUPPLY CURRENT
Negative Power Supply Current
LVPECL OUTPUTS (Note 22)
Characteristics
Unit
I
EE
23
30
39
23
30
30
mA
V
Output HIGH Voltage
Output LOW Voltage:
−1040 −990
−930 −1010 −960
−900
−985
−935
−875
mV
mV
OH
V
OL
−3.465 V ≤ V ≤ −3.0 V
EE
(OLS = V ) −1980 −1830 −1680 −1940 −1790 −1640 −1910 −1760 −1610
CC
(OLS = V − 0.4 V) −1270 −1210 −1120 −1235 −1175 −1085 −1210 −1150 −1060
CC
(OLS = V − 0.8 V, OLS = FLOAT) −1750 −1630 −1510 −1715 −1595 −1475 −1685 −1565 −1445
CC
(OLS = V − 1.2 V) −1040 −990
−910 −1010 −960
−880
−985
−935
−855
CC
EE
(OLS = V ) (Note 27) −1515 −1425 −1305 −1480 −1390 −1270 −1450 −1360 −1240
−3.0 V < V ≤ −2.375 V
EE
(OLS = V
)
−1945 −1795 −1645 −1905 −1755 −1605 −1875 −1725 −1575
CC
(OLS = V − 0.4 V) −1265 −1205 −1115 −1230 −1170 −1080 −1205 −1145 −1055
CC
(OLS = V − 0.8 V, OLS = FLOAT) −1725 −1605 −1485 −1690 −1570 −1450 −1660 −1540 −1420
CC
(OLS = V − 1.2 V) −1045 −995
−915 −1010 −960
−880
−990
−940
−860
CC
(OLS = V ) −1495 −1405 −1285 −1460 −1370 −1250 −1435 −1345 −1225
EE
V
mV
Output Voltage Amplitude:
OUTPP
−3.465 V ≤ V ≤ −3.0 V
EE
(OLS = V
)
705
815
220
640
0
695
125
530
0
805
215
635
0
690
125
525
0
800
215
630
0
CC
(OLS = V − 0.4 V) 130
CC
(OLS = V − 0.8 V, OLS = FLOAT) 535
CC
(OLS = V − 1.2 V)
0
CC
(OLS = V ) (Note 27) 345
435
340
430
335
425
EE
−3.0 V < V ≤ −2.375 V
EE
(OLS = V
)
670
800
215
615
5
660
120
505
0
795
210
610
0
655
120
500
0
790
210
605
5
CC
(OLS = V − 0.4 V) 125
CC
(OLS = V − 0.8 V, OLS = FLOAT) 510
CC
(OLS = V − 1.2 V)
0
CC
(OLS = V
)
325
415
320
410
320
410
EE
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figure 11 & 13) (Note 23)
V
Input HIGH Voltage (Single−Ended)
V
+
V
V
+
V
V
+
V
CC
mV
mV
mV
IH
EE
CC
EE
CC
EE
D, D, SEL, SEL
1200
1200
1200
V
V
Input LOW Voltage (Single−Ended)
D, D, SEL, SEL
V
V
−
V
V
VEE
V −
IH
150
IL
EE
IH
EE
IH−
150
150
Input Threshold Reference Voltage
Range (Note 24)
V
EE
+
V
CC
V
EE
+
V
CC
V
EE
+
V
CC
–75
th
950
–75
950
–75
950
V
ISE
Single−Ended Input Voltage
150
2600
150
2600
150
2600
mV
(V – V )
IH
IL
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8
NB7L86A
Table 12. DC CHARACTERISTICS, NECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V = −3.465 V to −2.375 V, T = −40°C to +85°C (Note 21)
EE A
−405C
Typ
255C
Typ
855C
Typ
Min
Max
Min
Max
Min
Max
Symbol
Characteristics
Unit
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figure 12) (Note 25)
V
Differential Input HIGH Voltage
(D, D, SEL, SEL)
V
+
V
V
+
V
V
+
V
CC
mV
mV
mV
mA
IHD
EE
CC
EE
CC
EE
1200
1200
120
V
Differential Input LOW Voltage
(D, D, SEL, SEL)
V
V
CC
75
−
V
V
CC
75
−
V
V
CC
75
−
ILD
EE
EE
EE
V
Differential Input Voltage
75
2600
0
75
2600
0
75
2600
0
ID
(V
IHD
– V ) (D, D, SEL, SEL)
ILD
V
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 26) (Figure 15)
V
+
V
+
V
+
IHCMR
EE
EE
EE
1200
1200
1200
I
mA
mA
(Input HIGH Current (@V
)
D, D,
SEL, SEL
D, D,
30
5
100
50
30
5
100
50
30
5
100
50
IH
IH
I
(Input LOW Current (@V )
20
5
100
50
20
5
100
50
20
5
100
50
IL
IL
SEL, SEL
TERMINATION RESISTORS
45
50
55
45
50
55
45
50
55
W
RTIN
Internal Input Termination Resistor
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
21.Input and output parameters vary 1:1 with V
.
CC
22.LVPECL outputs loaded with 50 W to (V − 2 V) for proper operation.
CC
23.V , V , V and V parameters must be complied with simultaneously.
th
IH
IL,,
ISE
24.V is applied to the complementary input when operating in single−ended mode. V = (V − V ) / 2.
th
th
IH
IL
25.V , V
V
and V
parameters must be complied with simultaneously.
IHD
IHCMR
ILD, ID
CMR
26.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
EE IHCMR
CC
IHCMR
input signal.
27.When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V .
CC
EE
EE
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9
NB7L86A
Table 13. AC CHARACTERISTICS V = 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V
CC
EE
CC
EE
−405C
Typ
8
255C
Typ
8
855C
Typ
8
Symbol
Characteristic
Unit
Min
Max
Min
Max
Min
Max
f
Maximum Input Clock Frequency
(See Figure 7) (Note 28)
7
7
7
GHz
max
f
f
< 7 GHz
590
270
730
440
470
230
720
420
540
180
700
390
mV
mV
Output Voltage Amplitude
in
V
OUTPP
(OLS = V
)
CC
= 8 GHz
in
t
t
PLH
Propagation Delay to Output Differential
110
160
5
210
15
115
165
5
215
15
120
170
5
220
15
ps
ps
ps
ps
ps
(Figure 15) D/SEL → Q
PHL
t
t
Duty Cycle Skew (Note 29)
SKEW
Q → D/SEL
Channel Skew
5
20
5
20
5
20
SKEW
t
S
Set−Up Time (Dx to SEL)
Hold−Up Time (Dx to SEL)
30
35
30
35
30
35
t
H
RMS Random Clock Jitter
(See Figure 7) (Note 31) fin ≤ 7 GHz
Peak−to−Peak Data Dependent Jitter
(Note 32) fin ≤ 7 Gb/s
0.5
12
1.5
0.5
12
1.5
0.5
12
1.5
t
JITTER
ps
V
Input Voltage Swing/Sensitivity (Differential
Configuration) (Note 30)
75
1890
75
1890
75
1890
mV
ps
INPP
t , t
Output Rise/ Fall Times
t
r
30
17
45
35
65
65
30
17
45
35
65
65
30
17
45
35
65
65
r
f
(20% − 80%) (Q, Q) @ 1 GHz
t
f
28.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V. Input edge rates 40 ps (20% − 80%).
CC
29.t
= |t
− t
| for a nominal 50% differential clock input waveform. See Figure 15.
SKEW
INPP
PLH
PHL
30.V
(max) cannot exceed V − V
.
CC
EE
31.Additive RMS jitter with 50% duty cycle clock signal at 7 GHz.
32.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2 −1 data rate at 7 Gb/s.
31
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10
NB7L86A
Figure 7. (VCC − VEE = 2.5 V @ 25°C)
NOTE: Output Voltage Amplitude (V
) / RMS Jitter vs. Input Frequency (f ) for 2:1 MUX Mode, Repetitive 1010 Input Data Pattern.
in
OUTPP
*When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V
CC
EE
EE.
NOTE: Output Voltage Amplitude (V
) / RMS Jitter vs. Input Frequency (f ) for 2:1 MUX Mode, Repetitive 1010 Input Data Pattern.
in
OUTPP
*When an output level of 400 mV is desired and V − V > 3.0 V, a 2 kW resistor should be connected from OLS to V
CC
EE
EE.
Figure 8. (VCC − VEE = 3.3 V @ 25°C)
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11
NB7L86A
Figure 9. Typical OLS Input Current vs. OLS Input Voltage
(VCC − VEE = 3.3 V @ 25°C)
Figure 10. OLS Operating Area
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12
NB7L86A
V
IH
IN
Vth
V
IL
IN
Vth
Figure 11. Differential Input Driven Single Ended
IN
IN
Figure 12. Differential Input Driven Differentially
V
CC
V
IHmax
V
thmax
V
ILmax
V
IH
V
th
V
V
th
IN
IL
V
IHmin
V
ILmin
V
thmin
V
EE
Figure 13. VTH Diagram
V
ID
= I V
− V
I
IHD(IN)
ILD(IN)
V
IN
IN
IHD
V
ILD
Figure 14. Differential Inputs Driven Differentially
V
CC
V
V
IHCMRmax
IHDmax
V
ILDmax
V
IHDtyp
IN
IN
V
V
ID
= V − V
IHD ILD
IHCMR
V
ILDtyp
V
IHCMRmin
V
V
IHDmin
ILDmin
V
EE
Figure 15. VIHCMR Diagram
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13
NB7L86A
D
V
V
= V
= V
− V
− V
INPP(D)
IH(D)
IL(D)
INPP(D)
IH(D)
IL(D)
D
Q
t
t
PLH
PHL
V
V
= V
− V
− V
OUTPP(Q)
OH(Q)
OL(Q)
= V
OUTPP(Q)
OH(Q)
OL(Q)
Q
Figure 16. AC Reference Measurement
SEL
SEL
Qx
t
t
PLH
PHL
Qx
Figure 17. SELX to QX Timing Diagram
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14
NB7L86A
APPLICATION INFORMATION
All NB7L86A inputs can accept PECL, CML, LVTTL,
LVCMOS and LVDS signal levels. The limitations for
differential input signal (LVDS, PECL, or CML) are
minimum input swing of 75 mV and the maximum input
swing of 2500 mV. Within these conditions, the input
voltage can range from V to 1.2 V. Examples interfaces
are illustrated below in a 50 W environment (Z = 50 W). For
output termination and interface, refer to application note
AND8020/D.
CC
Table 14. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
CML
Connect VTD and VTD to V (refer Figure 18)
CC
LVDS
Connect VTD and VTD together. (refer Figure 19)
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
Bias VTD and VTD inputs within the Common Mode range (V
Standard ECL termination techniques (refer Figure 21)
) (refer Figure 20)
CMR
An external voltage (V
) should be applied to the unused complementary
THR
differential input. Nominal V
is 1.5 V for LVTTL and V /2 for LVCMOS inputs.
THR
THR
CC
This voltage must be within the V
specification (refer Figure 22)
V
CC
V
CC
Z = 50 W
Q
D
50 W
NB7L86A
VTD
V
V
CML
Driver
CC
CC
VTD
50 W
Z = 50 W
Q
D
V
EE
V
EE
Figure 18. CML Interface
V
CC
V
CC
Z = 50 W
D
50 W
NB7L86A
50 W
VTD
LVDS
Driver
VTD
D
Z = 50 W
V
EE
V
EE
Figure 19. LVDS Interface
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15
NB7L86A
V
CC
V
CC
Z = 50 W
C
C
D
Recommended
RT values
50 W
NB7L86A
VTD
PECL
Driver
VCC
R
T
Vbias*
Vbias*
Z = 50 W
5.0 V 290 W
3.3 V 150 W
VTD
D
50 W
2.5 V
80 W
R
T
R
T
V
EE
V
EE
V
EE
Vbias must be within common mode range limits (V
*
)
CMR
Figure 20. PECL Interface
Z = 50 W
O
Q
Q
D
D
Driver
Receiver
Device
Device
Z = 50 W
O
50 W
50 W
V
TT
= V − 2.0 V
CC
V
TT
Figure 21. Typical termination for Output Driver and Device Evaluation
(refer AND8020/D – termination of ECL Logic Devices)
V
CC
V
CC
Z = 50 W
D
Recommended V
values
REF
50 W
V
REF
LVTTL/
LVCMOS
Driver
VTD
No Connect *
No Connect
V
− V
CC
EE
LVCMOS
LVTTL
NB7L86A
2
VTD
1.5 V
50 W
V
REF
D
V
EE
* or 60 pF to GND
V
EE
Figure 22. LVCMOS/LVTTL Interface
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16
NB7L86A
ORDERING INFORMATION
Device
†
Package Type
Shipping
NB7L86AMNG
QFN16
123 Units / Rail
(Pb−Free / Halide−Free)
NB7L86AMNHTBG
QFN16
100 / Tape & Reel
(Pb−Free / Halide−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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17
NB7L86A
PACKAGE DIMENSIONS
QFN16 3x3, 0.5P
CASE 485G−01
ISSUE F
NOTES:
D
A
B
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN 1
LOCATION
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
NOM MAX
A
0.90
1.00
0.05
0.03
2X
A3
0.10
C
EXPOSED Cu
MOLD CMPD
A3
b
D
0.20 REF
0.24
3.00 BSC
1.75
0.18
0.30
1.85
1.85
2X
0.10
C
TOP VIEW
D2 1.65
E
3.00 BSC
1.75
0.50 BSC
0.18 TYP
0.40
DETAIL B
A1
(A3)
E2 1.65
e
K
L
0.05
0.05
C
DETAIL B
ALTERNATE
A
C
0.30
0.50
0.15
CONSTRUCTIONS
L1 0.00
0.08
NOTE 4
A1
SEATING
PLANE
C
SIDE VIEW
RECOMMENDED
SOLDERING FOOTPRINT*
16X
0.10
C
A
B
0.58
DETAIL A
D2
PACKAGE
16X
L
OUTLINE
8
1
4
1
9
2X
2X
E2
1.84
3.30
16X
K
16X
0.30
16
16X b
e
e/2
0.10
0.05
C
C
A B
0.50
PITCH
NOTE 3
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
GigaComm is trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
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