NB7NPQ7042MMUTWG [ONSEMI]
3.3 V USB 3.1 四沟道 / 双端口线性再驱动器;
| 型号： | NB7NPQ7042MMUTWG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V USB 3.1 四沟道 / 双端口线性再驱动器 驱动 商用集成电路 驱动器 |
| 文件： | 总11页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7NPQ7042M
3.3 V USB 3.1 Quad Channel/
Dual Port Linear Redriver
Description
The NB7NPQ7042M is a 3.3 V quad channel / dual port linear
redriver suitable for USB 3.1 Gen 1 and USB 3.1 Gen 2 applications
that supports both 5 Gbps and 10 Gbps data rates. Signal integrity
degrades from PCB traces, transmission cables, and inter−symbol
interference (ISI). The NB7NPQ7042M compensates for these losses
by engaging varying levels of equalization at the input receiver, and flat
gain amplification on the output transmitter. The Flat Gain and
Equalization are controlled by four level control pins. Each channel has
a set of independent control pins to make signal optimization possible.
After power up, the NB7NPQ7042M periodically checks both of the
TX output pairs of each port for a receiver connection. When the receiver
is detected on both channels, the RX termination becomes enabled of
that respective port and is set to perform the redriver function.
The port becomes active once both TX outputs have detected
50−ohm termination, and the NB7NPQ7042M is set to perform the
redriver function. Port AB (channels A & B) and port CD (channels C
& D) are independent of each other.
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MARKING
DIAGRAM
NB7N
7042
ALYWG
G
1
X2QFN34
CASE 722AL
NB7N7042 = Specific Device Code
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The NB7NPQ7042M comes in a small 3.1 x 4.3 mm X2QFN34
package and is specified to operate across the entire industrial
temperature range, –40°C to 85°C.
(Note: Microdot may be in either location)
Features
ORDERING INFORMATION
• 3.3 V 5% Power Supply
†
Device
Package Shipping
• Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• Automatic Receiver Termination Detection
• Integrated Input and Output Termination
• Independent, Selectable Equalization and Flat Gain
• Hot−Plug Capable
• Flow−through Design for Ease of PCB Layout
• ESD Protection: 2 kV HBM
NB7NPQ7042MMUTWG X2QFN34
3000 /
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• Operating Temperature Range: −40°C to 85°C
• Small 3.1 x 4.3 x 0.35 mm X2QFN34 Package
• This is a Pb−Free Device
Typical Applications
• USB3.1 Type−C and Type−A Signal Routing
• Mobile Phone and Tablet
• Computer and Laptop
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V., Set−Top Boxes
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
October, 2018 − Rev. 0
NB7NPQ7042M/D
NB7NPQ7042M
CTRL_A1
CTRL_A0
Channel A Control Logic
A_RX−
1
2
34
A_TX−
A_TX−
A_TX+
B_RX−
B_RX+
A_RX−
A_RX+
B_TX−
33
32
31
30
29
28
27
Receiver/
Equalizer
Driver
A_TX+
A_RX+
B_TX−
B_TX+
26 B_RX−
3
Receiver/
Equalizer
Driver
4
B_TX+
25 B_RX+
VCC
5
CTRL_B1
24
23
22
Channel B Control Logic
GND
Exposed
Pad EP
CTRL_B1
CTRL_B0
CTRL_C1
CTRL_C0
6
CTRL_C0
CTRL_C1
C_RX−
C_RX+
D_TX−
D_TX+
CTRL_B0
VCC
7
Channel C Control Logic
C_RX−
C_RX+
D_TX−
D_TX+
C_TX−
8
21 C_TX−
C_TX+
19 D_RX−
18
Receiver/
Equalizer
Driver
C_TX+
9
20
D_RX−
10
11
Receiver/
Equalizer
Driver
12
13
14
15
16
17
D_RX+
D_RX+
Channel D Control Logic
CTRL_D1
CTRL_D0
Figure 1. Logic Diagram
Figure 2. X2QFN34 Package Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
Channel A Differential input for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
1
A_RX−
A_RX+
B_TX−
B_TX+
VCC
DIFF
INPUT
2
3
DIFF
OUTPUT
Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
4
5, 13, 22, 30
POWER 3.3V power supply. V pins must be externally connected to power supply to guarantee proper
CC
operation.
6
7
CTRL_C0 LVCMOS Pin C0 for control of Flat Gain settings on Channel C having internal 100 kW pull up and 200 kW pull
INPUT down. 4 state input: HIGH “H” where pin is connected to VCC, LOW “L” where pin is connected to
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
CTRL_C1 LVCMOS Pin C1 for control of Equalization settings on Channel C having internal 100 kW pull up and 200 kW
INPUT pull down. 4 state input: HIGH “H” where pin is connected to VCC, LOW “L” where pin is connected to
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
8
C_RX−
C_RX+
D_ TX−
D_TX+
NC
DIFF
Channel C Differential input for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
Channel D Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
No connection, must be left Open/Float
INPUT
9
DIFF
OUTPUT
10
11
12, 17, 29, 34
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NB7NPQ7042M
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
14
CTRL_D0 LVCMOS Pin D0 for control of Equalization settings on Channel D having internal 100 kW pull up and 200 kW
INPUT pull down. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected
CC
to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
15
CTRL_D1 LVCMOS Pin D1 for control of Flat Gain settings on Channel D having internal 100 kW pull up and 200 kW pull
INPUT down. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
CC
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
16, 33
GND
GROUND Reference Ground. GND pins must be externally connected to ground to guarantee proper opera-
tion.
18
19
20
21
23
D_RX+
D_RX−
C_TX+
C_TX−
DIFF
Channel D Differential input for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
INPUT
DIFF
OUTPUT
Channel C Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
CTRL_B0 LVCMOS Pin B0 for control of Flat Gain settings on Channel B having internal 100 kW pull up and 200 kW pull
INPUT down. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
CC
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
24
CTRL_B1 LVCMOS Pin B1 for control of Equalization settings on Channel B having internal 100 kW pull up and 200 kW
INPUT pull down. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected
CC
to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
25
26
27
28
31
B_RX+
B_RX−
A_TX+
A_TX−
DIFF
Channel B Differential input for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
INPUT
DIFF
OUTPUT
Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
CTRL_A0 LVCMOS Pin A0 for control of Equalization settings on Channel A having internal 100 kW pull up and 200 kW
INPUT pull down. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected
CC
to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
32
CTRL_A1 LVCMOS Pin A1 for control of Flat Gain settings on Channel A having internal 100 kW pull up and 200 kW pull
INPUT down. 4 state input: HIGH “H” where pin is connected to V , LOW “L” where pin is connected to
CC
Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor 68
kW connected from pin to Ground. Refer Table 2 for the different settings.
EP
GND
GROUND Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved heat
transfer out of the package. The pad is not electrically connected to the die, but is recommended to
be soldered to GND on the PC Board.
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NB7NPQ7042M
DEVICE CONFIGURATION
Table 2. CONTROL PIN EFFECTS (Typical Values)
PORT A/B
PORT C/D
Channel A
Channel B
Channel C
CTRL_C1 CTRL_C0
Channel D
CTRL_A1 CTRL_A0 CTRL_B1
CTRL_B0
(FGB)
CTRL_D1
CTRL_D0
(EQD)
EQ
FG
(FGA)
L
(EQA)
(EQB)
(EQC)
(FGC)
(FGD)
(dB)
(dB)
Settings
1
L
R
F
H
L
L
R
F
H
L
L
L
L
R
F
H
L
L
L
L
R
F
H
L
10.9
6.7
−3
−3
−3
−3
−1.5
−1.5
−1.5
−1.5
0
2
L
L
L
3
L
L
L
L
8.9
4
L
L
L
L
13.1
10.9
6.7
5
R
R
R
R
F
R
R
R
R
F
F
F
F
H
H
H
H
R
R
R
R
F
R
R
R
R
F
6
R
F
H
L
R
F
H
L
R
F
H
L
R
F
H
L
7
8.9
8
13.1
10.9
6.7
9
10
F
R
F
H
L
R
F
H
L
R
F
H
L
F
F
R
F
H
L
0
11 (Default)
F
F
F
8.9
0
12
13
14
15
16
F
F
F
13.1
10.9
6.7
0
H
H
H
H
H
H
H
H
H
H
H
H
2
R
F
H
R
F
H
R
F
H
R
F
H
2
8.9
2
13.1
2
NOTE: EQ and FG can be set by adjusting the voltage to the control pins. There are 4 specific levels – HIGH “H” where pin is connected
to V , LOW “L” where pin is connected to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external
CC
resistor 68 kW connected from pin to Ground. Please refer Table 7 for voltage levels.
Table 3. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
≤ 2 kV
≤ 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Dry pack (Note 1)
Flammability Rating
Level 1
UL 94 V−O @ 0.125 in
81,034
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. For additional information, see Application Note AND8003/D.
Table 4. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
−0.5
−0.5
−0.5
−65
Max
Unit
V
Supply Voltage (Note 2)
Voltage range at any input or output terminal
V
CC
4.6
Differential I/O
V
V
+ 0.5
V
CC
CC
LVCMOS inputs
+ 0.5
V
Storage Temperature Range, T
150
°C
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
125
85
J
Operating Ambient Temperature Range, T
−40
A
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 3)
34
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB7NPQ7042M
Table 5. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.135
−40
Nom
Max
3.465
+85
Unit
V
V
C
Main power supply
3.3
CC
T
A
Operating free−air temperature
AC coupling capacitor
°C
75
100
68
265
nF
kW
AC
Rext
External Resistor for input setting “R” 5%
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. POWER SUPPLY CHARACTERISTICS
Typ
(Note 4)
Parameter
Test Conditions
Min
Max
Unit
mA
mA
mA
Active
Link in U0 with Super Speed Plus data transmission
Link in U2 or U3 power saving state
225
I
CC
U2/U3
0.8
No USB Connection
4. TYP values use V = 3.3 V, T = 25°C
No connection state, termination disabled
0.5
CC
A
Table 7. LVCMOS CONTROL PIN CHARACTERISTICS
4−State LVCMOS Inputs (CTRL_A0, CTRL_A1, CTRL_B0, CTRL_B1, CTRL_C0, CTRL_C1, CTRL_D0, CTRL_D1)
Parameter
Test Conditions
Min
Typ
Max
0.1*V
Unit
V
V
IL
DC Input Setting “L” LOW
DC Input Setting “R” with Rext
Input pin connected to GND
GND
CC
V
IR
Rext (typ 68 kW) must be connect- 0.23*V 0.33*V 0.43*V
V
CC
CC
CC
ed between Pin and GND, [Logic
1/3 * V
]
CC
V
IF
DC Input Setting “F” FLOAT (Note 5)
Input pin is left FLOAT (open),
[Logic 2/3 * V
0.56*V 0.66*V 0.76*V
V
CC
CC
CC
]
CC
V
DC Input Setting “H” HIGH
Internal pull−up resistance
Internal pull−down resistance
High−level input current
Low−level input current
Input pin connected to V
V
CC
V
IH
PU
PD
IH
CC
R
R
100
200
kW
kW
mA
mA
I
V
V
= 3.465 V, V = 3.465 V
25
IN
CC
I
IL
= GND, V = 3.465 V
−45
IN
CC
5. Floating refers to a pin left in an open state, with no external connections.
Table 8. RECEIVER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Input differential voltage swing
AC−coupled, peak−to−peak
100
1200
mV
PP
RX−DIFF−pp
V
Common−mode voltage bias in the
receiver (DC)
V
CC
V
RX−CM
Z
Differential input resistance (DC)
Present after an USB device is
80
20
100
25
120
30
W
RX−DIFF
detected on TX+/TX−
Z
Common−mode input resistance (DC) Present after an USB device is
detected on TX+/TX−
W
RX−CM
Z
Common−mode input resistance
with termination disabled (DC)
Present when no USB device is
detected on TX+
25
kW
RX−HIGH−IMP
V
Low Frequency Periodic Signaling
(LFPS) Detect Threshold
Output voltage is considered
squelched below this threshold
voltage.
100
200
300
mV
PP
TH−LFPS−pp
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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NB7NPQ7042M
Table 9. TRANSMITTER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
−1 dB compression point Output
swing at 100 MHz
100 MHz Sinewave Input
900
mV
sw_100M
PPd
V
−1 dB compression point Output
5 GHz Sinewave Input
At 2.5 GHz
900
mV
sw_5G
PPd
swing at 5 GHz
C
TX input capacitance to GND
1.25
100
pF
TX
Z
Differential output impedance (DC)
Present after an USB device is
detected on TX+/TX−
80
20
120
30
W
TX−DIFF
Z
Common−mode output impedance
(DC)
Present after an USB device is
detected on TX+/TX−
25
90
W
TX−CM
I
TX short circuit current
TX+ or TX− shorted to GND
mA
V
TX−SC
V
Common−mode voltage bias in the
transmitter (DC)
100 mV, 50 MHz, 5 Gbps and
V
−0.8
V
CC
TX−CM
CC
7
10 Gbps, PRBS 2
V
AC common−mode peak−to−peak
Within U0 and at 50 MHz (LFPS)
100
10
mV
TX−CM−ACpp
PP
voltage swing in active mode
V
Differential voltage swing during
electrical idle
Tested with a high−pass filter
0
mV
TX−IDLE−DIFF−ACpp
PP
V
Voltage change to allow receiver
detect
The change in voltage that triggers
detection of a receiver.
325
600
mV
TX−RXDET
t , t
Output rise, fall time
20% − 80% of differential
voltage measured 1 inch from
the output pin
35
ps
ps
R
F
t
Output rise, Fall time mismatch
20% − 80% of differential
voltage measured 1 inch from
the output pin
5
RF−MM
t
, t
Differential propagation delay
Idle exit time
Propagation delay between
50% level at input and output
90
5
ps
ns
ns
diff−LH diff−HL
t
50 MHz clock signal, EQ an FG
setting “11 (Default)” FF
idleExit
t
Idle entry time
50 MHz clock signal, EQ an FG
setting “11 (Default)” FF
20
idleEntry
Table 10. TIMING AND JITTER CHARACTERISTICS
Parameter
TIMING
Test Conditions
Min
Typ
Max
Unit
t
Time from power applied until RX
termination is enabled
Apply 0 V to V , connect USB ter-
100
ms
READY
CC
mination to TX , apply 3.3 V to
V
CC
, and measure when Z
RX−DIFF
is enabled
JITTER FOR 5 Gbps
T
Total jitter (Notes 6, 7)
EQ and FG Setting “FF”
0.035
UI
(Note 8)
JTX−EYE
D
R
Deterministic jitter (Note 7)
Random jitter (Note 7)
0.003
0.005
UI
UI
JTX
JTX
JITTER FOR 10 Gbps
T
Total jitter (Notes 6, 7)
EQ and FG Setting “FF”
0.085
UI
(Note 8)
JTX−EYE
D
R
Deterministic jitter (Note 7)
Random jitter (Note 7)
0.04
UI
UI
JTX
JTX
0.007
−12
6. Includes RJ at 10
.
7. Measured at the ends of reference channel with a K28.5 pattern, VID = 1000 mVpp, −3.5 dB de−emphasis from source.
8. 5 Gbps, UI = 200 ps for 10 Gbps, UI = 100 ps
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NB7NPQ7042M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
V
OH
80%
Rx+
t
t
diff−HL
diff−LH
20%
Tx−
V
OL
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
APPLICATION GUIDELINES
LFPS Compliance Testing
bias (with an internal pull up resistor of 100 kW and pull
down resistor of 200 kW) the control pins to the correct
As part of USB 3.1 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ7042M is tested as a part of a USB
compliant system to ensure that it maintains compliance
while increasing system performance.
voltage (Logic 2/3 * V ). The low setting “L” can be set by
CC
pulling the control pin to ground. The high setting “H” can
be set by pulling the pin high to V . The Rext setting can
CC
be set by adding a 68 kW resistor from the control pin to
ground. This will bias the redriver internal voltage to Logic
LFPS Functionality
USB 3.1, Gen1 and Gen2 use Low Frequency Periodic
Signaling.
1/3 * V
.
CC
Linear Equalization
(LFPS) to implement functions like exiting low−power
modes, performing warm resets and providing link training
between host and peripheral devices. LFPS signaling
consists of bursts of frequencies ranging between 10 to
50 MHz and can have specific burst lengths or repeat rates.
The linear equalization that the NB7NPQ7042M provides
compensates for losses that occur naturally along board
traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping.LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1130 mV using 3 dB of flat gain.
Control Pin Settings
Control pins CTRL_A1, CTRL_B0, CTRL_C0 &
CTRL_D1 controls the flat gain and CTRL_A0, CTRL_B1,
CTRL_C1 & CTRL_D0 controls the equalization of
channels A, B, C and D respectively.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the FG.
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NB7NPQ7042M
Upto
2 dB loss
Upto 11 dB loss
CTRL_A1
CTRL_A0
Channel A Control Logic
A_RX−
A_TX−
220 nF
220 nF
330 nF
330 nF
220 nF
220 nF
Receiver/
Equalizer
Driver
A_RX+
A_TX+
B_RX−
B_TX−
220 nF
220 nF
Receiver/
Equalizer
kW
220
Driver
kW
B_TX+
220
B_RX+
Channel B Control Logic
CTRL_B1
CTRL_B0
CTRL _ C 1
CTRL _ C 0
Channel C Control Logic
C_TX−
C_RX−
220 nF
220 nF
220 nF
220 nF
330 nF
330 nF
Receiver/
Equalizer
Driver
C_RX+
C_TX+
D_TX−
D_RX−
220 nF
220 nF
Receiver/
Equalizer
kW
220
Driver
kW
220
D_RX+
D_TX+
Channel D Control Logic
CTRL_D1
CTRL_D0
Figure 5. USB 3.1 Host Side NB7NPQ7042M Application
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NB7NPQ7042M
Table 11. DESIGN REQUIREMENTS
Design Parameter
Value
Supply Voltage
3.3 V nominal, (3.135 V to 3.465 V)
Operation Mode (Control Pin Selection)
AC Coupling Capacitors
“F” Float by Default, to be adjusted based on application losses. See Table 2
220 nF nominal, 75 nF to 265 nF, see Figure 5
R
68 kW, 5%
ext
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 KW to 220 KW
100 nF to GND close to each Vcc pin, and 10 mF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ7042M
Trace loss of FR4 after NB7NPQ7042M
Linear Range at 5 GHz
Up to 11 dB
Up To 2 dB. Keep as short as possible for best performance.
900 mV differential
−3 dB, −1.5 dB, 0 dB, 2 dB
6.7 to 13 dB
DC Flat Gain Options
Equalization Options
Differential Trace Impedance
90 W 10%
9. Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
Typical Layout Practices
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
• Traces should be routed as straight and symmetric as
possible.
plane. This will help reduce EMI and noise on the data
lines.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
• RX and TX differential pairs should always be placed
and routed on the same layer directly above a ground
www.onsemi.com
9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
X2QFN34 3.1x4.3, 0.4P
CASE 722AL
ISSUE O
DATE 02 MAY 2017
1
NOTES:
B
E
A
SCALE 4:1
D
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.20 AND 0.25 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE PLATED TERMINALS.
L
PIN ONE
REFERENCE
L1
DETAIL A
MILLIMETERS
DIM MIN
NOM
0.35
−−−
0.17
3.10
1.90
4.30
3.10
MAX
0.40
0.05
0.22
3.20
2.00
4.40
3.20
A
A1
b
D
D1
E
E1
e
K
L
L1
0.30
−−−
0.12
3.00
1.80
4.20
3.00
MOLD
COMPOUND
0.40 BSC
0.35 REF
0.25
TOP VIEW
A
C
DETAIL B
0.20
0.30
0.10
C
C
DETAIL B
0.05 REF
GENERIC
0.08
A1
SEATING
PLANE
MARKING DIAGRAM*
NOTE 4
SIDE VIEW
D1
34X L
DETAIL A
XXXXX
XXXXX
ALYWG
G
11
18
XXXXX = Specific Device Code
A
L
= Assembly Location
= Wafer Lot
E1
Y
W
G
= Year
= Work Week
= Pb−Free Package
e
1
(Note: Microdot may be in either location)
28
34
K
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some products
may not follow the Generic Marking.
34X
b
e
0.10 C A
B
0.05 C
NOTE 3
BOTTOM VIEW
RECOMMENDED
SOLDERING FOOTPRINT
3.16
2.00
34X
0.31
34
1
4.36
3.20
PACKAGE
OUTLINE
34X
0.22
0.40
PITCH
DIMENSIONS: MILLIMETERS
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON63532G
X2QFN34 3.1X4.3, 0.4P
PAGE 1 OF 1
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