NBSG14 [ONSEMI]
2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL Outputs; 2.5V / 3.3V的SiGe差分1 ： 4时钟/数据RSECL输出驱动器
| 型号： | NBSG14 |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL Outputs |
| 文件： | 总13页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBSG14
2.5V/3.3VꢀSiGe Differential
1:4 Clock/Data Driver with
RSECL* Outputs
*Reduced Swing ECL
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MARKING DIAGRAMS*
Description
The NBSG14 is a 1−to−4 clock/data distribution chip, optimized for
ultra−low skew and jitter.
SG
14
ALYW
Inputs incorporate internal 50 ꢀ termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV.
FCBGA−16
BA SUFFIX
CASE 489
Features
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• 30 ps Typical Rise and Fall Times
• 125 ps Typical Propagation Delay
16
1
SG14
ALYWG
G
• RSPECL Output with Operating Range: V = 2.375 V to 3.465 V
QFN−16
MN SUFFIX
CASE 485G
CC
with V = 0 V
EE
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V = 0 V with V = −2.375 V to −3.465 V
CC
EE
• RSECL Output Level (400 mV Peak−to−Peak Output),
Differential Output
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
• 50 ꢀ Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
• Pb−Free Packages are Available
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 9
NBSG14/D
NBSG14
1
2
3
4
V
Q0
15
Q0
14
V
CC
EE
Exposed Pad (EP)
16
13
VTCLK
Q3
Q3
Q2
A
B
VTCLK
1
2
3
4
12
11
10
9
Q1
Q1
Q2
Q2
CLK
CLK
VEE
VEE
VCC
VCC
Q2
Q1
CLK
CLK
NBSG14
C
D
VTCLK
VTCLK
Q0
Q0
Q1
5
6
7
8
V
EE
Q3
Q3
V
CC
Figure 1. BGA−16 Pinout (Top View)
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
D1
QFN
Name
VTCLK
CLK
I/O
Description
1
2
−
Internal 50 ꢀ Termination pin. See Table 2.
C1
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 kꢀ to V and 36.5 kꢀ to V
.
EE
CC
B1
3
CLK
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 kꢀ to VEE.
A1
4
VTCLK
−
−
Internal 50 ꢀ Termination Pin. See Table 2.
B2,C2
5,16
V
EE
Negative Supply Voltage. All V Pins must be Externally Connected to
EE
Power Supply to Guarantee Proper Operation.
A2*
A3*
6
7
Q3
Q3
RSECL Output
RSECL Output
−
Inverted Differential Output 3. Typically Terminated with 50 ꢀ to
V
TT
= V − 2 V*
CC
Noninverted Differential Output 3. Typically Terminated with 50 ꢀ to
= V − 2 V*
V
TT
CC
B3,C3
A4*
8,13
9
V
CC
Positive Supply Voltage. All V Pins must be Externally Connected to
CC
Power Supply to Guarantee Proper Operation.
Q2
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
RSECL Output
−
Inverted Differential Output 2. Typically Terminated with 50 ꢀ to
V
TT
= V − 2 V*
CC
B4*
10
11
12
14
15
−
Q2
Q1
Q1
Q0
Q0
EP
Noninverted Differential Output 2. Typically Terminated with 50 ꢀ to
= V − 2 V*
V
TT
CC
C4*
D4*
D3*
D2*
N/A
Inverted Differential Output 1. Typically Terminated with 50 ꢀ to
= V − 2 V*
V
TT
CC
Noninverted Differential Output 1. Typically Terminated with 50 ꢀ to
= V − 2 V*
V
TT
CC
Inverted Differential Output 0. Typically Terminated with 50 ꢀ to
= V − 2 V*
V
TT
CC
Noninverted Differential Output 0. Typically Terminated with 50 ꢀ to
= V − 2 V*
V
TT
CC
Exposed Pad. The thermally exposed pad on package bottom (see case
drawing) must be attached to a heat−sinking conduit.
1. In the differential configuration when the input termination pins (VTCLK, VTCLK) are connected to a common termination voltage, if no
signal is applied then the device will be susceptible to self−oscillation.
*Devices in BGA package typically terminated with 50 ꢀ to V = V − 1.5 V.
TT
CC
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2
NBSG14
V
CC
Q3
Q3
VTCLK
36.5 Kꢀ
Q2
Q2
50 ꢀ
CLK
CLK
75 Kꢀ
75 Kꢀ
50 ꢀ
Q1
Q1
VTCLK
Q0
Q0
V
EE
Figure 3. Logic Diagram
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
Connect VTCLK and VTCLK to V
CML
LVDS
CC
Connect VTCLK and VTCLK Together
Bias VTCLK and VTCLK Inputs within
AC−COUPLED
Common Mode Range (V
)
IHCMR
RSECL, PECL, NECL
LVTTL, LVCMOS
Standard ECL Termination Techniques
An External Voltage (V
) should be Applied to the
THR
Unused Differential Input. Nominal V
is 1.5 V for LVTTL
THR
and V /2 for LVCMOS Inputs. This Voltage must be
CC
within the V
Specification.
THR
Table 3. ATTRIBUTES
Characteristics
Value
Value
Internal Input Pulldown Resistor (CLK, CLK)
Internal Input Pullup Resistor (CLK)
75 kꢀ
36.5 kꢀ
ESD Protection
Human Body Model
> 2 kV
> 100 V
Machine Model
Moisture Sensitivity (Note 1)
Pb Pkg
Pb−Free Pkg
FCBGA−16
QFN−16
Level 3
Level 1
N/A
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
158
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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NBSG14
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
= 0 V
Condition 2
Rating
3.6
Unit
V
V
CC
V
EE
V
I
Positive Power Supply
Negative Power Supply
V
V
EE
= 0 V
−3.6
V
CC
Positive Input
Negative Input
V
EE
V
CC
= 0 V
= 0 V
V v V
3.6
−3.6
V
V
I
I
CC
EE
V w V
V
INPP
Differential Input Voltage |CLK−CLK|
V
CC
V
CC
− V w 2.8 V
2.8
|V −V
CC
V
EE
− V < 2.8 V
|
EE
EE
I
I
Input Current Through R (50 ꢀ Resistor)
Static
Surge
45
80
mA
mA
IN
T
Output Current
Continuous
Surge
25
50
mA
mA
OUT
T
Operating Temperature Range
Storage Temperature Range
16 FCBGA
16 QFN
−40 to +70
−40 to +85
°C
A
T
stg
−65 to +150
°C
ꢁ
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
0 lfpm
16 FCBGA
16 FCBGA
16 QFN
108
86
41.6
35.2
°C/W
°C/W
°C/W
°C/W
JA
500 lfpm
16 QFN
ꢁ
Thermal Resistance (Junction−to−Case)
2S2P (Note 2)
2S2P (Note 3)
16 FCBGA
16 QFN
5
4.0
°C/W
°C/W
JC
T
sol
Wave Solder
Pb
Pb−Free
225
225
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard 51−6, multilayer board − 2S2P (2 signal, 2 power).
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG14
Table 5. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 2.5 V; V = 0 V (Note 4)
CC
EE
−40°C
Typ
25°C
70°C(BGA)/85°C(QFN)**
Min
45
Max
75
Min
45
Typ
60
Max
75
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 5)
Output Amplitude Voltage
Unit
mA
mV
mV
mV
I
EE
60
V
OH
1525
315
1575
405
1625
495
1550
315
1610
405
1650
495
1575
315
1635
405
1675
495
V
V
OUTPP
IH
Input HIGH Voltage (Single−Ended)
(Notes 7 and 9)
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
1435 1000*
1435 1000*
1435
1000*
V
V
V
Input LOW Voltage (Single−Ended)
(Notes 8 and 9)
V
−
V
−
V
150
−
V
−
V
−
V
150
−
V
2500
−
V
1400*
−
V −
IH
150
mV
mV
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
2500 1400*
2500 1400*
Input Threshold Voltage
(Single−Ended) (Note 9)
V
EE
+
V
CC
−
V
EE
+
V
CC
−
V
EE
+
V
CC
−
THR
IHCMR
1125
75
1125
75
1125
75
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 6)
1.2
2.5
1.2
2.5
1.2
45
2.5
R
Internal Input Termination Resistor
45
50
80
25
55
45
50
80
25
55
50
80
25
55
ꢀ
TIN
I
Input HIGH Current (@ V
)
150
100
150
100
150
100
ꢂ A
ꢂ A
IH
IL
IH
I
Input LOW Current (@ V )
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
4. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −0.5 V.
CC
EE
5. All outputs loaded with 50 ꢀ to V − 1.5 V for BGA package and V − 2 V for QFN package. V /V measured at V /V (Typical).
CC
CC
OH OL
IH IL
6. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
7. V cannot exceed V . |V − V
| < 2600 mV.
IH
CC
IH
THR
8. V always ≥ V . |V − V
| < 2600 mV.
IL
9. V
EE
IL
THR
is the voltage applied to one input when running in single−ended mode.
THR
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NBSG14
Table 6. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT V = 3.3 V; V = 0 V (Note 10)
CC
EE
−40°C
Typ
25°C
70°C(BGA)/85°C(QFN)**
Min
45
Max
75
Min
45
Typ
60
Max
75
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 11)
Output Amplitude Voltage
Unit
mA
mV
mV
mV
I
EE
60
V
OH
2325
350
2375
440
2425
530
2350
350
2410
440
2450
530
2375
350
2435
440
2475
530
V
V
OUTPP
IH
Input HIGH Voltage (Single−Ended)
(Notes 13 and 15)
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
V
CC
−
V
CC
−
V
CC
1435 1000*
1435 1000*
1435
1000*
V
V
V
Input LOW Voltage (Single−Ended)
(Notes 14 and 15)
V
−
V
−
V
150
−
V
−
V
−
V
150
−
V
2500
−
V
1400*
−
V −
IH
150
mV
mV
V
IL
IH
CC
IH
IH
CC
IH
IH
CC
2500 1400*
2500 1400*
Input Threshold Voltage
(Single−Ended) (Note 15)
V
EE
+
V
CC
−
V
EE
+
V
CC
−
V
EE
+
V
CC
−
THR
IHCMR
1125
75
1125
75
1125
75
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 12)
1.2
3.3
1.2
3.3
1.2
45
3.3
R
Internal Input Termination Resistor
45
50
80
25
55
45
50
80
25
55
50
80
25
55
ꢀ
TIN
I
Input HIGH Current (@ V
)
150
100
150
100
150
100
ꢂ A
ꢂ A
IH
IL
IH
I
Input LOW Current (@ V )
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
10.Input and output parameters vary 1:1 with V . V can vary +0.3 V to −0.165 V.
CC
EE
11. All outputs loaded with 50 ꢀ to V − 1.5 V for BGA package and V − 2 V for QFN package. V /V measured at V /V (Typical).
CC
CC
OH OL
IH IL
12.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
13.V cannot exceed V . |V − V
| < 2600 mV.
IH
CC
IH
THR
14.V always ≥ V . |V − V
| < 2600 mV.
IL
15.V
EE
IL
THR
is the voltage applied to one input when running in single−ended mode.
THR
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NBSG14
Table 7. DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V = −3.465 V to −2.375 V (Note 16)
EE
−40°C
Typ
60
25°C
Typ
60
70°C(BGA)/85°C(QFN)**
Min
Max
Min
45
Max
Min
45
Typ
60
Max
75
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 17)
Output Amplitude Voltage
Unit
mA
mV
mV
I
EE
45
75
75
V
OH
−975 −925 −875
−950
−890 −850
−925
−865
−825
V
OUTPP
−3.465 V v V v −3.0 V
350
315
440
405
530
495
350
315
440
405
530
495
350
315
440
405
530
495
EE
−3.0 V < V v −2.375 V
EE
V
V
V
V
Input HIGH Voltage (Single−Ended)
(Notes 19 and 21)
V
−
V
−
V
V
−
V
−
V
V
1435
−
V
1000*
−
V
CC
mV
mV
mV
V
IH
CC
CC
CC
CC
CC
CC
CC
CC
1435 1000*
1435 1000*
Input LOW Voltage (Single−Ended)
(Notes 20 and 21)
V
−
V
CC
−
V
IH
−
V
−
V
CC
−
V
IH
−
V
2500
−
V
CC
−
V −
IH
150
IL
IH
IH
IH
2500 1400* 150
2500 1400* 150
1400*
Input Threshold Voltage
(Single−Ended) (Note 21)
V
EE
+
V
75
−
V
EE
+
V
75
−
V
EE
+
V
75
−
THR
IHCMR
CC
CC
CC
1125
1125
1125
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 18)
V
+ 1.2
0.0
V
+ 1.2
0.0
V
+ 1.2
0.0
EE
EE
EE
R
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
80
25
55
ꢀ
TIN
I
IH
I
IL
Input HIGH Current (@ V
)
80
25
150
100
80
25
150
100
150
100
ꢂ A
ꢂ A
IH
Input LOW Current (@ V )
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
**The device packaged in FCBGA−16 have maximum temperature specification of 70°C and devices packaged in QFN−16 have maximum
temperature specification of 85°C.
16.Input and output parameters vary 1:1 with V
.
CC
17.All outputs loaded with 50 ꢀ to V −1.5 V for BGA package and V − 2 V for QFN package. V /V measured at V /V (Typical).
CC
CC
OH OL
IH IL
18.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
19.V cannot exceed V . |V − V
| < 2600 mV.
IH
CC
IH
THR
20.V always ≥ V . |V − V
| < 2600 mV.
IL
21.V
EE
IL
THR
is the voltage applied to one input when running in single−ended mode.
THR
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NBSG14
Table 8. AC CHARACTERISTICS for FCBGA−16
V
CC
= 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V
EE CC EE
−40°C
25°C
Typ
70°C
Typ
Min
Typ Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
f
Maximum Frequency
10.7
12
10.7
12
10.7
12
GHz
max
(See Figure 4) (Note 22)
t
t
,
Propagation Delay to
Output Differential
100
125
150
100
125
150
100
125
150
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 23)
Within−Device Skew (Note 24)
Device−to−Device Skew (Note 25)
2
6
25
10
15
50
2
6
25
10
15
50
2
6
25
10
15
50
SKEW
t
RMS Random Clock Jitter
ps
JITTER
0.2
1
0.2
10
1
0.2
1
(Figure 4) (Note 27)
Peak−to−Peak Data Dependent Jitter
(Note 28) < 10 Gb/s
f < 10 GHz
in
f
in
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 26)
75
20
2600
55
75
20
2600
55
75
20
2600 mV
INPP
t
r
t
f
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
Q, Q
30
30
30
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
22.Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 ꢀ to V − 1.5 V. Input edge rates 40 ps
CC
(20% − 80%).
23.See Figure 6. t
= |t
− t
PHL
| for a nominal 50% Differential Clock Input Waveform.
SKEW
PLH
24.Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
25.Device−to−device skew for identical transitions at identical V levels.
CC
26.V
(MAX) cannot exceed V − V (applicable only when V −V < 2600 mV).
INPP
CC EE CC EE
27.Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
31
28.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2 −1 data at 10 Gb/s.
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NBSG14
Table 9. AC CHARACTERISTICS for QFN−16
V
CC
= 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V
EE CC EE
−40°C
25°C
Typ
85°C
Typ
Min
Typ Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
f
Maximum Frequency
10.5
12
10.5
12
10.5
12
GHz
max
(See Figure 4) (Note 29)
t
t
,
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 30)
Within−Device Skew (Note 31)
Device−to−Device Skew (Note 32)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
SKEW
t
RMS Random Clock Jitter
ps
JITTER
0.2
1
0.2
10
1
0.2
1
(Figure 4) (Note 34)
Peak−to−Peak Data Dependent Jitter
(Note 35) < 10 Gb/s
f < 10 GHz
in
f
in
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 33)
75
15
2600
55
75
20
2600
55
75
20
2600 mV
INPP
t
r
t
f
Output Rise/Fall Times
(20% − 80%) @ 1 GHz
Q, Q
30
30
30
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
29.Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50 ꢀ to V − 2.0 V. Input edge rates 40 ps
CC
(20% − 80%)
30.See Figure 6. t
= |t
− t
PHL
| for a nominal 50% Differential Clock Input Waveform.
SKEW
PLH
31.Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
32.Device−to−device skew for identical transitions at identical V levels.
CC
33.V
(MAX) cannot exceed V − V (applicable only when V −V < 2600 mV).
INPP
CC EE CC EE
34.Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
31
35.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2 −1 data at 10 Gb/s.
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9
NBSG14
10
9
8
7
6
5
4
3
2
1
500
400
300
200
100
0
OUTPUT AMPLITUDE
OUTPUT P−P SPEC
(AMPLITUDE GUARANTEE)
RMS JITTER
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 4. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
X = 17 ps/DIV, Y = 53 mV/DIV
Figure 5. Eye Diagram at 10.8 Gbps
(VCC − VEE = 3.3 V @ 255C with Input Data Pattern of 2^31−1 PRBS.
Total Pk−Pk System Jitter Including Signal Generator is 18 ps.
This Data was taken by Acquiring 7000 Waveforms.)
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10
NBSG14
D/CLK
V
V
= = V (CLK) − V (CLK)
IH IL
INPP
D/CLK
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
t
PHL
PLH
Figure 6. AC Reference Measurement
Z = 50 ꢀ
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 ꢀ
o
50 ꢀ
50 ꢀ
V
TT
V
TT
= V − 2.0 V
CC
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
FCBGA−16
FCBGA−16
QFN−16
Shipping
NBSG14BA
100 Units / Tray (Contact Sales Representative)
100 / Tape & Reel
NBSG14BAR2
NBSG14MN
NBSG14MNG
123 Units / Rail
QFN−16
(Pb−Free)
123 Units / Rail
NBSG14MNR2
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
NBSG14MNR2G
QFN−16
(Pb−Free)
Board
Description
NBSG14BA Evaluation Board
NBSG14BAEVB
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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11
NBSG14
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
M
−Y−
E
K
M
MILLIMETERS
0.20
DIM MIN
MAX
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
A
A1
A2
b
1.40 MAX
0.25
0.35
3 X e
4
3
2
1
1.20 REF
0.30
0.50
A
D
4.00 BSC
3
B
E
4.00 BSC
1.00 BSC
0.50 BSC
e
16 X
b
C
D
S
M
M
0.15
0.08
Z X
Z
Y
S
VIEW M−M
5
0.15 Z
A2
A
−Z−
16 X
A1
0.10 Z
4
DETAIL K
ROTATED 90 CLOCKWISE
_
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12
NBSG14
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
A
B
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
PIN 1
LOCATION
MILLIMETERS
E
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
A3
b
D
0.20 REF
0.18
0.30
0.15
C
3.00 BSC
TOP VIEW
D2 1.65
1.85
E
3.00 BSC
0.15
C
E2 1.65
1.85
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
(A3)
0.10
0.08
C
C
A
SEATING
PLANE
16 X
SOLDERING FOOTPRINT*
SIDE VIEW
D2
A1
C
3.25
0.128
0.30
0.575
0.022
EXPOSED PAD
0.012
e
L
16X
EXPOSED PAD
5
8
NOTE 5
4
9
1.50
0.059
3.25
0.128
E2
e
K
16X
12
1
16
13
0.30
16X b
0.012
0.50
0.02
0.10 C A
B
BOTTOM VIEW
mm
inches
ǒ
Ǔ
0.05
C
NOTE 3
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NBSG14/D
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