NBSG16VSBAR2G [ONSEMI]
LINE TRANSCEIVER, PBGA16, 4 X 4 MM, PLASTIC, FCBGA-16;
| 型号： | NBSG16VSBAR2G |
| 厂家： | 
ONSEMI |
| 描述： | LINE TRANSCEIVER, PBGA16, 4 X 4 MM, PLASTIC, FCBGA-16 线路驱动器或接收器 驱动程序和接口 接口集成电路 |
| 文件： | 总14页 (文件大小：193K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NBSG16VS
2.5V/3.3VꢀSiGe Differential
Receiver/Driver with
Variable Output Swing
Description
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MARKING DIAGRAMS*
The NBSG16VS is a differential receiver/driver targeted for high
frequency applications that require variable output swing. The device
is functionally equivalent to the EP16VS device with much higher
bandwidth and lower EMI capabilities. This device may be used for
applications driving VCSEL lasers.
Inputs incorporate internal 50 ꢀ termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS,
CML, or LVDS. The output amplitude is varied by applying a voltage
SG
11
ALYW
FCBGA−16
BA SUFFIX
CASE 489
to the V
input pin. Outputs are variable swing ECL from 100 mV
CTRL
to 750 mV amplitude, optimized for operation from V − V
=
CC
EE
3.0 V to 3.465 V.
16
The V and V
pins are internally generated voltage supplies
1
BB
MM
available to this device only. The V is used as a reference voltage
BB
SG
16VS
ALYWG
G
for single−ended NECL or PECL inputs and the V
pin is used as a
MM
QFN−16
MN SUFFIX
CASE 485G
reference voltage for LVCMOS inputs. For single−ended input
operation, the unused complementary differential input is connected to
V
BB
or V
as a switching reference voltage. V or V
may also
MM
BB
MM
rebias AC coupled inputs. When used, decouple V and V
via a
BB
MM
0.01 ꢁ F capacitor and limit current sourcing or sinking to 0.5 mA.
A
L
= Assembly Location
= Wafer Lot
When not used, V and V
outputs should be left open.
BB
MM
Y
W
G
= Year
= Work Week
= Pb−Free Package
Features
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
(Note: Microdot may be in either location)
• 40 ps Typical Rise and Fall Times (V
• 120 ps Typical Propagation Delay (V
= V − 1 V)
CTRL
CC
= V − 1 V)
CTRL
CC
*For additional marking information, refer to
Application Note AND8002/D.
• Variable Swing PECL Output with Operating Range: V = 2.375 V to
CC
3.465 V with V = 0 V
EE
• Variable Swing NECL Output with NECL Inputs with
Operating Range: V = 0 V with V = −2.375 V to −3.465 V
ORDERING INFORMATION
CC
EE
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
• Output Level (100 mV to 750 mV Peak−to−Peak Output;
− V = 3.0 V to 3.465 V), Differential Output Only
V
CC
EE
• 50 ꢀ Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V EP Devices
• V and V
Reference Voltage Output
BB
MM
• Pb−Free Packages are Available
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 7
NBSG16VS/D
NBSG16VS
1
2
3
4
V
EE
V
BB
V
MM
V
EE
Exposed Pad (EP)
16
15
14
13
A
B
V
NC
V
V
EE
EE
CTRL
VTD
D
V
CC
1
2
3
4
12
11
10
9
D
D
VTD
VTD
V
Q
Q
CC
CC
MM
Q
Q
V
NBSG16VS
D
V
C
D
VTD
CC
V
EE
V
BB
V
V
EE
5
6
7
8
V
EE
NC V
V
CTRL EE
Figure 1. BGA−16 Pinout (Top View)
Figure 2. QFN−16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin
BGA
C2
QFN
Name
VTD
D
I/O
Description
1
2
−
Internal 50 ꢀ Termination Pin. See Table 2.
C1
ECL, CML, Inverted Differential Input. Internal 75 kꢀ to V and 36.5 kꢀ to V
.
EE
CC
LVCMOS,
LVDS,
LVTTL
Input
B1
B2
3
D
ECL, CML, Noninverted Differential Input. Internal 75 kꢀ to V
LVCMOS,
LVDS,
LVTTL
Input
.
EE
4
VTD
−
−
Internal 50 ꢀ Termination Pin. See Table 2.
A1,D1,A4,
D4
5,8,13,16
V
EE
Negative Supply Voltage
A2
A3
6
7
NC
−
No Connect
V
Output Amplitude Swing Control. Bypass Pin to V through 0.1 ꢁ F Capacitor.
CTRL
CC
B3,C3
B4
9,12
10
V
−
Positive Supply Voltage
CC
Q
RSECL
Output
Noninverted Differential Output. Typically Terminated with 50 ꢀ to
V
TT
= V − 2 V
CC
C4
11
Q
RSECL
Output
Inverted Differential Output. Typically Terminated with 50 ꢀ to V = V − 2 V
TT CC
D3
D2
14
15
−
V
−
−
−
LVCMOS Reference Voltage Output. (V − V )/2
CC EE
MM
V
ECL Reference Voltage Output
Exposed Pad. (Note 2)
BB
N/A
EP
1. The NC pin is electrically connected to the die and must be left open.
2. All V and V pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
CC
EE
bottom (see case drawing) must be attached to a heat−sinking conduit.
3. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage, and if no signal
is applied then the device will be susceptible to self−oscillation.
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2
NBSG16VS
+3.3 V
V
CC
+
V
CTRL
0.1 ꢁF
V
V
CTRL CC
R
VAR
V
CTRL
V
CC
V
MM
36.5
VTD
V
MM
VTD
36.5
Kꢀ
50
50
ꢀ
ꢀ
K
ꢀ
Q
50
50
ꢀ
ꢀ
D
D
Q OUT
Q OUT
Q
Q
D
D
Q OUT
Q OUT
Q
V
75
Kꢀ
75
Kꢀ
140
ꢀ
140 ꢀ
75
Kꢀ
75
50
ꢀ
50
ꢀ
BB
Kꢀ
VTD
V
BB
VTD
V
CC
− 2 V
V
EE
V
EE
Figure 3. Logic Diagram/
Voltage Source Implementation
Figure 4. Alternative Voltage Source Implementation
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS
CONNECTIONS
Connect VTD and VTD to V
CML
LVDS
CC
Connect VTD and VTD Together
AC−COUPLED
Bias VTD and VTD Inputs within
Common Mode Range (V
)
IHCMR
RSECL, PECL, NECL
LVTTL
Standard ECL Termination Techniques
An external voltage should be applied to the unused
complementary differential input. Nominal voltage is
1.5 V for LVTTL.
LVCMOS
V
MM
should be connected to the unused
complementary differential input.
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3
NBSG16VS
Table 3. ATTRIBUTES
Characteristics
Value
75 k
36.5 k
Internal Input Pulldown Resistor (D, D)
Internal Input Pullup Resistor (D)
ESD Protection
ꢀ
ꢀ
Human Body Model
> 2 kV
Machine Model
> 100 V
Moisture Sensitivity (Note 4)
Pb Pkg
Pb−Free Pkg
FCBGA−16
QFN−16
Level 3
Level 1
N/A
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
192
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
4. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
CC
V
EE
V
I
V
V
3.6
EE
Negative Power Supply
= 0 V
−3.6
V
CC
Positive Input
Negative Input
V
EE
V
CC
= 0 V
= 0 V
V v V
3.6
−3.6
V
V
I
I
CC
EE
V w V
V
INPP
Differential Input Voltage
|D − D|
V
CC
V
CC
− V w 2.8 V
2.8
|V − V
CC
V
V
EE
− V t 2.8 V
|
EE
EE
I
I
Output Current
Continuous
Surge
25
50
mA
mA
OUT
Input Current Through R (50 ꢀ Resistor)
Static
Surge
45
80
mA
mA
IN
T
I
I
V
V
Sink/Source
Sink/Source
1
1
mA
mA
°C
BB
BB
MM
MM
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
108
A
T
°C
stg
ꢂ
Thermal Resistance (Junction−to−Ambient) 0 lfpm
(Note 5)
16 FCBGA
16 FCBGA
16 QFN
°C/W
JA
500 lfpm
0 lfpm
500 lfpm
86
41.6
35.2
°C/W
°C/W
°C/W
16 QFN
ꢂ
Thermal Resistance (Junction−to−Case)
Wave Solder
2S2P (Note 5)
2S2P (Note 6)
16 FCBGA
16 QFN
5.0
4.0
°C/W
°C/W
JC
T
sol
Pb
Pb−Free
225
225
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
5. JEDEC standard 51−6 multilayer board − 2S2P (2 signal, 2 power).
6. JEDEC standards multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NBSG16VS
Table 5. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT V = 2.5 V; V = 0 V (Note 7)
CC
EE
−40°C
Typ
25°C
85°C
Typ
25
Min
18
Max
32
Min
18
Typ
25
Max
Min
18
Max
32
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Unit
mA
mV
mV
I
EE
25
32
V
OH
V
OL
1315
1440
1565
1305
1430
1555
1305
1430
1555
(Max Swing)
645
765
885
605
725
845
600
720
840
(V
CTRL
= V − 600 mV) 1090
1210
1330
1035
1155
1275
1010
1130
1250
CC
V
V
Input HIGH Voltage
(Single−Ended) (Notes 10 and 11)
V
V
−
V
V
V
−
V
V
V
−
V
CC
mV
mV
IH
THR
CC
CC
THR
CC
CC
THR
CC
+ 75 1000*
+ 75 1000*
+ 75 1000*
Input LOW Voltage
V
−
V
CC
−
V
THR
V
−
V
CC
−
V
THR
V
−
V
CC
−
V
THR
IL
IH
IH
IH
(Single−Ended) (Notes 10 and 12)
2500 1400* − 75
2500 1400* − 75
2500 1400* − 75
V
V
PECL Output Voltage Reference
1080
1.2
1140
1200
2.5
1080
1.2
1140
1200
2.5
1080
1.2
1140
1200
2.5
mV
V
BB
Input HIGH Voltage Common Mode
Range (Note 9)
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
mV
(V − V )/2 1100
1250
50
1400
55
1100
45
1250
50
1400
55
1100
45
1250
50
1400
55
CC
EE
R
TIN
Internal Input Termination Resistor
45
ꢀ
I
IH
I
IL
Input HIGH Current (@ V
)
30
100
50
30
100
50
30
100
50
ꢁ A
ꢁ A
IH
Input LOW Current (@ V )
25
25
25
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
7. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −0.965 V.
CC
EE
8. All loading with 50 ꢀ to V − 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10.V
is the voltage applied to the complementary input, typically V or V . V
= V
+ 75 mV. V
= V
− 75 mV.
THR
BB
MM THR(MIN)
IHCMR
THR(MAX)
IHCMR
11. V cannot exceed V
.
IH
CC
12.V always w V
.
IL
EE
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NBSG16VS
Table 6. DC CHARACTERISTICS, INPUT WITH VARIABLE PECL OUTPUT V = 3.3 V; V = 0 V (Note 18)
CC
EE
−40°C
Typ
25°C
85°C
Typ
27
Min
20
Max
34
Min
20
Typ
27
Max
Min
20
Max
34
Symbol
Characteristic
Negative Power Supply Current
Output HIGH Voltage (Note 13)
Output LOW Voltage (Note 13)
Unit
mA
mV
mV
I
EE
27
34
V
2095
2220
2345
2085
2210
2335
2075
2200
2325
OH
OL
V
(Max Swing) 1275
= V − 600 mV) 1750
1395
1870
1515
1990
1285
1730
1405
1850
1525
1970
1295
1715
1415
1835
1535
1955
(V
CTRL
CC
V
V
Input HIGH Voltage
(Single−Ended) (Notes 15 and 16)
V
V
−
V
V
V
−
V
V
V
−
V
CC
mV
mV
IH
THR
CC
CC
THR
CC
CC
THR
CC
+ 75 1000*
+ 75 1000*
+ 75 1000*
Input LOW Voltage
(Single−Ended) (Notes 15 and 17)
V
−
V
CC
−
V
THR
V
−
V
CC
−
V
THR
V
−
V
CC
−
V
THR
IL
IH
IH
IH
2500 1400* − 75
2500 1400* − 75
2500 1400* − 75
V
V
PECL Output Voltage Reference
1880
1.2
1940
2000
3.3
1880
1.2
1940
2000
3.3
1880
1.2
1940
2000
3.3
mV
V
BB
Input HIGH Voltage Common Mode
Range (Note 14)
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
mV
(V − V )/2 1500
1650
50
1800
55
1500
45
1650
50
1800
55
1500
45
1650
50
1800
55
CC
EE
R
TIN
Internal Input Termination Resistor
45
ꢀ
I
Input HIGH Current (@ V
)
30
100
50
30
100
50
30
100
50
ꢁ A
ꢁ A
IH
IL
IH
I
Input LOW Current (@ V )
25
25
25
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
13.All loading with 50 ꢀ to V − 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
15.V is the voltage applied to the complementary input, typically V or V . V
= V
+ 75 mV. V
= V
− 75 mV.
THR
BB
MM THR(MIN)
IHCMR
THR(MAX)
IHCMR
16.V cannot exceed V
.
IH
CC
17.V always w V
.
IL
EE
18.Input and output parameters vary 1:1 with V . V can vary +0.925 V to −0.165 V.
CC
EE
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NBSG16VS
Table 7. DC CHARACTERISTICS, NECL INPUT WITH VARIABLE NECL OUTPUT
V
CC
= 0 V; V = −3.465 V to −2.375 V (Note 19)
EE
−40°C
Typ
27
25°C
Typ
27
85°C
Typ
27
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
mA
mV
I
EE
Negative Power Supply Current
Output HIGH Voltage (Note 20)
20
34
20
34
20
34
V
OH
−1205 −1080
−1185 −1060
−955
−935
−1215 −1090 −965
−1195 −1070 −945
−1225 −1100
−1195 −1070
−975
−945
−3.465 V v V v −3.0 V
EE
−3.0 V t V v −2.375 V
EE
V
OL
Output LOW Voltage (Note 20)
−3.465 V v V v −3.0 V
mV
mV
EE
(Max Swing) −2000 −1910 −1820 −1990 −1900 −1810 −1980 −1890 −1800
= V − 600 mV) −1560 −1440 −1320 −1580 −1460 −1340 −1595 −1475 −1355
(V
CTRL
CC
−3.0 V t V v −2.375 V
EE
(Max Swing) −1855 −1620 −1290 −1895 −1705 −1425 −1900 −1730 −1470
= V − 600 mV) −1410 −1215 −1000 −1460 −1290 −1100 −1490 −1330 −1150
(V
CTRL
CC
V
V
Input HIGH Voltage
(Single−Ended) (Notes 22 and 23)
V
+ 75
V
1000*
−
V
V
+ 75
V
1000*
−
V
V
+ 75
V
1000*
−
V
CC
mV
mV
IH
THR
CC
CC
THR
CC
CC
THR
CC
Input LOW Voltage
V
−
V
CC
−
V
THR
V
−
V
CC
−
V
THR
V
−
V
CC
−
V
THR
IL
IH
IH
IH
(Single−Ended) (Notes 22 and 24)
2500
1400*
− 75
2500
1400*
− 75
2500
1400*
− 75
V
V
NECL Output Voltage Reference
−1420 −1360 −1300 −1420 −1360 −1300 −1420 −1360 −1300 mV
BB
Input HIGH Voltage Common Mode
Range (Note 21)
V
EE
+1.2
0.0
V
EE
+1.2
0.0
V +1.2
EE
0.0
V
IHCMR
(Differential Configuration)
V
MM
CMOS Output Voltage Reference
(Note 25)
V
− 150
V
MMT
V
+ 150
V
− 150
V
MMT
V
+ 150
V
− 150
V
MMT
V
+ 150
mV
MMT
MMT
MMT
MMT
MMT
MMT
R
Internal Input Termination Resistor
45
50
30
25
55
100
50
45
50
30
25
55
100
50
45
50
30
25
55
100
50
ꢀ
TIN
I
IH
I
IL
Input HIGH Current (@ V
)
ꢁ A
ꢁ A
IH
Input LOW Current (@ V )
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
*Typicals used for testing purposes.
19.Input and output parameters vary 1:1 with V
.
CC
20.All loading with 50 ꢀ to V − 2.0 V. V /V measured at V /V .
CC
OH OL
IH IL
21.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
22.V
is the voltage applied to the complementary input, typically V or V . V
= V
+ 75 mV. V
= V
− 75 mV.
THR
BB
MM THR(MIN)
IHCMR
THR(MAX)
IHCMR
23.V cannot exceed V
.
IH
CC
24.V always w V
.
IL
EE
25.V
typical = |V −V | / 2 + V = V
.
MM
CC
EE
EE
MMT
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NBSG16VS
Table 8. AC CHARACTERISTICS for FCBGA−16 V = 0 V; V = −3.465 V to −3.0 V or V = 3.0 V to 3.465 V; V = 0 V
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ Max
Min
Typ Max
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.7
12
10.7
12
10.7
12
GHz
max
(See Figure 8) (Note 26)
(Note 29)
(Note 29)
(Note 29)
t
t
,
Propagation Delay to Output Differen-
tial
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V − 2 V) D → Q, Q
100
100
125
120
145
140
100
100
125
120
145
140
100
100
125
120
145
140
CC
= V − 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 27)
RMS Random Clock Jitter
3
10
3
10
3
10
ps
ps
SKEW
JITTER
f
in
< 10 GHz
0.8
2
0.8
2
0.8
2
Peak−to−Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 28)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V − 2 V) Q, Q
30
30
45
40
55
50
30
30
45
40
55
50
30
30
45
40
55
50
CC
= V − 1 V) Q, Q
CC
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
26.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 ꢀ to V −2.0 V. Input edge rates 40 ps (20% − 80%).
CC
27.t
= |t
−t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
28.V
cannot exceed V − V (applicable only when V − V t 2600 mV).
INPP(MAX)
CC EE CC EE
29.Conditions include input amplitude of 500 mV and V
= V − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
CC
CTRL
Spec in Figure 8).
Table 9. AC CHARACTERISTICS for FCBGA−16 V = 0 V; −3.0 V tV v −2.375 V or 2.375 V v V t 3.0 V; V = 0 V
CC
EE
CC
EE
−40°C
Typ
25°C
Typ Max
85°C
Min
Max
Min
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10.7
12
10.7
12
10.7
12
GHz
max
(See Figure 9) (Note 30)
(Note 33)
(Note 33)
(Note 33)
t
t
,
Propagation Delay to Output Differen-
tial
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V − 2 V) D → Q, Q
100
100
125
120
145
140
100
100
125
120
145
140
100
100
125
120
145
140
CC
= V − 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 31)
3
10
3
10
3
10
ps
ps
SKEW
RMS Random Clock Jitter
f
JITTER
< 10 GHz
0.9
3
0.9
3
0.9
3
in
Peak−to−Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 32)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V − 2 V) Q, Q
25
22
50
45
70
60
25
22
50
45
70
60
25
22
50
45
70
60
CC
= V − 1 V) Q, Q
CC
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
30.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 ꢀ to V −2.0 V. Input edge rates 40 ps (20% − 80%).
CC
31.t
= |t
−t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
32.V
cannot exceed V − V (applicable only when V − V t 2600 mV).
INPP(MAX)
CC EE CC EE
33.Conditions include input amplitude of 500 mV and V
= V − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
CC
CTRL
Spec in Figure 9).
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8
NBSG16VS
Table 10. AC CHARACTERISTICS for QFN−16 V = 0 V; V = −3.465 V to −3.0 V or V = 3.0 V to 3.465 V; V = 0 V
CC
EE
CC
EE
−40°C
Typ
12
25°C
85°C
Min
Max
Min
Typ Max
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10
10
(Note 37)
12
10
(Note 37)
12
GHz
max
(See Figure 8) (Note 34)
(Note 37)
t
t
,
Propagation Delay to
Output Differential
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V − 2 V) D → Q, Q
100
100
140
135
180
180
100
100
140
135
180
180
100
80
140
135
180
220
CC
= V − 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 35)
3
20
3
15
3
10
ps
ps
SKEW
RMS Random Clock Jitter
JITTER
f
< 10 GHz
0.5
2
0.5
2
0.5
2
in
Peak−to−Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 36)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V − 2 V) Q, Q
30
30
45
40
55
50
30
30
45
40
55
50
30
30
45
40
55
50
CC
= V − 1 V) Q, Q
CC
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
34.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 ꢀ to V −2.0 V. Input edge rates 40 ps (20% − 80%).
CC
35.t
= |t
−t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
36.V
cannot exceed V − V (applicable only when V − V t 2600 mV).
INPP(MAX)
CC EE CC EE
37.Conditions include input amplitude of 500 mV and V
= V − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
CC
CTRL
Spec in Figure 8).
Table 11. AC CHARACTERISTICS for QFN−16 V = 0 V; −3.0 V tV v −2.375 V or 2.375 V v V t 3.0 V; V = 0 V
CC
EE
CC
EE
−40°C
Typ
25°C
Typ Max
85°C
Min
Max
Min
Min
Typ Max
Symbol
Characteristic
Maximum Frequency
Unit
f
10
12
10
12
10
12
GHz
max
(See Figure 9) (Note 38)
(Note 41)
(Note 41)
(Note 41)
t
t
,
Propagation Delay to
Output Differential
ps
PLH
PHL
(V
CTRL
(V
CTRL
= V − 2 V) D → Q, Q
100
100
140
135
180
180
100
100
140
135
180
180
80
100
140
135
180
220
CC
= V − 1 V) D → Q, Q
CC
t
t
Duty Cycle Skew (Note 39)
3
20
3
15
3
10
ps
ps
SKEW
RMS Random Clock Jitter
f
JITTER
< 10 GHz
0.5
3
0.5
3
0.5
3
in
Peak−to−Peak Data Dependent Jitter
< 10 Gb/s
f
in
TBD
TBD
TBD
V
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 40)
75
2600
75
2600
75
2600 mV
ps
INPP
t
r
t
f
Output Rise/Fall Times (20% − 80%)
@ 1 GHz
(V
CTRL
(V
CTRL
= V − 2 V) Q, Q
25
22
50
45
70
60
25
22
50
45
70
60
25
22
50
45
70
60
CC
= V − 1 V) Q, Q
CC
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
38.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 ꢀ to V −2.0 V. Input edge rates 40 ps (20% − 80%).
CC
39.t
= |t
−t
| for a nominal 50% differential clock input waveform. See Figure 10.
SKEW
PLH PHL
40.V
cannot exceed V − V (applicable only when V − V t 2600 mV).
INPP(MAX)
CC EE CC EE
41.Conditions include input amplitude of 500 mV and V
= V − 2 V. Minimum output amplitude guarantee of 100 mV (see Output P−P
CC
CTRL
Spec in Figure 9).
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9
NBSG16VS
100
90
80
70
60
50
40
30
20
10
0
V
CC
− 0.0
V
CC
− 0.5
V
CC
− 1.0
V
CC
− 1.5
V
CC
− 2.0
V
CTRL
(V)
Figure 5. Output Amplitude % vs. VCTRL (pin #A3)
V
OH
AMPLITUDE DECREASES
MAX. AMPLITUDE REGION
MIN. AMPLITUDE REGION
V
OL
2.375 V v V − V < 3.0 V
CC
EE
3.0 V v V − V v 3.465 V
CC
EE
V
CC
− 1.3
V
CC
− 0.0
V
CC
− 0.5
V
CC
− 1.0
V
CC
− 1.5
V
CC
− 2.0
V
CTRL
(V)
Figure 6. Output Amplitude vs. VCTRL (pin #A3)
3.40
3.20
3.00
2.80
2.60
V
CTRL
2.40
2.20
2.00
1.80
Q/Q
1.60
0
2
4
6
8
10
12
14
16
18
20
TIME (ns)
Figure 7. Output Response Under Amplitude Modulation of VCTRL
(Conditions Include VCC − VEE = 3.3 V at 255C, fIN (VCTRL) = 200 MHz, and fIN (D, D) = 2 GHz)
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10
NBSG16VS
900
800
700
600
500
400
300
200
100
9
8
7
6
5
4
3
2
1
V
= V − 2 V
CC
CTRL
V
CTRL
= V − 1 V
CC
V
CTRL
= V − 0 V
CC
OUTPUT P−P SPEC
(AMPLITUDE GUARANTEE)
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 8. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
800
9
8
7
V
CTRL
= V − 2 V
CC
700
600
500
400
V
CTRL
= V − 1 V
CC
6
5
4
3
2
1
V
CTRL
= V − 0 V
CC
OUTPUT P−P SPEC
(AMPLITUDE GUARANTEE)
300
200
100
RMS JITTER
0
0
1
2
3
4
5
6
7
8
9
10
11
12
INPUT FREQUENCY (GHz)
Figure 9. Output Voltage Amplitude (VOUTPP) / RMS Jitter vs.
Input Frequency (fin) at Ambient Temperature (Typical)
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
= V (Q) − V (Q)
OUTPP
OH
OL
Q
t
PHL
t
PLH
Figure 10. AC Reference Measurement
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11
NBSG16VS
Z = 50
ꢀ
ꢀ
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50
o
50
ꢀ
50 ꢀ
V
TT
V
TT
= V − 2.0 V
CC
Figure 11. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
FCBGA−16
FCBGA−16
QFN−16
Shipping
NBSG16VSBA
100 Units / Tray (Contact Sales Representative)
100 / Tape & Reel
NBSG16VSBAR2
NBSG16VSMN
NBSG16VSMNG
123 Units / Rail
QFN−16
(Pb−Free)
123 Units / Rail
NBSG16VSMNR2
NBSG16VSMNR2G
QFN−16
3000 / Tape & Reel
3000 / Tape & Reel
QFN−16
(Pb−Free)
Board
NBSG16VSBAEVB
Description
NBSG16VSBA Evaluation Board
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
NBSG16VS
PACKAGE DIMENSIONS
FCBGA−16
BA SUFFIX
PLASTIC 4X4 (mm) BGA FLIP CHIP PACKAGE
CASE 489−01
ISSUE O
LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA
−X−
D
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE MAXIMUM
SOLDER BALL DIAMETER, PARALLEL TO DATUM
PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY THE
SPHERICAL CROWNS OF THE SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE
ANY EFFECT OF MARK ON TOP SURFACE OF
PACKAGE.
M
−Y−
E
K
M
MILLIMETERS
0.20
DIM MIN
MAX
FEDUCIAL FOR PIN A1
IDENTIFICATION IN THIS AREA
A
A1
A2
b
1.40 MAX
0.25
0.35
3 X e
4
3
2
1
1.20 REF
0.30
0.50
A
D
4.00 BSC
3
B
E
4.00 BSC
1.00 BSC
0.50 BSC
e
16 X
b
C
D
S
M
M
0.15
0.08
Z X
Z
Y
S
VIEW M−M
5
0.15 Z
A2
A
−Z−
16 X
A1
0.10 Z
4
DETAIL K
ROTATED 90 CLOCKWISE
_
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13
NBSG16VS
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
B
PIN 1
LOCATION
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
A3
b
D
0.20 REF
TOP VIEW
0.18
0.30
0.15
C
3.00 BSC
D2 1.65
1.85
E
3.00 BSC
(A3)
E2 1.65
1.85
0.10
0.08
C
C
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
A
SEATING
PLANE
16 X
SOLDERING FOOTPRINT*
SIDE VIEW
D2
A1
C
3.25
0.128
0.30
0.575
0.022
EXPOSED PAD
e
L
16X
0.012
EXPOSED PAD
5
8
NOTE 5
4
9
E2
e
1.50
0.059
3.25
0.128
K
16X
12
1
16
13
16X b
0.30
0.012
0.10 C A
B
0.50
0.02
BOTTOM VIEW
0.05
C
NOTE 3
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and solderin
details, please download the ON Semiconductor Soldering an
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
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Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NBSG16VS/D
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