NC7SZ175P6X-L22347 [ONSEMI]
带异步清零功能的TinyLogic UHS D型触发器;
| 型号： | NC7SZ175P6X-L22347 |
| 厂家： | 
ONSEMI |
| 描述： | 带异步清零功能的TinyLogic UHS D型触发器 触发器 |
| 文件： | 总10页 (文件大小：295K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
TinyLogic UHS D-Type
Flip-Flop with
Asynchronous Clear
MARKING
DIAGRAMS
C4KK
XYZ
SIP6 1.45x1.0
CASE 127EB
NC7SZ175
Pin 1
Description
6
1
The NC7SZ175 is a single positive edge−triggered D−type CMOS
Flip−Flop with Asynchronous Clear from onsemi’s Ultra High Speed
Series of TinyLogic in the space saving SC70 6−lead package. The
device is fabricated with advanced CMOS technology to achieve ultra
high speed with high output drive while maintaining low static power
dissipation over a very broad V operating range. The device is
specified to operate over the 1.65 V to 5.5 V V range. The inputs
and output are high impedance when V
voltages up to 5.5 V independent of V
single flip−flop will store the state of the D input that meets the setup
and hold time requirements on the LOW−to−HIGH Clock (CP)
transition. A LOW input to Clear sets the Q output to LOW level. The
Clear input is independent of clock.
Z75MG
SC−88
CASE 419B−02
G
C4, Z75
= Specific Device Code
CC
KK
XY
Z
M
G
= 2−Digit Lot Run Traceability Code
= 2−Digit Date Code Format
= Assembly Plant Code
= Date Code*
CC
is 0 V. Inputs tolerate
operating voltage. This
CC
CC
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
Features
• Space Saving SC−88 6−Lead Package
• Ultra Small MicroPak™ Leadless Package
• Ultra High Speed: t = 2.6 ns Typ into 50 pF at 5 V V
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
PD
CC
• High Output Drive: 24 mA at 3 V V
CC
• Broad V Operating Range: 1.65 V to 5.5 V
CC
• Matches the Performance of LCX when Operated at 3.3 V V
• Power Down High Impedance Inputs / Output
CC
• Overvoltage Tolerant Inputs Facilitate 5 V to 3 V Translation
• Proprietary Noise / EMI Reduction Circuitry Implemented
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
IEEC / IEC
C
CP
D
Q
Figure 1. Logic Symbol
© Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
June, 2022 − Rev. 6
NC7SZ175/D
NC7SZ175
Connection Diagrams
CP
GND
D
1
2
3
CP
6
5
4
C
CP 1
GND 2
D 3
6 C
5 V
C
Q
V
CC
D
CC
Q
4 Q
Figure 2. SC70 (Top View)
Figure 4. MicroPak (Top Through View)
(Top View)
AAA
Pin One
AAA represents Product Code Top Mark − see ordering code.
NOTE: Orientation of Top Mark determines Pin One location.
Read the Top Product Code Mark left to right, Pin One
is the lower left pin (see diagram).
Figure 3. Pin 1 Orientation
PIN DESCRIPTIONS
FUNCTION TABLE
Pin Name
Description
Data Input
Inputs
Output
D
CP
C
CP
D
L
C
H
H
H
L
Q
L
Clock Pulse Input
Clear Input
H
X
X
H
Q
Flip−Flop Output
Qn
L
X
H = HIGH Logic Level
L = LOW Logic Level
Qn = No Change in Data
X = Immaterial
www.onsemi.com
2
NC7SZ175
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.5
−0.5
−0.5
−
Max
+6.5
+6.5
+6.5
−50
−50
50
Unit
V
V
CC
Supply Voltage
V
IN
DC Input Voltage
V
V
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
V
OUT
I
V
V
< 0 V
mA
mA
mA
mA
°C
IK
IN
I
< 0 V
−
OK
OUT
I
DC Output Source / Sink Current
−
OUT
I
/ I
DC V / GND Current
−
50
CC GND
CC
T
STG
Storage Temperature Range
−65
−
+150
150
260
332
812
T
Junction Temperature under Bias
°C
J
L
T
Junction Lead Temperature (Soldering, 10 Seconds)
−
°C
P
D
Power Dissipation in Still Air
SC−88
−
mW
MicroPak−6
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage Operating
Supply Voltage Data Retention
Input Voltage
Conditions
Min
1.65
1.5
0
Max
5.5
5.5
5.5
Unit
V
CC
V
V
IN
V
V
V
OUT
Output Voltage
0
V
CC
t , t
Input Rise and Fall Time
V
CC
V
CC
V
CC
= 1.8 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
0
20
ns/V
r
f
0
10
5
= 5.5 V 0.5 V
0
T
Operating Temperature
Thermal Resistance
−40
−
+85
377
154
°C
A
q
SC−88
°C/W
JA
MicroPak−6
−
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Unused inputs must be held HIGH or LOW. They may not float.
www.onsemi.com
3
NC7SZ175
DC ELECTICAL CHARACTERISTICS
T
A
= +25°C
T = −40 to +85°C
A
Min
0.65 V
Typ
−
Max
−
Min
Max
−
Symbol
Parameter
V
(V)
Conditions
Unit
CC
V
IH
HIGH Level Input
Control Voltage
1.65 to 1.95
2.3 to 5.5
1.65 to 1.95
2.3 to 5.5
1.65
1.8
0.65 V
V
CC
CC
CC
0.7 V
−
−
0.7 V
−
CC
V
IL
LOW Level Input
Control Voltage
−
−
−
0.35 V
−
−
0.35 V
V
V
CC
CC
−
0.3 V
0.3 V
CC
CC
V
OH
HIGH Level Control
Output Voltage
V
= V
I
= −100 mA
1.55
1.7
2.2
2.9
4.4
1.24
1.9
2.4
2.3
3.8
−
1.65
1.8
−
−
−
−
−
−
−
−
−
−
1.55
1.7
2.2
2.9
4.4
1.29
1.9
2.4
2.3
3.8
−
−
−
−
−
−
−
−
−
−
−
IN
IH
OH
or V
IL
2.3
2.3
3.0
3.0
4.5
4.5
1.65
2.3
I
I
I
I
I
I
= −4 mA
= −8 mA
= −16 mA
= −24 mA
= −32 mA
= 100 mA
1.52
2.15
2.8
OH
OH
OH
OH
OH
OL
3.0
3.0
2.68
4.2
4.5
V
OL
LOW Level Control
Output Voltage
1.65
1.8
V
IN
= V
IH
0.0
0.1
0.1
0.1
0.1
V
or V
IL
−
0.0
−
2.3
−
0.0
0.1
−
0.1
3.0
−
0.0
0.1
−
0.1
4.5
−
0.0
0.1
−
0.1
1.65
2.3
I
I
I
I
I
= 4 mA
−
0.08
0.10
0.15
0.22
0.22
−
0.24
0.3
−
0.24
0.3
OL
OL
OL
OL
OL
= 8 mA
−
−
3.0
= 16 mA
= 24 mA
= 32 mA
−
0.4
−
0.4
3.0
−
0.55
0.55
0.1
−
0.55
0.55
1.0
4.5
−
−
I
Input Leakage
Current
1.65 to 5.5 0 ≤ V ≤ 5.5 V
−
−
mA
mA
mA
IN
IN
I
Power Off Leakage
Current
0.0
V
or V = 5.5 V
OUT
−
−
−
−
1.0
1.0
−
−
10
OFF
IN
IN
I
Quiescent Supply
Current
1.65 to 5.5
V
= 5.5 V, GND
10.0
CC
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4
NC7SZ175
AC ELECTRICAL CHARACTERISTICS
T
A
= +25°C
Typ
−
T = −40 to +85°C
A
Min
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Max
−
Min
100
Max
−
Unit
Symbol
Parameter
V
(V)
Conditions
CC
f
Maximum Clock Frequency
(Figures 5, 8)
1.65
1.8
C = 50 pF,
MHz
MAX
L
R = 500 W
L
−
−
100
125
150
175
−
−
2.5 0.2
3.3 0.3
5.0 0.5
1.65
−
−
−
−
−
−
−
−
−
t
, t
Propagation Delay CP to Q
(Figures 5, 7)
C = 15 pF,
9.8
6.5
3.8
2.8
2.2
3.4
2.6
9.8
6.5
3.8
2.8
2.2
3.4
2.7
−
15.0
10.0
6.5
4.5
3.5
5.5
4.0
13.5
9.0
6.0
4.3
3.2
5.3
4.0
−
16.5
11.0
7.0
5.0
3.8
6.2
4.7
15.0
10.0
6.4
4.6
3.5
5.8
4.5
−
ns
PLH PHL
L
R = 1 MW
L
1.8
−
2.5 0.2
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
1.65
−
−
−
C = 50 pF,
−
L
R = 500 W
L
−
t
Propagation Delay C to Q
(Figures 5, 7)
C = 15 pF,
−
ns
PHL
L
R = 1 MW
L
1.8
−
2.5 0.2
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
2.5 0.2
3.3 0.3
5.0 0.5
2.5 0.2
3.3 0.3
5.0 0.5
2.5 0.2
3.3 0.3
5.0 0.5
2.5 0.2
3.3 0.3
5.0 0.5
2.5 0.2
3.3 0.3
5.0 0.5
−
−
−
C = 50 pF,
−
L
R = 500 W
L
−
t
S
Setup Time, CP to D
(Figures 5, 8)
C = 50 pF,
2.5
2.0
1.5
1.5
1.5
1.5
3.0
2.8
2.5
3.0
2.8
2.5
1.0
1.0
1.0
ns
ns
ns
ns
ns
L
R = 500 W
L
−
−
−
−
−
−
t
H
Hold Time, CP to D
(Figures 5, 8)
C = 50 pF,
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
L
R = 500 W
L
−
−
−
−
−
−
t
W
Pulse Width, CP
(Figures 5, 8)
C = 50 pF,
−
−
−
L
R = 500 W
L
−
−
−
−
−
−
Pulse Width, C
(Figures 5, 8)
Clock HIGH
or LOW
−
−
−
−
−
−
C = 50 pF,
L
R = 500 W
L
−
−
−
t
Recovery Time, C to CP
(Figures 5, 8)
C = 50 pF,
−
−
−
rec
L
R = 500 W
L
−
−
−
−
−
−
www.onsemi.com
5
NC7SZ175
CAPACITANCE (T = +25°C, f = 1 MHz)
A
Symbol
Parameter
Input Capacitance
Condition
Typ
3
Max
−
Units
pF
C
V
V
= Open, V = 0 V or V
IN
CC
IN
CC
CC
C
Output Capacitance
= 3.3 V, V = 0 V or V
4
−
pF
OUT
CC
IN
C
Power Dissipation Capacitance
(Note 2)
V
CC
V
CC
= 3.3 V
= 5.0 V
10
12
−
−
pF
PD
2. C is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I
) at
PD
CCD
no output loading and operating at 50% duty cycle. (See Figure 6)
C
is related to I
dynamic operating current by the expression: I
= (C ) (V ) (f ) + (I static).
CCD PD CC IN CC
PD
CCD
AC Loading and Waveforms
V
CC
A
V
CC
CP Input
D Input
C Input
CP
D
Q
OUTPUT
Q Output
C
C
R
L
L
CP Input = AC Waveform; t = t = 1.8 ns;
r
f
C includes load and stray capacitance
CP Input PRR = 10 MHz; Duty Cycle = 50%
D Input PRR = 5 MHz; Duty Cycle = 50%.
L
Input PRR = 1.0 MHz, t = 500 ns.
W
Figure 5. AC Test Circuit
Figure 6. ICCD Test Circuit
Figure 7. AC Waveforms
Figure 8. AC Waveforms
DEVICE ORDERING INFORMATION
†
Device
Top Mark
Z75
Packages
Shipping
NC7SZ175P6X
6−Lead SC70, EIAJ SC88, 1.25 mm Wide
6−Lead SC70, EIAJ SC88, 1.25 mm Wide
6−Lead MicroPak, 1.00 mm Wide
6−Lead MicroPak, 1.00 mm Wide
3000 / Tape & Reel
3000 / Tape & Reel
5000 / Tape & Reel
5000 / Tape & Reel
NC7SZ175P6X−L22347
NC7SZ175L6X
Z75
C4
NC7SZ175L6X−L22175
C4
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MicroPak is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
www.onsemi.com
6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SIP6 1.45X1.0
CASE 127EB
ISSUE O
DATE 31 AUG 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13590G
SIP6 1.45X1.0
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
DATE 11 DEC 2012
SCALE 2:1
2X
aaa H
D
NOTES:
D
H
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
D
GAGE
PLANE
6
1
5
2
4
3
L
L2
E1
E
DETAIL A
aaa
C
2X
2X 3 TIPS
bbb H
D
e
MILLIMETERS
DIM MIN NOM MAX
−−−
INCHES
MIN
−−−
NOM MAX
−−− 0.043
−−− 0.004
6X b
B
TOP VIEW
A
−−−
−−−
1.10
A1 0.00
A2 0.70
0.10 0.000
M
ddd
C A-B D
0.90
0.20
0.15
2.00
2.10
1.25
0.65 BSC
0.36
1.00 0.027 0.035 0.039
0.25 0.006 0.008 0.010
0.22 0.003 0.006 0.009
2.20 0.070 0.078 0.086
2.20 0.078 0.082 0.086
1.35 0.045 0.049 0.053
0.026 BSC
b
C
D
E
0.15
0.08
1.80
2.00
A2
DETAIL A
A
E1 1.15
e
L
0.26
0.46 0.010 0.014 0.018
0.006 BSC
L2
0.15 BSC
0.15
aaa
bbb
ccc
ddd
0.006
0.012
0.004
0.004
0.30
0.10
0.10
6X
ccc C
A1
SEATING
PLANE
c
C
SIDE VIEW
END VIEW
GENERIC
MARKING DIAGRAM*
RECOMMENDED
SOLDERING FOOTPRINT*
6
6X
0.30
XXXMG
6X
0.66
G
1
2.50
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
0.65
(Note: Microdot may be in either location)
PITCH
*Date Code orientation and/or position may
vary depending upon manufacturing location.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
STYLE 5:
STYLE 6:
PIN 1. ANODE 2
2. N/C
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
PIN 1. ANODE
2. ANODE
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
3. COLLECTOR
3. CATHODE 1
4. ANODE 1
5. N/C
4. EMITTER
5. BASE
6. COLLECTOR 2
6. ANODE
6. CATHODE
6. CATHODE 2
STYLE 7:
STYLE 8:
CANCELLED
STYLE 9:
STYLE 10:
STYLE 11:
STYLE 12:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
4. SOURCE 1
5. DRAIN 1
6. GATE 2
4. DRAIN 1
5. DRAIN 2
6. GATE 2
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
5. BASE 2
6. COLLECTOR 2
STYLE 13:
PIN 1. ANODE
2. N/C
STYLE 14:
PIN 1. VREF
2. GND
STYLE 15:
STYLE 16:
STYLE 17:
STYLE 18:
PIN 1. VIN1
2. VCC
PIN 1. ANODE 1
2. ANODE 2
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
3. COLLECTOR
4. EMITTER
5. BASE
3. GND
3. ANODE 3
3. VOUT2
4. VIN2
5. GND
6. VOUT1
4. IOUT
5. VEN
6. VCC
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
5. EMITTER 1
6. COLLECTOR 1
5. EMITTER 2
6. COLLECTOR 1
6. CATHODE
STYLE 19:
PIN 1. I OUT
2. GND
STYLE 20:
STYLE 21:
PIN 1. ANODE 1
2. N/C
STYLE 22:
PIN 1. D1 (i)
2. GND
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
STYLE 24:
PIN 1. CATHODE
2. ANODE
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
3. GND
3. ANODE 2
4. CATHODE 2
5. N/C
3. D2 (i)
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
4. V CC
4. EMITTER
5. COLLECTOR
6. COLLECTOR
4. D2 (c)
5. VBUS
6. D1 (c)
4. N/C
5. V EN
5. CH2
6. N/C
6. V REF
6. CATHODE 1
STYLE 30:
STYLE 25:
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
STYLE 29:
PIN 1. ANODE
2. ANODE
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
3. DRAIN 2
4. SOURCE 2
5. GATE 2
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
4. SOURCE
5. DRAIN
6. DRAIN
5. EMITTER
6. COLLECTOR 1
6. DRAIN 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
PAGE 2 OF 2
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