NCD57540DWKR2G [ONSEMI]
Isolated Dual-Channel IGBT Gate Driver with >8mm Creepage and Clearance;
| 型号： | NCD57540DWKR2G |
| 厂家： | 
ONSEMI |
| 描述： | Isolated Dual-Channel IGBT Gate Driver with >8mm Creepage and Clearance 栅 双极性晶体管 |
| 文件： | 总23页 (文件大小：816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
Isolated Dual Channel IGBT
Gate Driver
1
NCD57530, NCV57530,
NCD57540, NCV57540
SOIC−16 WB
CASE 752AJ
MARKING DIAGRAMS
NCx575y0 are high−current two channel isolated IGBT gate drivers
with 5 kV internal galvanic isolation from input to each output and
rms
CASE 752AJ
16
functional isolation between the two output channels. The device
accepts 3.3 V to 20 V bias voltage and signal levels on the input side
and up to 32 V bias voltage on the output side. The device accepts
complementary inputs and offers separate pins for Disable
(NCx57540) or Enable (NCx57530) and Dead Time control for
system design convenience. Drivers are available in CASE 752AJ
SOIC−16 wide body package with increased insulation between
channels (less pin 12 & 13) .
575y0
AWLYYWWG
G
1
575y0
= Specific Device Code
= 3 or 4
y
A
Features
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• High Peak Output Current ( 6.5 A)
• Configurable as a Dual Low−Side or Dual High−Side or Half−Bridge
Driver
WL
YY, Y
WW
G
• Programmable Overlap or Dead Time control
(See page 21)
• Disable Pin to Turn Off Outputs for Power Sequencing (NCx57540)
• Enable Pin for Independent Driver Control (NCx57530)
• IGBT Gate Clamping during Short Circuit
PIN CONNECTIONS
• Short Propagation Delays with Accurate Matching
• Tight UVLO Thresholds on all Power Supplies
• 3.3 V, 5 V, and 15 V Logic Input
INA
INB
V
DDA
OUTA
GNDA
V
DDI
• 5 kV Galvanic Isolation from Input to each Output
rms
GND
and 1.5 kV Differential Voltage between Output Channels
rms
DIS or EN*
DT
• 1200 V Working Voltage (per VDE0884−11 Requirements)
• High Common Mode Transient Immunity
V
DDB
• Case 752AJ for Improved Insulation Between Output Channels
NC
OUTB
GNDB
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
V
DDI
NCx575y0
x = D or V
y = 3 or 4
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
Compliant
* depends on variant
Typical Applications
• EV Chargers
ORDERING INFORMATION
• Motor Control
See detailed ordering and shipping information on page 21 of
this data sheet.
• Uninterruptible Power Supplies (UPS)
• Industrial Power Supplies
• Solar Inverters
• Automotive Applications
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
June, 2022 − Rev. 0
NCD57540/D
NCD57530, NCV57530, NCD57540, NCV57540
VDDI
VDDI
VDDA
OUTA
GNDA
UVLOI
UVLOA
RESET
RESET
CONTROL
INA
CONTROL
DT
NC
NC
VDDI
Functional Isolation
Deadtime
and
Interlock
EN
VDDB
OUTB
GNDB
UVLOB
RESET
CONTROL
RESET
CONTROL
INB
GNDI
NCx57530
VDDI
VDDI
VDDA
OUTA
GNDA
UVLOI
UVLOA
RESET
CONTROL
INA
RESET
CONTROL
DT
NC
NC
Functional Isolation
Deadtime
and
Interlock
DIS
VDDB
OUTB
GNDB
UVLOB
RESET
CONTROL
RESET
CONTROL
INB
GNDI
NCx57540
Figure 1. Simplified Block Diagram
www.onsemi.com
2
NCD57530, NCV57530, NCD57540, NCV57540
+V2
INA
INB
VDDA
OUTA
V1
VDDI
VDDI
GNDA
GND2
+V3
Functional
Isolation
GNDI
EN
VDDB
GND1
OUTB
DT
GNDB
GND3
NCx57530
+V2
INA
INB
VDDA
OUTA
V1
VDDI
VDDI
GNDA
GND2
+V3
Functional
Isolation
GNDI
DIS
DT
VDDB
GND1
OUTB
GNDB
GND3
NCx57540
Figure 2. Typical Application, High and Low Side IGBT Gate Drive (Dead Time added)
www.onsemi.com
3
NCD57530, NCV57530, NCD57540, NCV57540
+V2
INA
INB
VDDA
OUTA
V1
VDDI
VDDI
GNDA
GND2
+V3
Functional
Isolation
GNDI
EN
VDDB
GND1
OUTB
DT
GNDB
GND3
NCx57530
+V2
INA
INB
VDDA
OUTA
V1
VDDI
VDDI
GNDA
GND2
+V3
Functional
Isolation
GNDI
DIS
DT
VDDB
GND1
OUTB
GNDB
GND3
NCx57540
Figure 3. Typical Application, Two Channels IGBT Gate Drive (no added Dead Time)
www.onsemi.com
4
NCD57530, NCV57530, NCD57540, NCV57540
Table 1. FUNCTION DESCRIPTION
Pin
Name
No.
I/O
Description
INA
1
Input
A non-inverting gate driver input that defines OUTA. It has an equivalent pull−down resistor of 125 kꢀ to
ensure that output is low in the absence of an input signal.
A positive or negative going pulse with pulse width longer than maximum value of t
before OUTA reacts.
is required at INA
MIN2
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
.
the same as for V
= 5 V. Maximum voltage on this pin is V
DDI
DDI
INB
2
Input
A non−inverting gate driver input that defines OUTB. It has an equivalent pull−down resistor of 125 kꢀ to
ensure that output is low in the absence of an input signal.
A positive or negative going pulse with pulse width longer than maximum value of t
before OUTB reacts.
is required at INB
MIN2
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
.
the same as for V
= 5 V. Maximum voltage on this pin is V
DDI
DDI
V
DDI
3, 8
Power Low voltage side power supply. A good quality bypassing capacitor is required from this pin to GND and
should be placed close to the pins for best results.
The under voltage lockout (UVLOI) circuit enables the device to operate at power on when a typical
supply voltage higher than V
is present.
−
−
UVLOI OUT ON
Please see Figure 7 and 8 for more details.
GNDI
DIS
4
5
Power
Input
Low voltage side ground.
A high level on disable pin turns both OUTA and OUTB low simultaneously regardless of the states of
INA, INB and DT. Minimum pulse width filter and propagation delays apply. It has an equivalent
pull−down resistor of 125 kꢀ to ensure that OUTA and OUTB react to INA, INB and DT in the absence
of an input signal.
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay the
DDI
DDI
DDI
same as for V
= 5 V. Maximum voltage on this pin is V
.
DDI
DDI
EN
DT
5
6
Input
Input
Enable input allows additional gating of OUT, and can be used when the driver output needs to be turned
off independent of the Microcontroller input. A low level on enable pin turns both OUTA and OUTB low
simultaneously regardless of the states of INA, INB and DT.
It has an equivalent pull−up resistor of 125 kꢀ to ensure that OUTA and OUTB react to INA, INB and DT
in the absence of an input signal.
The input logic levels scale with V
up to V
= 5 V. With V
above 5 V the input logic levels stay
DDI
DDI
DDI
the same as for V
= 5 V. Maximum voltage on this pin is V
.
DDI
DDI
A deadtime pin is used to configure the two outputs sequence. The deadtime (t ) and interlocking logic
DT
between INA and INB is defined by the value of the external resistor (R ) connected between DT pin
DT
and GNDI. The deadtime can be estimated as t (ns) ≈ 10 x R (kꢀ). If DT pin is pulled up to VDDI
DT
DT
for disabling the deadtime and interlocking logic the OUTA and OUTB can be high simultaneously.
Minimum deadtime will be observed between OUTA and OUTB when DT pin is left floating.
Allowed resistance between this pin and GNDI is in range of 5 to 500 kꢀ.
Maximum voltage on this pin is V
.
DDI
Corresponding waveforms are on Figure 4.
GNDB
OUTB
9
Power Ground for channel B.
10
Output Output of channel B on the high voltage side. It has galvanic isolation from low voltage side and from
channel A. OUTB provides the appropriate drive voltage and source/sink current to the IGBT gate.
OUTB is actively pulled low during startup, when DIS is high and under UVLOB, UVLOI condition.
There is interlocking logic that prevents OUTA and OUTB cross conduction when DT pin is not connect-
ed to V
.
DDI
V
DDB
11
Power High voltage side power supply for channel B. A good quality bypassing capacitor is required from this
pin to GNDB and should be placed close to the pins for best results.
The under voltage lockout (UVLOB) circuit enables the device to operate at power on when a typical
supply voltage higher than V
is present.
−
−
UVLOB OUT ON
Please see Figure 9 and 10 for more details.
NC
7,12*,
13*
−
Not connected internally. (* Presence of pins depends on the type of case, see Page 21.)
GNDA
OUTA
14
15
Power Ground for channel A.
Output Output of channel A on the high voltage side. It has galvanic isolation from low voltage side and from
channel B. OUTA provides the appropriate drive voltage and source/sink current to the IGBT gate.
OUTA is actively pulled low during startup, when DIS is high and under UVLOA, UVLOI condition.
There is interlocking logic that prevents OUTA and OUTB cross conduction when DT pin is not
connected to V
.
DDI
V
DDA
16
Power High voltage side power supply for channel A. A good quality bypassing capacitor is required from this
pin to GNDA and should be placed close to the pins for best results.
The under voltage lockout (UVLOA) circuit enables the device to operate at power on when a typical
supply voltage higher than V
is present.
−
−
UVLOA OUT ON
Please see Figure 9 and 10 for more details.
www.onsemi.com
5
NCD57530, NCV57530, NCD57540, NCV57540
Table 2. SAFETY AND INSULATION RATINGS
Symbol
Parameter
Value
I−IV
Unit
−
Installation Classifications per DIN VDE 0110/1.89 Table 1 Rated
Mains Voltage
< 150 V
< 300 V
< 450 V
< 600 V
RMS
RMS
RMS
RMS
I−IV
−
I−IV
−
I−IV
−
< 1000 V
I−III
−
RMS
CTI
Comparative Tracking Index (DIN IEC 112/VDE 0303 Part 1)
Climatic Classification
600
−
40/125/21
2
−
Pollution Degree (DIN VDE 0110/1.89)
−
V
PR
Input−to−Output Test Voltage, Method b, V
× 1.875 = V , 100% Production
2250
V
PK
IORM
PR
Test with t = 1 s, Partial Discharge < 5 pC
m
V
Maximum Working Insulation Voltage
Maximum Working Insulation Voltage
Highest Allowable Over Voltage
External Creepage
1200
870
8400
8.0
V
IORM
PK
V
IOWM
V
RMS
V
V
PK
IOTM
E
mm
mm
ꢁ m
°C
CR
E
External Clearance
8.0
CL
DTI
Insulation Thickness
17.3
150
264
1136
Safety Limit Values – Maximum Values in Failure; Case Temperature
Safety Limit Values – Maximum Values in Failure; Input Power
Safety Limit Values – Maximum Values in Failure; Output Power
T
Case
P
mW
mW
ꢀ
S,INPUT
P
S,OUTPUT
9
R
Insulation Resistance at TS, V = 500 V
IO
IO
10
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Over operating free−air temperature range unless otherwise noted
Symbol
Parameter
Supply voltage, low voltage side
Minimum
−0.3
Maximum
Unit
V
V
−GNDI
−GNDA
−GNDB
22
36
36
DDI
V
V
Supply voltage, high voltage side, channel A
Supply voltage, high voltage side, channel B
Gate driver output voltage, channel A
Gate driver output voltage, channel B
−0.3
V
DDA
DDB
−0.3
V
V
GNDA − 0.3
GNDB − 0.3
−
V
DDA
V
DDB
+ 0.3
+ 0.3
V
OUTA
OUTB
V
V
I
Gate−driver output sourcing current
6.5
A
PK−SRC
(maximum pulse width = 10 ꢁ s, minimum period = 5 ms,
V
DDA
– GNDA = V
– GNDB = 15 V)
DDB
I
Gate−driver output sinking current
−
−
6.5
10
A
PK−SNK
(maximum pulse width = 10 ꢁ s, minimum period = 5 ms,
V
DDA
– GNDA = V
– GNDB = 15 V )
DDB
t
Maximum Short Circuit Clamping Time
(I = I = 500 mA)
ꢁ
s
CLP
OUTA_CLAMP
OUTB_CLAMP
V
−GNDI
Voltage at INA, INB, DIS, DT
Power Dissipation (Note 3)
−0.3
−
V
DDI
+ 0.3
V
mW
°C
°C
kV
kV
−
LIM
PD
T (max)
1060
150
150
4
Maximum Junction Temperature
−40
−65
−
J
T
Storage Temperature Range
STG
ESDHBM
ESDCDM
MSL
ESD Capability, Human Body Model (Note 4)
ESD Capability, Charged Device Model (Note 4)
Moisture Sensitivity Level
−
2
−
1
T
SLD
Lead Temperature Soldering Reflow, Pb−Free Versions (Note 5)
−
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
2. The minimum value is verified by characterization with a single pulse of 100 mA for 100 ꢁ s.
2
3. The value is estimated for ambient temperature 25°C and junction temperature 150°C, 650 mm , 1 oz copper, 2 surface layers and 2 internal
power plane layers. Power dissipation is affected by the PCB design and ambient temperature.
www.onsemi.com
6
NCD57530, NCV57530, NCD57540, NCV57540
4. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114).
ESD Charged Device Model tested per AEC−Q100−011 (EIA/JESD22−C101).
Latchup Current Maximum Rating: ≤ 100 mA per JEDEC standard: JESD78, 25°C.
5. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Table 4. THERMAL CHARACTERISTICS
Parameter
Conditions
Symbol
Value
Unit
2
Thermal Resistance, Junction−to−Air
R
°C/W
81
100 mm , 2 oz Copper, 1 Surface Layer
ꢂ
JA
2
57
100 mm , 2 oz Copper, 2 Surface Layers
and 2 Internal Power Plane Layers
Table 5. RECOMMENDED OPERATING RANGES (Note 6)
Symbol Parameter
Supply voltage, low voltage side
Minimum
UVLOI
UVLOA
UVLOB
GNDI
Maximum
Unit
V
V
DDI
−GNDI
−GNDA
−GNDB
20
32
32
V
V
Supply voltage, high voltage side, channel A
Supply voltage, high voltage side, channel B
Logic Input Voltage at INA, INB, DIS, DT
Common Mode Transient Immunity (CMTI)
Ambient Temperature
V
DDA
DDB
V
V
V
DDI
V
IN
| dV /dt |
100
−
kV/ꢁ s
°C
ISO
T
−40
125
A
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area.
Table 6. ISOLATION CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
Input−Output Isolation
Voltage
T = 25°C, Relative Humidity < 50%,
5000
−
−
V
RMS
ISO, INPUT
A
t = 1.0 minute, I
10 A, 50 Hz
I−O
TO OUTPUT
(Notes 7, 8, 9)
V
Output−Output Isolation
T = 25°C, Relative Humidity < 50%,
1500
−
−
−
−
V
RMS
ISO, OUTPUT
TO OUTPUT
A
Voltage
t = 1.0 minute, I
10 A, 50 Hz
I−O
(Notes 7, 8, 9)
11
R
Isolation Resistance
V
I−O
= 500 V (Note 7)
10
ꢀ
ISO
7. Device is considered a two−terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
8. 5,000 V for 1−minute duration is equivalent to 6,000 V for 1−second duration.
RMS
RMS
9. The input−output isolation voltage is a dielectric voltage rating per UL1577. It should not be regarded as an input−output continuous voltage
rating. For the continuous working voltage rating, refer to equipment−level safety specification or DIN VDE V 0884−11 Safety and Insulation
Ratings Table.
Table 7. ELECTRICAL CHARACTERISTICS
V
DDI
= 5V, V
= V
= 15 V
DDA
DDB
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
V
V
Supply Under Voltage Output
−
−
−
3.1
−
V
V
V
V
UVLOI−OUT−ON
DDI
Enabled
V
V
DDI
Supply Under Voltage Output
2.4
0.1
12.4
UVLOI−OUT−OFF
Disabled
V
V
DDI
Supply Voltage Output
−
−
UVLOI−HYST
Enabled/Disabled Hysteresis
V
V
V
/V Supply Under Voltage
12.9
13.4
UVLOA−OUT−ON
DDA DDB
Output Enabled
UVLOB−OUT−ON
V
V
V
/V
Supply Under Voltage Output
Supply Voltage Output
DDA DDB
11.5
12
12.5
V
UVLOA−OUT−OFF
DDA DDB
Disabled
UVLOB−OUT−OFF
V
V
/V
0.8
1.0
−
V
UVLOA/B−HYST
Enabled/Disabled Hysteresis
I
Low Voltage Side Quiescent Current
V
INA
= V = 0 V
INB
−
−
2
mA
QDDI−0
www.onsemi.com
7
NCD57530, NCV57530, NCD57540, NCV57540
Table 7. ELECTRICAL CHARACTERISTICS (continued) V
= 5V, V
= V
= 15 V
DDI
DDA
DDB
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
VOLTAGE SUPPLY
Parameter
Test Conditions
Min
Typ
Max
Unit
I
Low Voltage Side Operating Current at
50% Duty Cycle
INA PWM, INB Low (or INA Low,
INB PWM), f = 200 kHz
−
−
−
−
−
−
4
6.5
2
mA
mA
mA
QDDI−50
I
Low Voltage Side Operating Current
at 100% Duty Cycle
INA or INB High
QDDI−100
I
, I
High Voltage Side Quiescent Current
V
INA
= V
= 0 V,
QDDA−0 QDDB−0
INB
Current per Channel
I
,
High Voltage Side Operating
Current at 50% Duty Cycle
Current per Channel,
−
−
−
−
10
2
mA
mA
QDDA−50
I
f = 200 kHz, C = 1 nF
QDDB−50
G
(see Figure 18)
I
,
High Voltage Side Operating
Current at 100% Duty Cycle
Current per Channel
QDDA−100
I
QDDB−100
LOGIC INPUT
, V
V
INAL
,
Low Level Input Voltage
High Level Input Voltage
Input Hysteresis
Level scale for V = 3.3 to 5 V
DDI
−
−
−
0.3 ×
V
V
V
INBL
for V
> 5 V is the same
V
DDI
DDI
V
DISL
, V
ENL
as for V
= 5 V
DDI
V
INAH
, V
INBH
,
Level scale for V = 3.3 to 5 V
DDI
0.7 ×
V
DDI
−
for V
> 5 V is the same
DDI
DDI
V
DISH
, V
ENH
as for V
= 5 V
V
V
V
,
,
,
Level scale for V
= 3.3 to 5 V
−
0.15 ×
V
DDI
−
−
INA−HYS
INB−HYS
DIS−HYS
DDI
for V
> 5 V is the same
DDI
as for V
= 5 V
DDI
V
EN−HYS
V
, V
DISN
(Note 10)
,
Negative Input Transient
50 ns
−5
−
V
INAN
INBN
ENN
V
, V
I
I
, I , I
Logic “1” Input Bias Current
Logic “1” Input Bias Current
Logic “0” Input Bias Current
Logic “1” Input Bias Current
Logic “1” Input Bias Current
Logic “0” Input Bias Current
V
INA
V
INA
V
INA
V
INA
V
INA
V
INA
= V
= V
= V
= V
= V
= V
= 3.3 V
= 20 V
−
−
−
−
−
−
50
50
1
−
−
−
−
−
−
ꢁ A
ꢁ A
ꢁ A
ꢁ A
ꢁ A
ꢁ A
INAH INBH DISH
INB
INB
INB
INB
INB
INB
DIS
DIS
DIS
DDI
, I
, I
= V
= V
= V
= V
= V
INAH INBH DISH
DDI
I
, I
, I
= 0 V
INAL INBL DISL
I
= V = V
= 3.3 V
= 20 V
= 0 V
1
ENH
ENH
EN
DDI
DDI
DDI
I
= V = V
1
EN
I
= V = V
50
ENL
EN
DRIVER OUTPUT
V
,
Output Low State
I
I
= 200 mA, T = 25°C
−
0.1
0.22
0.5
V
V
OUTAL1
SINK
A
V
OUTBL1
= 200 mA, T = −40°C
SINK
A
V
,
to 125°C
OUTAL2
V
OUTBL2
V
,
Output High State
I
I
= 200 mA, T = 25°C
14.7
14.2
14.8
−
OUTAH1
SRC
A
V
OUTBH1
= 200 mA, T = −40°C
SRC
A
V
,
to 125°C
OUTAH2
V
OUTBH2
I
I
Peak Driver Current, Sink (Note 10)
−
−
6.5
6
−
−
A
A
PK−SNK1
Peak Miller Plateau Current, Sink
(Note 10)
V
= V
= 6 V
PK−SNK2
OUTA
OUTB
(near IGBT Miller Plateau)
I
I
Peak Driver Current, Source (Note 10)
−
−
6.5
6
−
−
A
A
PK−SRC1
Peak Miller Plateau Current, Source
(Note 7)
V
= V
= 9 V
PK−SRC2
OUTA
OUTB
(near IGBT Miller Plateau)
IGBT SHORT CIRCUIT CLAMPING
Clamping Voltage
V
,
I
= I = 500 mA
OUTB
−
1
1.3
V
CLAMP−OUTA
OUTA
V
(V
(V
− V
− V
),
(pulse test, t
= 10 ꢁ s)
CLAMP−OUTB
CLAMP−OUTA
CLAMP−OUTB
DDA
DDB
CLPmax
)
(see Figure 30)
www.onsemi.com
8
NCD57530, NCV57530, NCD57540, NCV57540
Table 7. ELECTRICAL CHARACTERISTICS (continued) V
= 5V, V
= V
= 15 V
DDI
DDA
DDB
For typical values T = 25°C, for min/max values, T is the operating ambient temperature range that applies, unless otherwise noted.
A
A
Symbol
DYNAMIC CHARACTERISTIC
Parameter
Test Conditions
Min
Typ
Max
Unit
t
OUTA High Propagation Delay
OUTA Low Propagation Delay
Propagation Delay Distortion
C
= 10 nF, V to 10%
INAH
40
40
60
60
0
90
90
20
90
90
20
20
20
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PD−ON−A
LOAD
of Output Change for PW > 150 ns
C = 10 nF, V to 90%
LOAD
t
PD−OFF−A
INAL
of Output Change for PW > 150 ns
t
PW >150 ns
−20
40
DISTORT−A
(Channel A) (t
− t
)
)
PD−ON−A
PD−OFF−A
t
OUTB High Propagation Delay
OUTB Low Propagation Delay
Propagation Delay Distortion
C
= 10 nF, V to 10%
INBH
60
60
0
PD−ON−B
LOAD
of Output Change for PW > 150 ns
t
C
= 10 nF, V to 90%
40
PD−OFF−B
DISTORT−B
LOAD
INBL
of Output Change for PW > 150 ns
t
PW >150 ns
−20
−20
−20
−
(Channel B) (t
− t
PD−OFF−B
PD−ON−B
t
Rising Edge Propagation Delay
Distortion (t − t
PW >150 ns
PW >150 ns
0
DISTORT−ON
)
PD−ON−A
PD−ON−B
t
Falling Edge Propagation Delay
0
DISTORT−OFF
Distortion (t
− t
PD−OFF−B
)
PD−OFF−A
t
t
Rise Time for Both Channel A and B
Fall Time for Both Channel A and B
Deadtime between channels
C
= 1 nF, 10% to 90%
LOAD
12
10
RISE
of Output Change
C
= 1 nF, 90% to 10%
−
−
FALL
LOAD
of Output Change
t
DT
DT pin Float
−
−
<20
5
−
−
ns
ꢁ s
ns
ns
ns
ns
ns
ns
ns
ꢁ s
ꢁ s
R
R
= 500 kꢀ
= 20 kꢀ
DT
DT
−
200
60
60
−
−
t
Disable Delay (NCx57540 only)
Enable Delay (NCx57530 only)
Input Pulse Width for no output
−
−
DIS
t
−
−
EN
t
t
Positive pulse (L−H−L), T = 25°C
−
10
10
−
MIN1
MIN2
A
Negative pulse (H−L−H), T = 25°C
−
−
A
Input Pulse Width for guaranteed output
Positive pulse (L−H−L), T = 25°C
40
40
−
−
A
Negative pulse (H−L−H), T = 25°C
−
−
A
t
UVLOI/UVLOA/UVLOB Fall Delay
UVLOI/UVLOA/UVLOB Rise Delay
(Note 10)
(Note 10)
1.5
20
−
UVF
t
10
−
UVR
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10.Values based on design and/or characterization.
11. PW = Pulse Width
Modes of Operation
The typical application schematics are on Figure 2 and
Figure 3.
The NCx575y0 can operate in 2 distinct modes:
1. The low−side, high−side half−bridge driver with
programmable dead−time.
• The dead−time is set by resistor R connected between
DT
DT pin and GNDI. Adjusting dead−time is described in
the section Dead−time (DT).
2. The two independent (potentially overlapping)
channels with two inputs.
nd
2
mode – driver with two independent channels and two
st
1
mode – half−bridge driver with two inputs and
inputs is different from previous mode because it allows for
completely independent and even overlapping PWMs to
drive the outputs individually.
adjustable dead−time is for applications where you have
high−side and low−side PWM available. The driver
provides interlock function to prevent activation of
high−side and low−side outputs at the same time. In addition
the driver generates dead−time which is adjustable by DT
pin.
• DT pin has to be connected to V . This disables the
DDI
interlock function and dead−time generator and allows
the overlapping PWMs. So the channel A and B can be
driven completely independently.
www.onsemi.com
9
NCD57530, NCV57530, NCD57540, NCV57540
Dead−Time (DT)
achieved. The lowest allowed value of R = 5 kꢀ which
DT
The dead−time pin is controlling the integrated interlock
and dead−time generator.
reduces the dead−time to about 70 ns.
The Figures 2 and 3 illustrate the behavior of the
• If DT pin is connected to V
the interlock and
dead−time generator are disabled. The channels A and B
DDI
st
NCx575y0 in 1 mode (high−side, low−side half−bridge
driver with two inputs). The outputs for various input PWM
combinations are shown in Figure 4.
are completely independent.
• If DT pin is floating the interlock is enabled but dead−time
generator is disabled. There is a minimal dead−time
shorter than 20 ns.
The dead−time is a time from low−side output going low
to high−side output going high or from high−side output
going low to low side output going high. The overlap is
a situation where both signals are high at the same time.
Overlap causes cross conduction in the half−bridge and must
be avoided.
In the “Non−overlap and Dead−time are met” column in
Fig. 4, the channel A PWM, INA (high−side), and channel
B PWM, INB (low−side), are not overlapping and have
sufficient dead−time. Therefore, the driver does not apply
corrections to the signals and passes them as they are to their
respective output.
• If there is a resistor R connected between the DT pin
DT
and GNDI the interlock and dead−time generator are both
enabled. The dead−time can be adjusted in range from
200 ns (R ≈ 20 kꢀ) to 5 ꢁ s (R ≈ 500 kꢀ). Dead−time
DT
DT
can be estimated by the equation t (ns) ≈ 10 x R (kꢀ).
DT
DT
With high R values the potential noise pick−up on high
DT
impedance of R should be considered. R should be
DT
DT
as close to driver pins as possible and the loop should be
minimized.
• If R is below 20 kꢀ the DT is not closely following the
DT
equation but dead−times lower than 200 ns could be
Figure 4. Deadtime, Interlock and Output Minimum Pulse Width
In the “Dead−time corrected” column, the high−side and
low−side signals are not overlapping but the dead−time
value is less than the value set through the DT pin.
Consequently, the driver increases the dead−time value to
the value set by the DT pin.
In the “Overlap and Dead−time corrected” column, the
high−side and low−side input signals are high at the same
time (overlapping). This condition could cause
cross−conduction in the half−bridge. Therefore, the driver’s
interlock function trims signal OUTB which is going low
when INA goes high, and not when INB goes low. The driver
also inserts the dead−time set through DT pin, thus the
output pulses are not overlapping and cross−conduction in
the half−bridge is avoided.
In the “Overlap, Dead−time corrected and Short pulses
filtered out” column, the high−side and low side signals are
overlapping and could cause cross−conduction in the
half−bridge. Therefore, the driver’s interlock function trims
the output signals and a short spike remains on each output
signal. If the spike is shorter than tMIN1 (Minimum pulse
width filtering time), it will be suppressed and no output is
generated.
www.onsemi.com
10
NCD57530, NCV57530, NCD57540, NCV57540
Enable (EN) Pin (NCx57530)
In the “Overlap corrected” column the dead−time is met
but the signals are overlapping so just the non−overlapping
parts pass to the output.
EN (Enable) is a useful feature as it allows to deactivate
both outputs independently of inputs INA, INB, DT. If EN
is set to high both OUTA and OUTB work depending on
INA and INB. If EN is set to low, the outputs OUTA/OUTB
are set to low immediately, then if EN is set to high,
OUTA/OUTB follows INA/INB immediately (see
Figure 5). It has an internal pull−up resistor of 125 kꢀ to
ensure that OUTA and OUTB react to INA, INB and DT in
the absence of an external signal. External pull−up resistor
10−47 kꢀ is recommended to prevent unwanted EN
activation by external interference. Direct connection to
VDDI is recommended if the pin is not used.
Inputs INA, INB, DIS, EN
Unused inputs INA, INB, DIS should be tied to GNDI.
Unused EN should be tied to V
.
DDI
Disable (DIS) Pin (NCx57540)
DIS (disable) pin allows to deactivate both outputs
independently of inputs INA, INB, DT.
If the pin is set high both OUTA and OUTB are set low
immediately.
If DIS is set low, the outputs OUTA/OUTB are restored
after rising edge is detected on the INA/INB respectively.
It has an internal pull−down resistor of 125 kꢀ to ensure
that OUTA and OUTB react to INA, INB and DT in the
absence of an external signal. External pull−down resistor
10−47 kꢀ is recommended to prevent unwanted DIS
activation by external interference. Direct connection to
GNDI is recommended if the pin is not used.
Input Voltage Levels
The NCx575y0 has a two modes for high and low levels
on all input pins:
1. For V
from 3.3 to 5 V the high and low input
DDI
levels are scaling with the V
as stated in the
DDI
Electrical characteristics table. Low input level is
0.3 × V , high input level is 0.7 × V
.
DDI
DDI
2. For V
above 5 V the high and low input levels
DDI
NCx57530
clamp at the same value as for V
means the low input level is 0.3 × 5 = 1.5 V and the
high input level is 0.7 × 5 = 3.5 V.
= 5 V. That
DDI
EN (ENABLE)
VDDI
tEN
tEN
tEN
Clamping
Circuit
INA
(INB)
INx
tPD-ON-X
tPD-OFF-X
Figure 6. Input Pin Structure
OUTx
Edge Triggered Inputs
The INA, INB and DIS inputs are activated by a signal
edge (edge triggered), not with signal level. This means that
after power cycling the driver, a rising edge has to occur on
INA, INB for OUTA and OUTB to go high, respectively.
The same conditions apply if the output signals are disabled
through the DIS pin. Therefore, after DIS signal goes low,
a rising edge has to occur on INA, INB for OUTA and OUTB
to go high, respectively.
NCx57540
DIS (DISABLE)
tDIS
tDIS
Under Voltage Lockout UVLOI, UVLOA, UVLOB
NCx575y0 UVLOA and UVLOB ensures reliable
switching of the IGBT connected to the driver output.
Driving the IGBT with low gate voltage causes it to switch
outside the saturation region (in the linear region) which
significantly increases the power losses and there is a danger
of damage.
INx
OUTx WAITING
FOR INx RISING
EDGE TRIGGER
tPD-ON-X
tPD-ON-X
OUTx
UVLOI ensures correct transmission of the signals from
the primary side to the secondary side of the driver.
NCx575y0 is equipped by edge triggered inputs in order
to prevent output pulse trimming. Therefore, after returning
from safe state to active state, a rising edge has to occur on
Figure 5. Disable Function
www.onsemi.com
11
NCD57530, NCV57530, NCD57540, NCV57540
INA, INB in order to set OUTA and OUTB high,
respectively (see Figures 7, 8 and Figures 9, 10).
Another note for the t
is that it is valid if the V
rises
. The
UVR
DD2
from just below V
to V
UVLO−OUT−OFF
UVLO−OUT−ON
As a side effect of this feature is that the t
time is
cold−start time from V
= 0 V to PWM at the output
UVR
DDA(B)
always prolonged by a t
. The t
is the
is t
+ startup time of the internal bias circuits. The whole
UVR−spread
UVR−spread
UVR
delay caused by the time before next rising edge of PWM
signal comes.
time is about 20 ꢁ s and the internal bias circuit startup time
is about 10 ꢁ s.
V
DDA
V
DDB
V
UVLOI-HYST
V
V
UVLOI-OUT-ON
UVLOI-OUT-OFF
V
DDI
t
t
t
t
t
UVF
UVR
UVF
UVR
UVR
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 7. Output Ramp−up and Ramp−down Times during UVLOI
V
DDA
V
DDB
V
V
UVLOI-OUT-ON
UVLOI-OUT-OFF
V
DDI
t
t
UVF
t
t
t
UVR
UVR
UVF
UVR
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 8. VDDI Glitch Filtering
www.onsemi.com
12
NCD57530, NCV57530, NCD57540, NCV57540
V
V
DDI
V
UVLOA,B-HYST
UVLOA,B-OUT-ON
UVLOA,B-OUT-OFF
V
V
/V
DDA DDB
t
t
t
UVR
t
t
UVR
UVF
UVR
UVF
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 9. Output Ramp−up and Ramp−down Times during UVLOA, UVLOB
V
DDI
V
V
UVLOA,B-OUT-ON
UVLOA,B-OUT-OFF
V
/V
DDA DDB
t
t
t
UVR
t
t
UVF
UVF
UVR
UVR
t
UVR-spread
INA/INB
OUTA/OUTB
Figure 10. VDDA/VDDB Glitch Filtering
Power Supply
Cooling Polygons on GNDA/GNDB
It is important to provide cooling polygons if driving
IGBTs with higher gate capacitance values and using higher
switching frequencies. They have to be connected to GNDA
and GNDB (See Figure 12).
Decoupling (VDDI, VDDA, VDDB)
Suitable external power capacitors are required for
reliable driving of IGBT gate with high current. Parallel
combination of 100 nF + 4,7 ꢁ F low ESR ceramic capacitors
is optimal for a wide range of applications using IGBT. For
reliable driving of IGBT modules (containing several
parallel IGBT’s) with a gate capacitance over 10 nF a higher
decoupling capacity is required (typically 100 nF + 10 ꢁ F).
Capacitors should be as close as possible to the driver’s
power pins. The recommended layout is provided in the
Figure 12.
Output Current on GNDA/GNDB
The NCx575y0 has a high current, low−drop MOSFET
output stage. It is capable of driving IGBTs with gate
capacitance C of up to 100 nF. For optimal IGBT driving
G
a few conditions have to be met:
www.onsemi.com
13
NCD57530, NCV57530, NCD57540, NCV57540
• Low inductance (wide and short) traces from OUTA
(OUTB) to R and to IGBT gate and from emitter
G
(source) to GNDA (GNDB).
• Sufficient power rating of gate resistors R .
G
• Reasonable combination of switching frequency f and
gate capacitance C of the IGBT.
G
• Good V
and V
decoupling (discussed above).
DDA
DDB
• Sufficient cooling pads (discussed above).
Low Inductance Traces
All the traces have to be as low inductance as possible due
to the high current path from the driver output to IGBT gate.
In practice that means wide tracks which are as short as
possible. Tracks also have to be routed in order to not create
big loops. The driving path (driver output, RG, IGBT gate)
and return path (IGBT emitter, GNDA or GNDB pin) have
to be routed as a pair and not enclosing other components.
Figure 12. SOIC−16 Recommended Layer Stack
(CASE 752AJ)
High−speed
signals
10 mils
0.25 mm
10 mils
0.25 mm
Ground plane
Keep this space free
from traces, pads
and vias
40 mils
1 mm
40 mils
1 mm
Power plane
10 mils
0.25 mm
10 mils
0.25 mm
Low−speed
signals
314 mils
(8 mm)
Figure 11. SOIC−16WB Recommended Layer Stack
www.onsemi.com
14
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
6
5
4
3
2
1
0
6
(6)
5
(6)
(3)
(3)
4
(5)
(5)
3
(2)
(4)
(2)
(4)
2
(1)
1
(1)
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) I
(2) I
(3) I
(4) I
(5) I
(6) I
−0, I = 0 V, I = 0 V, D = 5 V
NA NB T
QDDI
(1) I
, I = 0 V, I = 0 V, D = 5 V
NB T
QDDI−0 NA
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
(2) I
(3) I
(4) I
(5) I
(6) I
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
QDDI−50 NA
NB
T
QDDI−50 NA
NB
T
, I = 5 V, I = 0 V, D = 5 V
, I = 5 V, I = 0 V, D = 5 V
QDDI−100 NA
NB
T
QDDI−100 NA
NB
T
, I = 0 V, I = 0 V, D = 5 k
, I = 0 V, I = 0 V, D = 5 k
QDDI−0 NA
NB
T
QDDI−0 NA
NB
T
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 k
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 k
QDDI−50 NA
NB
T
QDDI−50 NA
NB
T
, I = 5 V, I = 0 V, D = 5 k
, I = 5 V, I = 0 V, D = 5 k
QDDI−100 NA
NB
T
QDDI−100 NA
NB
T
(Note: V
DDI
= 5 V, V
DDA
= 15 V, V
= 15 V)
(Note: V
= 3.3 V, V
DDA
= 15 V, V
= 15 V)
DDB
DDI
DDB
Figure 14. IQDDI Supply Current, VDDI = 5 V
Figure 13. IQDDI Supply Current, VDDI = 3.3 V
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
(5)
(6)
(3)
(5)
(2)
(6)
(2)
(4)
(1)
(3)
(4)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) I
(2) I
(3) I
(4) I
(5) I
(6) I
, V
, V
, V
= 15 V, I = 0 V, I = 0 V, D = 5 V
(1) I
(2) I
(3) I
(4) I
(5) I
(6) I
, I = 0 V, I = 0 V, D = 5 V
QDDA−0 DDA NA NB T
QDDI−0 NA
NB
T
= 15 V, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
NA NB T
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 V
QDDA−50 DDA
QDDI−50 NA
NB
T
= 15 V, I = 5 V, I = 0 V, D = 5 V
NA NB T
, I = 5 V, I = 0 V, D = 5 V
QDDA−100 DDA
QDDI−100 NA
NB
T
, V
= 32 V, I = 0 V, I = 0 V, D = 5 V
NA NB T
, I = 0 V, I = 0 V, D = 5 k
QDDA−0 DDA
QDDI−0 NA
NB
T
, V
, V
= 32 V, I = 5 V/200 kHz/50%, I = 0 V, DT = 5 V
NA NB
, I = 5 V/200 kHz/50%, I = 0 V, D = 5 k
QDDA−50 DDA
QDDI−50 NA
NB
T
, I = 5 V, I = 0 V, D = 5 k
= 32 V, I = 5 V, I = 0 V, D = 5 V
QDDA−100 DDA NA NB T
QDDI−100 NA
NB
T
(Note: V
= 5 V, V
= 15 V)
(Note: V
= 20 V, V
DDA
= 15 V, V
= 15 V)
DDI
DDB
DDI
DDB
Figure 16. IQDDA Supply Current
Figure 15. IQDDI Supply Current, VDDI = 20 V
www.onsemi.com
15
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
20
8
7
6
5
4
3
2
1
0
(5)
(1)
(3)
(2)
15
(2)
10
(6)
5
(3)
(4)
(1)
0
−40 −20
0
20
40
60
80
100 120
1
10
100
1000
Temperature (5C)
Frequency (kHz)
(1) I
, V
= 15 V, I = 0 V, I = 0 V, D = 5 V
QDDB−0 DDB
NA
NB
T
(2) I
(3) I
(4) I
(5) I
(6) I
, V
= 15 V, I = 0 V, I 5 V/200 kHz/50%, D = 5 V
NB = T
= 15 V, I = 0 V, I = 5 V, D = 5 V
NA NB T
= 32 V, I = 0 V, I = 0 V, D = 5 V
NA NB T
(1) C = 1 nF
(2) C = 10 nF
G
(3) C = 100 nF
G
QDDB−50 DDB
NA
G
, V
QDDB−100 DDB
, V
QDDB−0 DDB
, V
= 32 V, I = 0 V, I = 5 V/200 kHz/50%, D = 5 V
QDDB−50 DDB
NA
NB
T
(Note: V
= 5 V, V
= 15 V, V = 15 V, I = 5 V/50%, I = 0 V,
DDB NA NB
DDI
DDA
, V
= 32 V, I = 0 V, I = 5 V, D = 5 V
NA NB T
QDDB−100 DDB
D = V , DIS = GNDI, R = 0 Ω)
T DDI G
(Note: V
= 5 V, V
= 15 V)
DDI
DDA
Figure 18. IQDDA (IQDDB) Supply Current
vs. Switching Frequency
Figure 17. IQDDB Supply Current
−0.1
−0.2
−0.3
−0.4
−0.5
28
27
26
25
24
23
22
21
(3)
(2)
(1)
(3)
(2)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(3) I
(2) I
(2) I
(3) I
(1) I
INAL
(1) I
DISL
INBL
INBH
DISH
INAH
(Note: V
= 3.3 V, V
= V
INB
= V
DIS
= GNDI, V
= V = 15 V)
DDB
(Note: V
= V
INA
= V
INB
= V
DIS
= 3.3 V, V
= V
DDB
= 15 V)
DDI
INA
DDA
DDI
DDA
Figure 20. Input Bias Current − Logic “0”
Figure 19. Input Bias Current − Logic “1”
www.onsemi.com
16
Temperature (5
Temperature (5C)
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
41
40
39
38
37
36
35
34
33
32
−0.1
(3)
−0.2
(2)
−0.3
(3)
(1)
−0.4
(2)
(1)
−0.5
−40 −20
0
20
40
60
C)
80
100 120
−40 −20
0
20
40
60
80
100 120
(2) I
(3) I
(3) I
DISL
(1) I
(2) I
INBL
(1) I
INBH
DISH
INAH
INAL
(Note: V
= V
INA
= V
INB
= V
DIS
= 5 V, V
= V
DDB
= 15 V)
(Note: V
= 5 V, V
= V
INB
= V
DIS
= GNDI, V
= V = 15 V)
DDB
DDI
DDA
DDI
INA
DDA
Figure 21. Input Bias Current − Logic “1”
Figure 22. Input Bias Current − Logic “0”
−0.1
−0.2
−0.3
−0.4
−0.5
49
48
47
46
45
44
43
42
41
40
39
38
37
(3)
(2)
(1)
(3)
(2)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(3) I
(2) I
(2) I
(3) I
(1) I
INAL
(1) I
DISL
INBL
INBH
DISH
INAH
(Note: V
= 20 V, V
= V
= V
= GNDI, V
= V = 15 V)
DDB
(Note: V
= V
INA
= V
INB
= V
DIS
= 20 V, V
= V
DDB
= 15 V)
DDI
INA
INB
DIS
DDA
DDI
DDA
Figure 23. Input Bias Current − Logic “1”
Figure 24. Input Bias Current − Logic “0”
www.onsemi.com
17
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
13
12.9
12.8
12.7
12.6
12.5
12.4
12.3
12.2
12.1
12
2.9
2.8
(1)
(3)
2.7
2.6
2.5
(1)
(2)
(2)
(4)
11.9
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) V
(4) V
(1) V
UVLOA−OUT−OFF
UVLOA−OUT−ON
(2) V
(1) V
UVLOI−OUT−OFF
UVLOI−OUT−ON
(3) V
UVLOB−OUT−ON
UVLOB−OUT−OFF
Figure 26. UVLOI Threshold Voltage
Figure 25. NCx57540 UVLOA and UVLOB
Threshold Voltage
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
140
130
120
110
100
90
(3)
(1)
(2)
(1)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) t
(1) V
(2) V
(3) V
UVFI
UVLOI−HYST
UVLOA−HYST
UVLOB−HYST
Figure 27. UVLOx Enable/Disable Voltage
Hysteresis
Figure 28. UVLOI Fall Delay
www.onsemi.com
18
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
1.1
1.5
1.4
1.3
1.05
(1)
1
(1)
(2)
(2)
0.95
0.9
0.85
0.8
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) t
(1) V
(2) V
(1) t
UVFB
CLAMP−OUTA
CLAMP−OUTB
UVFA
Figure 29. UVLOA and UVLOB Fall Delay
Figure 30. IGBT Short Circuit Clamping Voltage
84
82
80
78
76
74
72
70
80
78
76
74
72
70
(1)
(4)
(1)
(3)
(2)
(5)
(6)
(2)
(3)
(5)
(6)
(4)
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) t
(3) t
(5) t
, V
= 3.3 V
= 5 V
= 20 V
(2) t
(4) t
(6) t
, V
= 3.3 V
= 5 V
= 20 V
PD−ON−A DD1
PD−ON−B DD1
(1) t
(3) t
(5) t
, V
= 3.3 V
= 5 V
= 20 V
(2) t
(4) t
(6) t
, V
= 3.3 V
, V = 5 V
PD−OFF−B DD1
PD−OFF−A DD1
PD−OFF−B DD1
, V
, V
PD−ON−A DD1
PD−ON−B DD1
, V
PD−OFF−A DD1
, V
, V
PD−ON−A DD1
PD−ON−B DD1
, V
, V = 20 V
PD−OFF−B DD1
PD−OFF−A DD1
Figure 32. Propagation Delay Turn−off
Figure 31. Propagation Delay Turn−on
www.onsemi.com
19
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
16.5
16
76
(1)
(1)
15.5
15
74
(3)
(2)
14.5
14
72
(2)
13.5
13
70
68
12.5
12
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(1) t
(2) t
(3) t , V
= 20 V
(1) t , V
DIS DD1
= 3.3 V
(2) t , V
= 5 V
RISE
FALL
DIS DD1
DIS DD1
Figure 33. Rise Time / Fall Time
Figure 34. Disable Delay Time
80
18
16
14
12
10
8
(1)
(1)
(3)
78
76
74
72
70
(2)
(3)
6
4
2
(2)
0
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
Temperature (5C)
(2) t , V
= 5 V
(3) t , V
= 20 V
(2) t , V
= 5 V
(1) t , V
= 3.3 V
(1) t , V
= 3.3 V
(3) t , V
= 20 V
DT DDI
DT DDI
DT DDI
DT DDI
DT DDI
DT DDI
(Note: V
is inverted from V , V
= V
DDB
= 15 V)
INA
INB DDA
(Note: V
is inverted from V , V
= V
DDB
= 15 V)
INA
INB DDA
Figure 36. Deadtime, DT pin 5 kW to GNDI
Figure 35. Deadtime, DT pin FLOAT
www.onsemi.com
20
NCD57530, NCV57530, NCD57540, NCV57540
TYPICAL CHARACTERISTICS
5.5
5.3
5.1
4.9
4.7
4.5
(1)
(2)
(3)
−40 −20
0
20
40
60
80
100 120
Temperature (5C)
(2) t , V
= 5 V
(1) t , V
= 3.3 V
(3) t , V
= 20 V
DT DDI
DT DDI
DT DDI
(Note: V
is inverted from V , V
= V
DDB
= 15 V)
INA
INB DDA
Figure 37. Deadtime, DT pin 500 kW to GNDI
ORDERING INFORMATION
†
Device
Qualification
Package
Case
Shipping
NCD57530DWKR2G
NCD57540DWKR2G
NCV57530DWKR2G*
Industrial
SOIC−16 Wide Body (less pin 12 & 13) (Pb−Free)
752AJ 1,000 / Tape & Reel
Automotive
(AEC−Q100 Qualified
and PPAP Capable)
NCV57540DWKR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
www.onsemi.com
21
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−16 WB LESS PINS 12 & 13
CASE 752AJ
ISSUE O
DATE 17 FEB 2021
1
SCALE 1:1
GENERIC
MARKING DIAGRAM*
16
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
AWLYYWW
XXXXX = Specific Device Code
*This information is generic. Please refer to
A
= Assembly Location
= Wafer Lot
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
WL
YY
WW
= Year
= Work Week
1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON30578H
SOIC−16 WB LESS PINS 12 & 13
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
ADDITIONAL INFORMATION
TECHNICAL PUBLICATIONS:
Technical Library: www.onsemi.com/design/resources/technical−documentation
onsemi Website: www.onsemi.com
ONLINE SUPPORT: www.onsemi.com/support
For additional information, please contact your local Sales Representative at
www.onsemi.com/support/sales
相关型号：
NCD5R1J1KN150TRF
Ceramic Capacitor, Ceramic, 1000V, 5% +Tol, 5% -Tol, N150, -150ppm/Cel TC, 0.0000051uF,
NICHICON
NCD5R6M500SLJ.1LSTBF
Ceramic Capacitor, Ceramic, 500V, 20% +Tol, 20% -Tol, SL, -330ppm/Cel TC, 0.0000056uF,
NICHICON
NCD680C2KVNPOCTBF
Ceramic Capacitor, Ceramic, 2000V, 0.37% +Tol, 0.37% -Tol, C0G, 30ppm/Cel TC, 0.000068uF, Through Hole Mount, RADIAL LEADED, ROHS COMPLIANT
NICHICON
NCD680D50N1500K.1LSTBF
Ceramic Capacitor, Ceramic, 50V, 0.7353% +Tol, 0.7353% -Tol, N1500, -1500ppm/Cel TC, 0.000068uF,
NICHICON
NCD680D5KVNPOETRF
Ceramic Capacitor, Ceramic, 5000V, 0.74% +Tol, 0.74% -Tol, C0G, 30ppm/Cel TC, 0.000068uF, Through Hole Mount, RADIAL LEADED, ROHS COMPLIANT
NICHICON
NCD680Z3KVNPOETBF
Ceramic Capacitor, Ceramic, 3000V, 80% +Tol, 20% -Tol, C0G, 30ppm/Cel TC, 0.000068uF, Through Hole Mount, RADIAL LEADED, ROHS COMPLIANT
NICHICON
NCD681D100N1500K.1LSTBF
Ceramic Capacitor, Ceramic, 100V, 0.0735% +Tol, 0.0735% -Tol, N1500, -1500ppm/Cel TC, 0.00068uF,
NICHICON
NCD681D50N3300D.2LSF
Ceramic Capacitor, Ceramic, 50V, 0.0735% +Tol, 0.0735% -Tol, N3300, -3300ppm/Cel TC, 0.00068uF,
NICHICON
NCD681J1KSLD.295LSF
Ceramic Capacitor, Ceramic, 1000V, 5% +Tol, 5% -Tol, SL, -330ppm/Cel TC, 0.00068uF,
NICHICON
NCD681K1KVY5PJ.1LSTRF
Ceramic Capacitor, Ceramic, 1000V, 10% +Tol, 10% -Tol, Y5P, -/+10ppm/Cel TC, 0.00068uF,
NICHICON
NCD681K50N3300K.1LSTRF
Ceramic Capacitor, Ceramic, 50V, 10% +Tol, 10% -Tol, N3300, -3300ppm/Cel TC, 0.00068uF,
NICHICON
©2020 ICPDF网 联系我们和版权申明