NCD98011XMXTAG [ONSEMI]
12-Bit Low Power SAR ADC;
| 型号： | NCD98011XMXTAG |
| 厂家： | 
ONSEMI |
| 描述： | 12-Bit Low Power SAR ADC |
| 文件： | 总12页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Low Power SAR ADC
NCD98010, NCD98011
The NCD98010 (unsigned output) and the NCD98011 (signed
output) ADC products provide an extremely low power solution for
analog to digital conversion applications using a capacitor−based
successive−approximation architecture. Optimized for low power and
speed, the NCD98010/1 can achieve a sample rate of 2 MSPS while
consuming less than 1 mW of power. The device also features a large
input voltage range of 1.65 V to 3.3 V for various applications for both
analog and digital supplies. The SPI−compatible interface provides a
straight−forward data−acquisition method.
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MARKING
DIAGRAMS
Features
X2QFN8
DP SUFFIX
CASE 722AM
XXM
• Nanowatt Power Consumption
• Fully Differential Input
• 2−MSPS Throughput
• Small Package Size
• Pre−Calibrated
US8 (SSOP8)
MX SUFFIX
CASE 493
XXM
• SPI Interface
XX
M
= Specific Device Code
= Date Code
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
PIN CONFIGURATION
• Low−Power Data Acquisition
• Battery−powered Equipment
• Level Sensors
• Ultrasonic Flow Meters
• Motor Controls
• Wearable Fitness
V
INN
8
CSN
V
V
1
2
3
7
6
5
INP
OUT
CLK
CC
GND
4
V
DD
• Portable Medical Equipment
• Glucose Meters
VCC
X2QFN8 (Top View)
V
GND
1
2
8
7
DD
VDD
CLK
V
CC
V
OUT
CSN
3
4
6
5
INP
+
V
INN
VINP
CSN
CLK
Switched
Comparator
Capacitive
DAC
US8 (Top View)
VINN
-
Serial
Interface
ORDERING INFORMATION
†
Device
Package
Shipping
Successive Approximation Register
Digital Control
OUT
NCD98010XMXTAG
NCD98011XMXTAG
X2QFN
5000 / Tape &
Reel
NCD98010XDPT3G*
NCD98011XDPT3G*
SSOP8
GND
Figure 1. Block Diagram
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
* These products are currently under development.
Please contact Sales regarding their availability.
© Semiconductor Components Industries, LLC, 2020
1
Publication Order Number:
March, 2020 − Rev. 1
NCD9801/D
NCD98010, NCD98011
PIN DESCRIPTION
X2QFN
Pin No.
SSOP
Pin No.
Name
CSN
OUT
CLK
Function
1
2
3
4
5
6
7
8
4
3
2
1
8
7
6
5
Chip select (active low)
Data Output (serialized)
Clock
VDD
GND
VCC
Digital I/O supply voltage
Common ground for all pins
Analog supply and ADC reference voltage
Analog input, positive signal
V
INP
INN
V
Analog input, negative signal
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3 to 3.63
−0.3 to 3.63
−0.3 to 3.63
−0.3 to 3.63
−0.3 to 3.63
−0.3 to 3.63
−40 to 150
260
Unit
V
Supply Voltage Range
Supply Voltage Range
Input Voltage Range
V
CC
V
DD
V
V
V
INP
INN
OUT
Input Voltage Range
V
V
Output Voltage Range
CSN Input Voltage Range
Storage Temperature Range
V
V
V
EN
V
T
STG
°C
°C
kV
V
Lead Temperature, Soldering (10 sec.)
T
SLD
ESD Capability, Human Body Model (Note 1)
ESD Capability, Charged Device Model (Note 1)
Latch−up Current Immunity (Note 1)
ESD
ESD
2.0
HBM
CDM
500
LU
100
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested by the following methods @ T = 25°C:
A
ESD Human Body Model tested per JESD22−A114
ESD Charged Device Model per ESD STM5.3.1
Latch−up Current tested per JESD78.
RECOMMENDED OPERATING CONDITIONS
Rating
Symbol
Min
1.65
1.65
Max
3.6
3.6
0
Unit
V
Analog Supply Voltage
Digital I/O Supply Voltage
Ground
V
CC
V
DD
V
GND
V
Ambient Temperature
Junction Temperature
T
−40
−40
120
125
°C
°C
A
T
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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2
NCD98010, NCD98011
ELECTRICAL CHARACTERISTICS (T = 25°C, V = 3 V, unless otherwise noted)
J
CC
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
POWER SUPPLY REQUIREMENTS
Analog Supply and ADC reference
Digital I/O Supply
V
V
1.65
1.65
3
3.6
3.6
150
V
CC
3
V
DD
2 MSPS for V = 3.6 V
100
50
mA
mA
mA
mA
mW
mW
mW
mW
mA
mA
mA
mA
CC
1 MSPS for V = 3 V
CC
Analog Supply Current
I
VCC
100 kSPS for V = 3.6 V
7.6
30
20
540
72
CC
1 MSPS for V = 1.8 V
CC
2 MSPS for V = 3.6 V
300
150
15
CC
1 MSPS for V = 3 V
CC
Analog Power Dissipation
P
I
VCC
100 kSPS for V = 3.6 V
CC
1 MSPS for V = 1.8 V
54
CC
2 MSPS for V = 3.6 V
852
425
45
DD
Digital Supply Current
Dependent on SDO loading
(tested with ~7 pF)
1 MSPS for V = 3 V
DD
VDD
100 kSPS for V = 3.6 V
DD
1 MSPS for V = 1.8 V
136
DD
Standby current (CSN high)
(Note 2)
V
CC
= 3.6 V
I
3.9
6
mA
STNDBY
ANALOG INPUT
Full−Scale Voltage Span
Common Mode Voltage=V /2
V
fs
−V
CC
V
CC
V
ppd
CC
V
inp
V
inn
to GND
to GND
−0.2
−0.2
V
CC
V
CC
+ 0.1
V
Absolute Voltage Range
+ 0.1
V
Sampling Capacitance
SYSTEM PERFORMANCE
Resolution
Measured with 1kHz, 1V Stimuli
C
2
pF
S
12
0
Bits
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.8 V
= 3.3 V
= 1.8 V
= 3.3 V
= 1.8 V
= 3.3 V
= 1.8 V
= 3.3 V
−2
−2
2
2
Integral Nonlinearity (Note 3)
Differential Nonlinearity (Note 3)
Offset Error
INL
LSB
0
−1.5
−1.5
0
1.5
DNL
LSB
LSB
0
1.5
0
E
O
−10
0
10
10
Effective Number of bits
Offset error drift with temperature
Gain Error
ENOB
dV /dT
11.2
0.02
0.3
0.3
0.0006
ppm/°C
%FS
OS
V
V
= 1.8 V
= 3.3 V
−0.6
0.6
CC
E
G
CC
Gain error drift with temperature
SAMPLING DYNAMICS
Acquisition Time
%FS/°C
62.5
ns
Maximum throughput rate
DYNAMIC CHARACTERISTICS
2
MSPS
f
IN
f
IN
f
IN
f
IN
= 1 kHz V = 3.3 V
70
65
CC
Signal−to−Noise Ratio
SNR
THD
dB
dB
= 1 kHz V = 1.8 V
CC
= 1 kHz V = 3.3 V
−80
−80
CC
Total−Harmonic Distortion
= 1 kHz V = 1.8 V
CC
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3
NCD98010, NCD98011
ELECTRICAL CHARACTERISTICS (T = 25°C, V = 3 V, unless otherwise noted)
J
CC
Parameter
Conditions
Symbol
Min
Typ
Max
Unit
DYNAMIC CHARACTERISTICS
f
IN
f
IN
f
IN
f
IN
= 1 kHz V = 3.3 V
68
69
69
62
80
74
CC
Signal−to−Noise and Distortion
SINAD
SFDR
dB
dB
(Note 4)
= 1 kHz V = 1.8 V
CC
= 1 kHz V = 3.3 V
CC
Spurious−Free Dynamic Range
(Note 4)
= 1 kHz V = 1.8 V
CC
DIGITAL INPUT/OUTPUT
High−Level Input Voltage
Low−Level Input Voltage
High−Level Output Voltage
Low−Level Output Voltage
V
V
*0.7
V
V
V
V
IH
DD
V
V
*0.3
IL
DD
2 mA drive
2 mA drive
V
OH
V
− 0.5 V
DD
V
OL
GND+0.5
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Standby current includes both digital and analog currents.
3. INL and DNL parameters were verified via bench testing and are not used for production screening.
4. SINAD and SFDR are tested at production and guaranteed by correlation to bench test results.
TIMING CHARACTERISTICS (T = 25°C unless otherwise specified)
J
Parameter
TIMING SPECIFICATIONS
Throughput
Conditions
Symbol
Min
Typ
Max
Unit
f
2
MSPS
ms
THROUGH
Cycle Time
f
0.5
CYCLE
Conversion Time
f
437.5
ns
CONV
Data Delay
1
cycle
TIMING REQUIREMENTS
Acquisition Time (CSN high)
CLK Frequency
t
62.5
ns
MHz
ns
ACQ
f
32
CLK
CLK Period
t
31.25
CLK
st
CSN Falling to 1 SCLK falling edge
t
t
15.75
15.75
ns
CSN_SCLK
SCLK_CSN
Last SCLK falling edge to CSN rising
Falling SCLK to SDO valid (Note 5)
ns
Assumed 10 pF Load
t
30
ns
SDO_VALID
5. When SCLK is running at higher frequencies, the t
of 30 ns requires SDO to be sampled on the falling edge of SCLK at the end
SDO_VALID
of the bit width just before SDO changes to the next output. This will ensure acquisition of the correct data. For example, location A shown
below would be the best place to sample SDO for the acquisition of bit 9.
tCYCLE
tAQU
tCONV
Sample: N
Sample: N+1
tSCLK_CSN
tCSN_SCLK
tSCLK
A
CSN
SCLK
OUT
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
tSDO_VALID
Data: N-1
Figure 2. Serial Interface Timing
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4
NCD98010, NCD98011
TYPICAL CHARACTERISTICS
95
90
76
75
74
73
72
71
70
69
68
THD
85
80
SNR
75
70
65
60
SNDR
67
66
0
0
0
5
10
15
20
25
30
35
35
35
−60 −40 −20
0
20
40
60
80 100
SCLK FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 3. SNR vs. SCLK Frequency
Figure 4. SNR vs. Temperature
95
90
12.0
11.8
11.6
11.4
85
80
75
11.2
11.0
10.8
10.6
70
65
60
10.4
10.2
10.0
5
10
15
20
25
30
0
5
10
15
20
25
30
35
SCLK FREQUENCY (MHz)
SCLK FREQUENCY (MHz)
Figure 5. SNDR vs. SCLK Frequency
Figure 6. ENOB vs. SCLK Frequency
95
90
45
40
35
30
25
20
15
DVDD = 3.3 V
DVDD = 1.8 V
85
80
75
70
10
65
60
5
0
5
10
15
20
25
30
−60 −40 −20
0
20
40
60
80 100
SCLK FREQUENCY (MHz)
TEMPERATURE (°C)
Figure 7. THD vs. SCLK Frequency
Figure 8. DVDD Current vs. Temperature
(SCLK = 2 kHz)
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NCD98010, NCD98011
TYPICAL CHARACTERISTICS
450
400
350
300
250
200
10
9
AVDD = 3.3 V
AVDD = 1.8 V
8
DVDD
7
6
5
4
3
2
150
100
AVDD
25
50
0
1
0
0
5
10
15
20
30
35
−60 −40 −20
0
20
40
60
80 100
SCLK (MHz)
TEMPERATURE (°C)
Figure 9. Current vs. SCLK Frequency
Figure 10. AVDD Current vs. Frequency
30
25
20
15
10
5
0
1.5
2.0
2.5
3.0
3.5
DVDD (V)
Figure 11. SDO Delay from Falling Edge of
SCLK
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NCD98010, NCD98011
TERMINOLOGY
Understanding how ADC metrics affect application
performance is key to obtaining desired performance. Key
terminology are defined below and should be used when
determining overall system performance when using the
NDC98010/1.
Positive Offset
Error
Ideal ADC
Offset and Gain Error
0
Offset and gain, if characterized, can be calibrated out post
digitization. An ideal ADC has a linear transfer function
following the equation y = m*x + b, where m is the gain and
b is the offset. Ideally the offset would be 0, and the gain
would be
Negative
Offset Error
n−1
(
)
2
m +
(eq. 1)
VinputRange
ADC Analog
Input (V)
VCM
Any deviation from an offset of 0 and the ideal gain is
considered error. Although these errors can be calibrated
out, any initial gain error reduces the ADCs dynamic range.
The plots below shows examples of these errors. Calibrating
these errors out would be achieved by adding / subtracting
codes to get the digitized output to 0 when the inputs are
Figure 13. Offset Error Example
SNR = (6.02N + 1.76) dB, where N is the number of bits.
A 12 bit converter has a theoretical SNR of 74 dB.
SINAD (or SNDR)
shorted together at V . After the offset (for signed output
CM
SINAD is the signal to noise and distortion ratio. SINAD
is the ratio of the RMS signal amplitude to the mean value
of the root sum square (RSS) of all other spectral
components, including harmonics, but excluding DC.
SINAD is useful because it provides a metric for the ADCs
overall dynamic performance, as it includes all components
which make up noise and distortion.
format) has been calibrated, samples can be taken at both
polarities to determine the gain error. The output can be
multiplied by a scale factor (after the offset has been
adjusted) to compensate for the gain error.
Positive Gain
Error
SFDR
SFDR is the Spurious Free Dynamic Range. SFDR is the
ratio of the RMS value of the signal to the RMS value of the
highest magnitude spurious signal regardless of where it
falls in the frequency spectrum. The highest spur might not
be a harmonic, though it typically is.
0
Ideal ADC
THD
THD is the total harmonic distortion, defined as ratio of
the RMS of the primary signal and the mean of the root sum
squared of all the harmonics. Generally only the first 5
harmonics are considered. The figure below shows an
example of these AC metrics in the frequency domain.
Negative Gain
Error
2
2
2
4
2
ȡ
) H ȣ
ǸH 2
) H ) H
3
ȧ
5ȧ
Ȥ
ADC Analog
Input (V)
THD + 20 log
(eq. 2)
VCM
H1
Ȣ
Figure 12. Gain Error Example
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NCD98010, NCD98011
ADC Full Scale
ADC TRANSFER FUNCTION
The NCD98010/1 offers a full input range of 0 V to VCC.
The format of the digital output is offered in an unsigned
format (NCD98010) and a signed format (NCD98011). The
ADC Input (Sinusiod)
SNR: RMS of Signal to RMS
of noise floor
output code resulting from V
and V
tied together and
INN
INP
SFDR (dBc)
Harmonics
SINAD: RMS of Signal to RMS
of noise + Harmonics
held at VCC/2 is therefore 0h000 for the NCD98011 and
0h100 for the NCD98010. This distinction is shown below
in Figures 16 and 17.
SFDR: Signal to largest non-
fundamental content
Noise Floor
NCD98010
Unsigned Output Format
THD: RMS of Signal to mean
value of RSS of its harmonics
111111111111
111111111110
111111111101
111111111100
fSAMPLE/2
Frequency
Figure 14. Spurious Free Dynamic Range in the
Frequency Domain
.
.
.
100000000001
100000000000
011111111111
011111111110
ENOB
The effective number of bits describes the dynamic range
of the ADC. It quantifies the actual resolution of the ADC
taking into account noise and distortion. ENOB typically
changes over ADC input frequency, and is an important
metric for non−DC applications. It is defined as:
.
.
.
000000000100
000000000010
000000000001
000000000000
SINAD * 1.76
ENOB +
(eq. 3)
6.02
0 LSB
− V
−Full Scale
Full Scale
V
INP
INN
THEORY OF OPERATION
The NCD98010/1 uses a successive approximation
architecture. Conversion from an analog signal to a digital
signal occurs in 2 different stages over 16 clock cycles. The
first stage is a differential sample and hold operation, where
the input Vinn and Vinp voltages are sampled onto a
differential charge re−distribution capacitive array. The
second stage implements a binary decision tree, bit cycling
through 1/2 divisions of the reference. The internal digital
control block steps through each of 12 bits to determine
whether that bit in the digital output code is higher or lower
Figure 16. NCD98010 Unsigned Output Definition
NCD98011
Signed Output Format
011111111111
011111111110
011111111101
011111111100
.
N
.
.
000000000010
000000000001
000000000000
111111111111
111111111110
than the sampled signal. V acts as the analog supply and
CC
the ADC reference. This allows for a maximum input range
of 0 V to V
.
CC
.
.
.
ADC
100000000011
100000000010
100000000001
100000000000
Sample/Hold
Bit Cycling for Current Sample and Data Transmission for Previous Sample
Operation
SCLK
CSN
0 LSB
− V
−Full Scale
Full Scale
V
INP
INN
Must be high for at least
2 clock cycles
Figure 17. NCD98011 Signed Output Definition
Figure 15. SAR ADC Internal Operation
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NCD98010, NCD98011
APPLICATION INFORMATION
The NCD98010/1 supports many application due to its small size and low power. The typical connection diagram for the
NCD98010/1 maximizing performance is shown below in Figure 18.
Input Buffer
10kΩ
Anti-Aliasing Filter
VCC
VDD
VCC
1μF
1μF
1μF
10kΩ
10kΩ
+
RCM
VCC VDD
CCM
CDIFF
INP
INN
CSN
OUT
SCLK
VCM
RCM
GND
CCM
-
NCD98010
1μF
10kΩ
Figure 18. NCD Connection Diagram
Buffering
The common mode filter cutoff frequency should be no
greater than the Nyquist frequency (F / 2). Set the
differential cutoff frequency to be one decade less than the
Many applications of the NCD98010/1 benefit by a
differential input buffer. A unity gain buffer provides current
drive to support the anti−aliasing filter and the 2 pF of ADC
input capacitance for applications where very high input
impedance is required. Input buffers also allow for control
of the common mode voltage to maximize the full scale
SAMPLE
common−mode cutoff frequency by increasing the
differential capacitor (C
) by a factor of 10 over C
.
DIFF
CM
This will help to reduce errors caused by common mode
filter component mismatch. Selecting the appropriate values
for the anti−aliasing filter is important to maintain peak
performance. Adding resistors to the signal path will
range of the ADC by setting V
to VCC/2. Input buffers
CM
are recommended for applications where the source of the
differential analog inputs require extremely high input
impedance. Noise introduced by the input buffers should be
less than the quantization noise of the ADC (74 dB SNR) to
avoid becoming the dominant noise source. Use buffers with
sufficient bandwidth (> Nyquist: F
less than 1/2 LSB to avoid introducing additional noise and
offset errors.
introduce noise. Keeping R
as small as possible will
CM
mitigate additional noise and error. The thermal noise
introduced by the filter resistors can be calculated by:
nV
Hz
+ Ǹ
/ 2) and an offset
ǒ Ǔ
Vn
4 @ k @ T @ RCM
(eq. 6)
SAMPLE
Ǹ
(3) Noise introduced by series anti−aliasing filter.
Where k = 1.38E−23 J/K (Boltzmann’s constant) and T is the
temperature in degree Kelvin.
Anti−Alias Filter
The use of 2 common mode filters in addition to a
differential filter is recommended to maintain high common
mode rejection. These anti−aliasing filter are built using
Using smaller resistors and larger capacitors to achieve
the desired cutoff frequency will help mitigate noise and
charge injection. When choosing anti−aliasing filter
components, ensure that the settling time is short enough for
the input to be within 1/2 LSB of the desired value before the
CSN goes low to begin the conversion.
R , C , and C
CM CM
as shown above in Figure 12 in the
DIFF
Anti−Aliasing Filter box. The equations for determining the
cutoff frequencies of each filter are as follows:
1
fcutoff_CM(HZ) +
(eq. 4)
(eq. 5)
2p @ RCM @ CCM
Power Supply Decoupling
Local ADC supply decoupling is essential for maintaining
high power supply rejection ratio. For the NCD98010/1, the
analog supply (VCC) is also the reference for the ADC. Any
noise or drift greater than 1/2 LSB will affect the DNL and
INL of the converter. Use local decoupling capacitors of
(1) Cutoff frequency for the common mode filters.
1
fcutoff_DIFF(HZ) +
2p @ 2RCM @ CDIFF
(2) Cutoff frequency for the differential filter.
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NCD98010, NCD98011
Minimal Component Realization
1 mF. All decoupling capacitors must connect directly to a
low impedance ground plane in order to be effective. Short
traces or vias are required to minimize additional series
inductance. Ceramic capacitors are recommended based on
their low ESR and ESL. X7R ceramic capacitors are
For applications where minimizing board space trumps
ADC performance, the NCD98010/1 connection diagram
can be reduced as shown in Figure 19 below. The removal
of the input buffering may be an option depending on the
nature of the differential analog input source. Removing the
anti−aliasing filter would come at the expense of reduced
ENOB due to the digitization of aliased signals.
recommended for applications involving
temperature range.
a
wide
Anti-Aliasing Filter
VDD
1μF
1μF
CCM
VCC VDD
+
-
INP
INN
CSN
RCM
OUT
SCLK
GND
RCM
CCM
NCD98010
Figure 19. Reduced Component Connection Diagram
Output Timing / Definition
Figure 20 below shows the NCD98010/1 output format. There is a 1 sample latency associated with the output data. The
digital data for analog input sampled are clocked out of the ADC by SCLK one conversion later, as shown in the diagram below.
Sample: N
Sample: N+1
Sample: N+2
CSN
SCLK
OUT
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data: N-1
Figure 20. NCD98010/1 Output Format
Data: N
Layout Guidelines
Ideal PCB layouts have a ground plane placed underneath
the device and the PCB is partitioned into digital and analog
sections supporting the analog inputs to the ADC on one
side, and the digital interface on the other side. To avoid the
coupling of digital noise into the analog partition, care must
be taken not to cross digital signals with the analog input
signals. Keep the analog input signals and the VCC supply
/ reference signal away from noise digital signals.
Recommended bypass capacitances should be places as
close as possible to the VCC and VDD pins, and the path to
ground needs to be a low inductance low resistance local
connection.
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NCD98010, NCD98011
PACKAGE DIMENSIONS
US8
CASE 493−02
ISSUE B
−X−
NOTES:
A
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
8
5
J
−Y−
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
DETAIL E
B
L
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED 0.0508 (0.0002 “).
1
4
R
G
S
U
P
MILLIMETERS
INCHES
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
MIN
1.90
2.20
0.60
0.17
0.20
0.50 BSC
0.40 REF
0.10
MAX
2.10
2.40
0.90
0.25
0.35
MIN
MAX
0.083
0.094
0.035
0.010
0.014
C
0.075
0.087
0.024
0.007
0.008
0.020 BSC
0.016 REF
H
−T−
0.10 (0.004)
T
K
SEATING
D
N
PLANE
R 0.10 TYP
M
0.10 (0.004)
T
X Y
0.18
0.10
3.20
6
0.004
0.007
0.004
0.126
6
V
0.00
3.00
0
0.000
0.118
0
M
_
_
_
_
5
10
5
10
_
_
_
_
0.23
0.23
0.37
0.60
0.34
0.33
0.47
0.80
0.010
0.009
0.015
0.024
0.013
0.013
0.019
0.031
F
DETAIL E
U
V
0.12 BSC
0.005 BSC
SOLDERING FOOTPRINT*
3.8
0.015
1.8
0.07
0.50
0.0197
0.30
0.012
1.0
0.0394
mm
inches
ǒ
Ǔ
SCALE 8:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
NCD98010, NCD98011
PACKAGE DIMENSIONS
X2QFN8, 1.5x1.5, 0.5P
CASE 722AM
ISSUE O
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